1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
20 let neverHasSideEffects = 1 in {
21 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
22 (ins VR128:$src1, VR128:$src2, VR128:$src3),
24 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
26 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
27 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
29 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
30 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
31 (ins VR256:$src1, VR256:$src2, VR256:$src3),
33 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
35 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
36 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
38 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
39 } // neverHasSideEffects = 1
42 // Intrinsic for 213 pattern
43 multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
44 PatFrag MemFrag128, PatFrag MemFrag256,
45 SDNode Op213, ValueType OpVT128, ValueType OpVT256> {
46 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
47 (ins VR128:$src1, VR128:$src2, VR128:$src3),
49 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
50 [(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
51 VR128:$src1, VR128:$src3)))]>;
53 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
54 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
56 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
57 [(set VR128:$dst, (OpVT128 (Op213 VR128:$src2, VR128:$src1,
58 (MemFrag128 addr:$src3))))]>;
60 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
61 (ins VR256:$src1, VR256:$src2, VR256:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
64 [(set VR256:$dst, (OpVT256 (Op213 VR256:$src2, VR256:$src1,
67 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
68 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
72 (OpVT256 (Op213 VR256:$src2, VR256:$src1,
73 (MemFrag256 addr:$src3))))]>;
75 } // Constraints = "$src1 = $dst"
77 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
78 string OpcodeStr, string PackTy,
79 PatFrag MemFrag128, PatFrag MemFrag256,
80 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
81 defm r213 : fma3p_rm_int <opc213, !strconcat(OpcodeStr,
82 !strconcat("213", PackTy)), MemFrag128, MemFrag256,
83 Op, OpTy128, OpTy256>;
84 defm r132 : fma3p_rm <opc132,
85 !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
86 defm r231 : fma3p_rm <opc231,
87 !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
91 let ExeDomain = SSEPackedSingle in {
92 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
93 memopv8f32, X86Fmadd, v4f32, v8f32>;
94 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
95 memopv8f32, X86Fmsub, v4f32, v8f32>;
96 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
97 memopv4f32, memopv8f32, X86Fmaddsub,
99 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
100 memopv4f32, memopv8f32, X86Fmsubadd,
104 let ExeDomain = SSEPackedDouble in {
105 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
106 memopv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
107 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
108 memopv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
109 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
110 memopv2f64, memopv4f64, X86Fmaddsub,
111 v2f64, v4f64>, VEX_W;
112 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
113 memopv2f64, memopv4f64, X86Fmsubadd,
114 v2f64, v4f64>, VEX_W;
117 // Fused Negative Multiply-Add
118 let ExeDomain = SSEPackedSingle in {
119 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
120 memopv8f32, X86Fnmadd, v4f32, v8f32>;
121 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
122 memopv8f32, X86Fnmsub, v4f32, v8f32>;
124 let ExeDomain = SSEPackedDouble in {
125 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
126 memopv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
127 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
128 memopv2f64, memopv4f64, X86Fnmsub, v2f64,
132 let Predicates = [HasFMA] in {
133 def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
134 (VFMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
135 def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1,
136 (memopv4f32 addr:$src3)),
137 (VFMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
138 def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
139 (VFMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
140 def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1,
141 (memopv4f32 addr:$src3)),
142 (VFMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
143 def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
144 (VFMADDSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
145 def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1,
146 (memopv4f32 addr:$src3)),
147 (VFMADDSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
148 def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
149 (VFMSUBADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
150 def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1,
151 (memopv4f32 addr:$src3)),
152 (VFMSUBADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
154 def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
155 (VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
156 def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1,
157 (memopv8f32 addr:$src3)),
158 (VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
159 def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
160 (VFMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
161 def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1,
162 (memopv8f32 addr:$src3)),
163 (VFMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
164 def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
165 (VFMADDSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
166 def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1,
167 (memopv8f32 addr:$src3)),
168 (VFMADDSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
169 def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
170 (VFMSUBADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
171 def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1,
172 (memopv8f32 addr:$src3)),
173 (VFMSUBADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
175 def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
176 (VFMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
177 def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1,
178 (memopv2f64 addr:$src3)),
179 (VFMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
180 def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
181 (VFMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
182 def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1,
183 (memopv2f64 addr:$src3)),
184 (VFMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
185 def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
186 (VFMADDSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
187 def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1,
188 (memopv2f64 addr:$src3)),
189 (VFMADDSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
190 def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
191 (VFMSUBADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
192 def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1,
193 (memopv2f64 addr:$src3)),
194 (VFMSUBADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
196 def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
197 (VFMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
198 def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1,
199 (memopv4f64 addr:$src3)),
200 (VFMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
201 def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
202 (VFMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
203 def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1,
204 (memopv4f64 addr:$src3)),
205 (VFMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
206 def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
207 (VFMADDSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
208 def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1,
209 (memopv4f64 addr:$src3)),
210 (VFMADDSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
211 def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
212 (VFMSUBADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
213 def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1,
214 (memopv4f64 addr:$src3)),
215 (VFMSUBADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
217 def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
218 (VFNMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
219 def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1,
220 (memopv4f32 addr:$src3)),
221 (VFNMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
222 def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
223 (VFNMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
224 def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1,
225 (memopv4f32 addr:$src3)),
226 (VFNMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
228 def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
229 (VFNMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
230 def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1,
231 (memopv8f32 addr:$src3)),
232 (VFNMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
233 def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
234 (VFNMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
235 def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1,
236 (memopv8f32 addr:$src3)),
237 (VFNMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
239 def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
240 (VFNMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
241 def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1,
242 (memopv2f64 addr:$src3)),
243 (VFNMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
244 def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
245 (VFNMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
246 def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1,
247 (memopv2f64 addr:$src3)),
248 (VFNMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
250 def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
251 (VFNMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
252 def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1,
253 (memopv4f64 addr:$src3)),
254 (VFNMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
255 def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
256 (VFNMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
257 def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1,
258 (memopv4f64 addr:$src3)),
259 (VFNMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
261 } // Predicates = [HasFMA]
263 let Constraints = "$src1 = $dst" in {
264 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
266 let neverHasSideEffects = 1 in {
267 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
268 (ins RC:$src1, RC:$src2, RC:$src3),
269 !strconcat(OpcodeStr,
270 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
272 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
273 (ins RC:$src1, RC:$src2, x86memop:$src3),
274 !strconcat(OpcodeStr,
275 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
276 } // neverHasSideEffects = 1
279 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
280 ComplexPattern mem_cpat, Intrinsic IntId,
281 RegisterClass RC, SDNode OpNode, ValueType OpVT> {
282 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
283 (ins VR128:$src1, VR128:$src2, VR128:$src3),
284 !strconcat(OpcodeStr,
285 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
286 [(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
288 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
289 (ins VR128:$src1, VR128:$src2, memop:$src3),
290 !strconcat(OpcodeStr,
291 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
293 (IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
294 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
295 (ins RC:$src1, RC:$src2, RC:$src3),
296 !strconcat(OpcodeStr,
297 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
299 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
301 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
302 (ins RC:$src1, RC:$src2, memop:$src3),
303 !strconcat(OpcodeStr,
304 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
306 } // Constraints = "$src1 = $dst"
308 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
309 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
311 defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>;
312 defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>;
313 defm SDr132 : fma3s_rm<opc132, !strconcat(OpStr, "132sd"), f64mem, FR64>,
315 defm SDr231 : fma3s_rm<opc231, !strconcat(OpStr, "231sd"), f64mem, FR64>,
317 defm SSr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213ss"), ssmem,
318 sse_load_f32, IntF32, FR32, OpNode, f32>;
319 defm SDr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213sd"), sdmem,
320 sse_load_f64, IntF64, FR64, OpNode, f64>, VEX_W;
323 defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
324 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
325 defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
326 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
328 defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
329 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
330 defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
331 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
334 //===----------------------------------------------------------------------===//
335 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
336 //===----------------------------------------------------------------------===//
339 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
340 ComplexPattern mem_cpat, Intrinsic Int> {
341 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
342 (ins VR128:$src1, VR128:$src2, VR128:$src3),
343 !strconcat(OpcodeStr,
344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
346 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
347 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
348 (ins VR128:$src1, VR128:$src2, memop:$src3),
349 !strconcat(OpcodeStr,
350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
352 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
353 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
354 (ins VR128:$src1, memop:$src2, VR128:$src3),
355 !strconcat(OpcodeStr,
356 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
358 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
360 let isCodeGenOnly = 1 in
361 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
362 (ins VR128:$src1, VR128:$src2, VR128:$src3),
363 !strconcat(OpcodeStr,
364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
367 multiclass fma4p<bits<8> opc, string OpcodeStr,
368 Intrinsic Int128, Intrinsic Int256,
369 PatFrag ld_frag128, PatFrag ld_frag256> {
370 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
371 (ins VR128:$src1, VR128:$src2, VR128:$src3),
372 !strconcat(OpcodeStr,
373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
375 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
376 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
377 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
378 !strconcat(OpcodeStr,
379 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
380 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
381 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
382 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
383 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
384 !strconcat(OpcodeStr,
385 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
387 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
388 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
389 (ins VR256:$src1, VR256:$src2, VR256:$src3),
390 !strconcat(OpcodeStr,
391 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
393 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
394 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
395 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
396 !strconcat(OpcodeStr,
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
398 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
399 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
400 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
401 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
402 !strconcat(OpcodeStr,
403 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
405 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
407 let isCodeGenOnly = 1 in {
408 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
409 (ins VR128:$src1, VR128:$src2, VR128:$src3),
410 !strconcat(OpcodeStr,
411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
412 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
413 (ins VR256:$src1, VR256:$src2, VR256:$src3),
414 !strconcat(OpcodeStr,
415 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
416 } // isCodeGenOnly = 1
419 let Predicates = [HasFMA4] in {
421 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
422 int_x86_fma_vfmadd_ss>;
423 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
424 int_x86_fma_vfmadd_sd>;
425 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma_vfmadd_ps,
426 int_x86_fma_vfmadd_ps_256, memopv4f32, memopv8f32>;
427 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma_vfmadd_pd,
428 int_x86_fma_vfmadd_pd_256, memopv2f64, memopv4f64>;
429 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
430 int_x86_fma_vfmsub_ss>;
431 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
432 int_x86_fma_vfmsub_sd>;
433 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma_vfmsub_ps,
434 int_x86_fma_vfmsub_ps_256, memopv4f32, memopv8f32>;
435 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma_vfmsub_pd,
436 int_x86_fma_vfmsub_pd_256, memopv2f64, memopv4f64>;
437 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
438 int_x86_fma_vfnmadd_ss>;
439 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
440 int_x86_fma_vfnmadd_sd>;
441 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma_vfnmadd_ps,
442 int_x86_fma_vfnmadd_ps_256, memopv4f32, memopv8f32>;
443 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma_vfnmadd_pd,
444 int_x86_fma_vfnmadd_pd_256, memopv2f64, memopv4f64>;
445 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
446 int_x86_fma_vfnmsub_ss>;
447 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
448 int_x86_fma_vfnmsub_sd>;
449 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma_vfnmsub_ps,
450 int_x86_fma_vfnmsub_ps_256, memopv4f32, memopv8f32>;
451 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma_vfnmsub_pd,
452 int_x86_fma_vfnmsub_pd_256, memopv2f64, memopv4f64>;
453 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma_vfmaddsub_ps,
454 int_x86_fma_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
455 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma_vfmaddsub_pd,
456 int_x86_fma_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
457 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma_vfmsubadd_ps,
458 int_x86_fma_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
459 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma_vfmsubadd_pd,
460 int_x86_fma_vfmsubadd_pd_256, memopv2f64, memopv4f64>;