1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
20 PatFrag MemFrag128, PatFrag MemFrag256,
21 ValueType OpVT128, ValueType OpVT256,
22 bit IsRVariantCommutable = 0, bit IsMVariantCommutable = 0,
23 SDPatternOperator Op = null_frag> {
24 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in
25 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
26 (ins VR128:$src1, VR128:$src2, VR128:$src3),
28 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
29 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
30 VR128:$src1, VR128:$src3)))]>;
32 let mayLoad = 1, isCommutable = IsMVariantCommutable in
33 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
34 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
36 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
37 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
38 (MemFrag128 addr:$src3))))]>;
40 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in
41 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
42 (ins VR256:$src1, VR256:$src2, VR256:$src3),
44 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
45 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
46 VR256:$src3)))]>, VEX_L;
48 let mayLoad = 1, isCommutable = IsMVariantCommutable in
49 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
50 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
52 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
54 (OpVT256 (Op VR256:$src2, VR256:$src1,
55 (MemFrag256 addr:$src3))))]>, VEX_L;
57 } // Constraints = "$src1 = $dst"
59 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
60 string OpcodeStr, string PackTy,
61 PatFrag MemFrag128, PatFrag MemFrag256,
62 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
63 // For 213, both the register and memory variant are commutable.
64 // Indeed, the commutable operands are 1 and 2 and both live in registers
66 defm r213 : fma3p_rm<opc213,
67 !strconcat(OpcodeStr, "213", PackTy),
68 MemFrag128, MemFrag256, OpTy128, OpTy256,
69 /* IsRVariantCommutable */ 1,
70 /* IsMVariantCommutable */ 1,
72 let hasSideEffects = 0 in {
73 defm r132 : fma3p_rm<opc132,
74 !strconcat(OpcodeStr, "132", PackTy),
75 MemFrag128, MemFrag256, OpTy128, OpTy256>;
76 // For 231, only the register variant is commutable.
77 // For the memory variant the folded operand must be in 3. Thus,
78 // in that case, it cannot be swapped with 2.
79 defm r231 : fma3p_rm<opc231,
80 !strconcat(OpcodeStr, "231", PackTy),
81 MemFrag128, MemFrag256, OpTy128, OpTy256,
82 /* IsRVariantCommutable */ 1,
83 /* IsMVariantCommutable */ 0>;
84 } // hasSideEffects = 0
88 let ExeDomain = SSEPackedSingle in {
89 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32,
90 loadv8f32, X86Fmadd, v4f32, v8f32>;
91 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32,
92 loadv8f32, X86Fmsub, v4f32, v8f32>;
93 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
94 loadv4f32, loadv8f32, X86Fmaddsub,
96 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
97 loadv4f32, loadv8f32, X86Fmsubadd,
101 let ExeDomain = SSEPackedDouble in {
102 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64,
103 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
104 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64,
105 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
106 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
107 loadv2f64, loadv4f64, X86Fmaddsub,
108 v2f64, v4f64>, VEX_W;
109 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
110 loadv2f64, loadv4f64, X86Fmsubadd,
111 v2f64, v4f64>, VEX_W;
114 // Fused Negative Multiply-Add
115 let ExeDomain = SSEPackedSingle in {
116 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32,
117 loadv8f32, X86Fnmadd, v4f32, v8f32>;
118 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32,
119 loadv8f32, X86Fnmsub, v4f32, v8f32>;
121 let ExeDomain = SSEPackedDouble in {
122 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64,
123 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
124 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
125 loadv2f64, loadv4f64, X86Fnmsub, v2f64,
129 let Constraints = "$src1 = $dst" in {
130 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
131 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
132 bit IsRVariantCommutable = 0, bit IsMVariantCommutable = 0,
133 SDPatternOperator OpNode = null_frag> {
134 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in
135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
136 (ins RC:$src1, RC:$src2, RC:$src3),
137 !strconcat(OpcodeStr,
138 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
142 let mayLoad = 1, isCommutable = IsMVariantCommutable in
143 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
144 (ins RC:$src1, RC:$src2, x86memop:$src3),
145 !strconcat(OpcodeStr,
146 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
148 (OpVT (OpNode RC:$src2, RC:$src1,
149 (mem_frag addr:$src3))))]>;
151 } // Constraints = "$src1 = $dst"
153 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
154 string OpStr, string PackTy, string PT2, Intrinsic Int,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
156 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
157 ComplexPattern mem_cpat> {
158 let hasSideEffects = 0 in {
159 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
160 x86memop, RC, OpVT, mem_frag>;
161 // See the other defm of r231 for the explanation regarding the
163 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy),
164 x86memop, RC, OpVT, mem_frag,
165 /* IsRVariantCommutable */ 1,
166 /* IsMVariantCommutable */ 0>;
169 // See the other defm of r213 for the explanation regarding the
171 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy),
172 x86memop, RC, OpVT, mem_frag,
173 /* IsRVariantCommutable */ 1,
174 /* IsMVariantCommutable */ 1,
178 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
179 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
181 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", IntF32, OpNode,
182 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
183 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode,
184 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
186 // These patterns use the 123 ordering, instead of 213, even though
187 // they match the intrinsic to the 213 version of the instruction.
188 // This is because src1 is tied to dest, and the scalar intrinsics
189 // require the pass-through values to come from the first source
190 // operand, not the second.
191 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
193 (!cast<Instruction>(NAME#"SSr213r")
194 (COPY_TO_REGCLASS $src1, FR32),
195 (COPY_TO_REGCLASS $src2, FR32),
196 (COPY_TO_REGCLASS $src3, FR32)),
199 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
201 (!cast<Instruction>(NAME#"SDr213r")
202 (COPY_TO_REGCLASS $src1, FR64),
203 (COPY_TO_REGCLASS $src2, FR64),
204 (COPY_TO_REGCLASS $src3, FR64)),
208 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
209 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
210 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
211 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
213 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
214 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
215 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
216 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
219 //===----------------------------------------------------------------------===//
220 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
221 //===----------------------------------------------------------------------===//
224 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
225 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
227 let isCommutable = 1 in
228 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
229 (ins RC:$src1, RC:$src2, RC:$src3),
230 !strconcat(OpcodeStr,
231 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
233 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
234 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
235 (ins RC:$src1, RC:$src2, x86memop:$src3),
236 !strconcat(OpcodeStr,
237 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
238 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
239 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
240 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
241 (ins RC:$src1, x86memop:$src2, RC:$src3),
242 !strconcat(OpcodeStr,
243 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
245 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
247 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
248 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
249 (ins RC:$src1, RC:$src2, RC:$src3),
250 !strconcat(OpcodeStr,
251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
255 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
256 ComplexPattern mem_cpat, Intrinsic Int> {
257 let isCodeGenOnly = 1 in {
258 let isCommutable = 1 in
259 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
260 (ins VR128:$src1, VR128:$src2, VR128:$src3),
261 !strconcat(OpcodeStr,
262 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
264 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
265 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
266 (ins VR128:$src1, VR128:$src2, memop:$src3),
267 !strconcat(OpcodeStr,
268 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
269 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
270 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4;
271 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
272 (ins VR128:$src1, memop:$src2, VR128:$src3),
273 !strconcat(OpcodeStr,
274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
276 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
277 } // isCodeGenOnly = 1
280 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
281 ValueType OpVT128, ValueType OpVT256,
282 PatFrag ld_frag128, PatFrag ld_frag256> {
283 let isCommutable = 1 in
284 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
285 (ins VR128:$src1, VR128:$src2, VR128:$src3),
286 !strconcat(OpcodeStr,
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
289 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
291 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
292 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
293 !strconcat(OpcodeStr,
294 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
296 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
297 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
298 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
299 !strconcat(OpcodeStr,
300 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
302 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
303 let isCommutable = 1 in
304 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
305 (ins VR256:$src1, VR256:$src2, VR256:$src3),
306 !strconcat(OpcodeStr,
307 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
309 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
310 VEX_W, MemOp4, VEX_L;
311 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
312 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
313 !strconcat(OpcodeStr,
314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
315 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
316 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L;
317 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
318 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
319 !strconcat(OpcodeStr,
320 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
321 [(set VR256:$dst, (OpNode VR256:$src1,
322 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
324 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
325 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
326 (ins VR128:$src1, VR128:$src2, VR128:$src3),
327 !strconcat(OpcodeStr,
328 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
329 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
330 (ins VR256:$src1, VR256:$src2, VR256:$src3),
331 !strconcat(OpcodeStr,
332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
334 } // isCodeGenOnly = 1
337 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
338 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
339 int_x86_fma_vfmadd_ss>;
340 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
341 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
342 int_x86_fma_vfmadd_sd>;
343 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
344 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
345 int_x86_fma_vfmsub_ss>;
346 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
347 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
348 int_x86_fma_vfmsub_sd>;
349 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
351 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
352 int_x86_fma_vfnmadd_ss>;
353 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
355 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
356 int_x86_fma_vfnmadd_sd>;
357 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
359 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
360 int_x86_fma_vfnmsub_ss>;
361 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
363 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
364 int_x86_fma_vfnmsub_sd>;
366 let ExeDomain = SSEPackedSingle in {
367 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
368 loadv4f32, loadv8f32>;
369 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
370 loadv4f32, loadv8f32>;
371 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
372 loadv4f32, loadv8f32>;
373 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
374 loadv4f32, loadv8f32>;
375 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
376 loadv4f32, loadv8f32>;
377 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
378 loadv4f32, loadv8f32>;
381 let ExeDomain = SSEPackedDouble in {
382 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
383 loadv2f64, loadv4f64>;
384 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
385 loadv2f64, loadv4f64>;
386 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
387 loadv2f64, loadv4f64>;
388 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
389 loadv2f64, loadv4f64>;
390 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
391 loadv2f64, loadv4f64>;
392 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
393 loadv2f64, loadv4f64>;