1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
20 let neverHasSideEffects = 1 in {
21 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
22 (ins VR128:$src1, VR128:$src2, VR128:$src3),
23 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
26 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
27 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
28 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
30 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
31 (ins VR256:$src1, VR256:$src2, VR256:$src3),
32 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
35 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
36 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
37 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
39 } // neverHasSideEffects = 1
42 // Intrinsic for 132 pattern
43 multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
44 PatFrag MemFrag128, PatFrag MemFrag256,
45 Intrinsic Int128, Intrinsic Int256> {
46 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
47 (ins VR128:$src1, VR128:$src2, VR128:$src3),
48 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
49 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src3, VR128:$src2))]>;
50 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
51 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
52 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
54 (Int128 VR128:$src1, (MemFrag128 addr:$src3), VR128:$src2))]>;
55 def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
56 (ins VR256:$src1, VR256:$src2, VR256:$src3),
57 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
58 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src3, VR256:$src2))]>;
59 def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
60 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
61 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 (Int256 VR256:$src1, (MemFrag256 addr:$src3), VR256:$src2))]>;
65 } // Constraints = "$src1 = $dst"
67 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
68 string OpcodeStr, string PackTy,
69 PatFrag MemFrag128, PatFrag MemFrag256,
70 Intrinsic Int128, Intrinsic Int256> {
71 defm r132 : fma3p_rm_int <opc132, !strconcat(OpcodeStr,
72 !strconcat("132", PackTy)), MemFrag128, MemFrag256,
74 defm r132 : fma3p_rm <opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
75 defm r213 : fma3p_rm <opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
76 defm r231 : fma3p_rm <opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
80 let ExeDomain = SSEPackedSingle in {
81 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
82 memopv8f32, int_x86_fma_vfmadd_ps, int_x86_fma_vfmadd_ps_256>;
83 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
84 memopv8f32, int_x86_fma_vfmsub_ps, int_x86_fma_vfmsub_ps_256>;
85 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
86 memopv4f32, memopv8f32, int_x86_fma_vfmaddsub_ps,
87 int_x86_fma_vfmaddsub_ps_256>;
88 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
89 memopv4f32, memopv8f32, int_x86_fma_vfmsubadd_ps,
90 int_x86_fma_vfmaddsub_ps_256>;
93 let ExeDomain = SSEPackedDouble in {
94 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
95 memopv4f64, int_x86_fma_vfmadd_pd, int_x86_fma_vfmadd_pd_256>, VEX_W;
96 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
97 memopv4f64, int_x86_fma_vfmsub_pd, int_x86_fma_vfmsub_pd_256>, VEX_W;
98 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", memopv2f64,
99 memopv4f64, int_x86_fma_vfmaddsub_pd, int_x86_fma_vfmaddsub_pd_256>, VEX_W;
100 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", memopv2f64,
101 memopv4f64, int_x86_fma_vfmsubadd_pd, int_x86_fma_vfmsubadd_pd_256>, VEX_W;
104 // Fused Negative Multiply-Add
105 let ExeDomain = SSEPackedSingle in {
106 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
107 memopv8f32, int_x86_fma_vfnmadd_ps, int_x86_fma_vfnmadd_ps_256>;
108 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
109 memopv8f32, int_x86_fma_vfnmsub_ps, int_x86_fma_vfnmsub_ps_256>;
111 let ExeDomain = SSEPackedDouble in {
112 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
113 memopv4f64, int_x86_fma_vfnmadd_pd, int_x86_fma_vfnmadd_pd_256>, VEX_W;
114 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", memopv2f64,
115 memopv4f64, int_x86_fma_vfnmsub_pd, int_x86_fma_vfnmsub_pd_256>, VEX_W;
119 let Constraints = "$src1 = $dst" in {
120 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
122 let neverHasSideEffects = 1 in {
123 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
124 (ins RC:$src1, RC:$src2, RC:$src3),
125 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
128 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
129 (ins RC:$src1, RC:$src2, x86memop:$src3),
130 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
132 } // neverHasSideEffects = 1
135 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
136 ComplexPattern mem_cpat, Intrinsic IntId> {
137 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
138 (ins VR128:$src1, VR128:$src2, VR128:$src3),
139 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
140 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src3, VR128:$src2))]>;
141 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
142 (ins VR128:$src1, VR128:$src2, memop:$src3),
143 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
145 (IntId VR128:$src1, mem_cpat:$src3, VR128:$src2))]>;
147 } // Constraints = "$src1 = $dst"
149 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
150 string OpStr, Intrinsic IntF32, Intrinsic IntF64> {
151 defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>;
152 defm SSr213 : fma3s_rm<opc213, !strconcat(OpStr, "213ss"), f32mem, FR32>;
153 defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>;
154 defm SDr132 : fma3s_rm<opc132, !strconcat(OpStr, "132sd"), f64mem, FR64>, VEX_W;
155 defm SDr213 : fma3s_rm<opc213, !strconcat(OpStr, "213sd"), f64mem, FR64>, VEX_W;
156 defm SDr231 : fma3s_rm<opc231, !strconcat(OpStr, "231sd"), f64mem, FR64>, VEX_W;
157 defm SSr132 : fma3s_rm_int <opc132, !strconcat(OpStr, "132ss"), ssmem,
158 sse_load_f32, IntF32>;
159 defm SDr132 : fma3s_rm_int <opc132, !strconcat(OpStr, "132sd"), sdmem,
160 sse_load_f64, IntF64>;
163 defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
164 int_x86_fma_vfmadd_sd>, VEX_LIG;
165 defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
166 int_x86_fma_vfmsub_sd>, VEX_LIG;
168 defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
169 int_x86_fma_vfnmadd_sd>, VEX_LIG;
170 defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
171 int_x86_fma_vfnmsub_sd>, VEX_LIG;
174 //===----------------------------------------------------------------------===//
175 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
176 //===----------------------------------------------------------------------===//
179 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
180 ComplexPattern mem_cpat, Intrinsic Int> {
181 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
182 (ins VR128:$src1, VR128:$src2, VR128:$src3),
183 !strconcat(OpcodeStr,
184 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
186 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
187 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
188 (ins VR128:$src1, VR128:$src2, memop:$src3),
189 !strconcat(OpcodeStr,
190 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
192 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
193 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
194 (ins VR128:$src1, memop:$src2, VR128:$src3),
195 !strconcat(OpcodeStr,
196 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
198 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
200 let isCodeGenOnly = 1 in
201 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
202 (ins VR128:$src1, VR128:$src2, VR128:$src3),
203 !strconcat(OpcodeStr,
204 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
207 multiclass fma4p<bits<8> opc, string OpcodeStr,
208 Intrinsic Int128, Intrinsic Int256,
209 PatFrag ld_frag128, PatFrag ld_frag256> {
210 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
211 (ins VR128:$src1, VR128:$src2, VR128:$src3),
212 !strconcat(OpcodeStr,
213 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
215 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
216 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
217 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
218 !strconcat(OpcodeStr,
219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
221 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
222 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
223 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
224 !strconcat(OpcodeStr,
225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
227 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
228 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
229 (ins VR256:$src1, VR256:$src2, VR256:$src3),
230 !strconcat(OpcodeStr,
231 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
233 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
234 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
235 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
236 !strconcat(OpcodeStr,
237 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
238 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
239 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
240 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
241 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
242 !strconcat(OpcodeStr,
243 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
245 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
247 let isCodeGenOnly = 1 in {
248 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
249 (ins VR128:$src1, VR128:$src2, VR128:$src3),
250 !strconcat(OpcodeStr,
251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
252 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
253 (ins VR256:$src1, VR256:$src2, VR256:$src3),
254 !strconcat(OpcodeStr,
255 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
256 } // isCodeGenOnly = 1
259 let Predicates = [HasFMA4] in {
261 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
262 int_x86_fma_vfmadd_ss>;
263 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
264 int_x86_fma_vfmadd_sd>;
265 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma_vfmadd_ps,
266 int_x86_fma_vfmadd_ps_256, memopv4f32, memopv8f32>;
267 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma_vfmadd_pd,
268 int_x86_fma_vfmadd_pd_256, memopv2f64, memopv4f64>;
269 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
270 int_x86_fma_vfmsub_ss>;
271 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
272 int_x86_fma_vfmsub_sd>;
273 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma_vfmsub_ps,
274 int_x86_fma_vfmsub_ps_256, memopv4f32, memopv8f32>;
275 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma_vfmsub_pd,
276 int_x86_fma_vfmsub_pd_256, memopv2f64, memopv4f64>;
277 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
278 int_x86_fma_vfnmadd_ss>;
279 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
280 int_x86_fma_vfnmadd_sd>;
281 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma_vfnmadd_ps,
282 int_x86_fma_vfnmadd_ps_256, memopv4f32, memopv8f32>;
283 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma_vfnmadd_pd,
284 int_x86_fma_vfnmadd_pd_256, memopv2f64, memopv4f64>;
285 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
286 int_x86_fma_vfnmsub_ss>;
287 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
288 int_x86_fma_vfnmsub_sd>;
289 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma_vfnmsub_ps,
290 int_x86_fma_vfnmsub_ps_256, memopv4f32, memopv8f32>;
291 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma_vfnmsub_pd,
292 int_x86_fma_vfnmsub_pd_256, memopv2f64, memopv4f64>;
293 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma_vfmaddsub_ps,
294 int_x86_fma_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
295 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma_vfmaddsub_pd,
296 int_x86_fma_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
297 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma_vfmsubadd_ps,
298 int_x86_fma_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
299 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma_vfmsubadd_pd,
300 int_x86_fma_vfmsubadd_pd_256, memopv2f64, memopv4f64>;