1 //====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 multiclass fma_rm<bits<8> opc, string OpcodeStr> {
19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
20 (ins VR128:$src1, VR128:$src2),
21 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
23 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
24 (ins VR128:$src1, f128mem:$src2),
25 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
27 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
28 (ins VR256:$src1, VR256:$src2),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
31 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
32 (ins VR256:$src1, f256mem:$src2),
33 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
37 multiclass fma_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
38 string OpcodeStr, string PackTy> {
39 defm r132 : fma_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
40 defm r213 : fma_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
41 defm r231 : fma_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
44 let isAsmParserOnly = 1 in {
46 defm VFMADDPS : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
47 defm VFMADDPD : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
48 defm VFMADDSUBPS : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
49 defm VFMADDSUBPD : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
50 defm VFMSUBADDPS : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
51 defm VFMSUBADDPD : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
52 defm VFMSUBPS : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
53 defm VFMSUBPD : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
55 // Fused Negative Multiply-Add
56 defm VFNMADDPS : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
57 defm VFNMADDPD : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
58 defm VFNMSUBPS : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
59 defm VFNMSUBPD : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
62 //===----------------------------------------------------------------------===//
63 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
64 //===----------------------------------------------------------------------===//
67 multiclass fma4s<bits<8> opc, string OpcodeStr> {
68 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
69 (ins VR128:$src1, VR128:$src2, VR128:$src3),
71 "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
73 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
74 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
76 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
78 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
79 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
81 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
86 let isAsmParserOnly = 1 in {
87 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd">;
90 // FMA4 Intrinsics patterns
92 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
93 (VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
94 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2,
95 (alignedloadv2f64 addr:$src3)),
96 (VFMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
97 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
99 (VFMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;