1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
20 PatFrag MemFrag128, PatFrag MemFrag256,
21 ValueType OpVT128, ValueType OpVT256,
22 SDPatternOperator Op = null_frag> {
23 let usesCustomInserter = 1 in
24 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
25 (ins VR128:$src1, VR128:$src2, VR128:$src3),
27 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
28 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
29 VR128:$src1, VR128:$src3)))]>;
32 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
33 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
35 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
36 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
37 (MemFrag128 addr:$src3))))]>;
39 let usesCustomInserter = 1 in
40 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
41 (ins VR256:$src1, VR256:$src2, VR256:$src3),
43 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
44 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
45 VR256:$src3)))]>, VEX_L;
48 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
49 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
51 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
53 (OpVT256 (Op VR256:$src2, VR256:$src1,
54 (MemFrag256 addr:$src3))))]>, VEX_L;
56 } // Constraints = "$src1 = $dst"
58 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
59 string OpcodeStr, string PackTy,
60 PatFrag MemFrag128, PatFrag MemFrag256,
61 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
62 let isCommutable = 1 in
63 defm r213 : fma3p_rm<opc213,
64 !strconcat(OpcodeStr, "213", PackTy),
65 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
66 let neverHasSideEffects = 1 in {
67 defm r132 : fma3p_rm<opc132,
68 !strconcat(OpcodeStr, "132", PackTy),
69 MemFrag128, MemFrag256, OpTy128, OpTy256>;
70 defm r231 : fma3p_rm<opc231,
71 !strconcat(OpcodeStr, "231", PackTy),
72 MemFrag128, MemFrag256, OpTy128, OpTy256>;
73 } // neverHasSideEffects = 1
77 let ExeDomain = SSEPackedSingle in {
78 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32,
79 loadv8f32, X86Fmadd, v4f32, v8f32>;
80 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32,
81 loadv8f32, X86Fmsub, v4f32, v8f32>;
82 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
83 loadv4f32, loadv8f32, X86Fmaddsub,
85 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
86 loadv4f32, loadv8f32, X86Fmsubadd,
90 let ExeDomain = SSEPackedDouble in {
91 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64,
92 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
93 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64,
94 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
95 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
96 loadv2f64, loadv4f64, X86Fmaddsub,
98 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
99 loadv2f64, loadv4f64, X86Fmsubadd,
100 v2f64, v4f64>, VEX_W;
103 // Fused Negative Multiply-Add
104 let ExeDomain = SSEPackedSingle in {
105 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32,
106 loadv8f32, X86Fnmadd, v4f32, v8f32>;
107 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32,
108 loadv8f32, X86Fnmsub, v4f32, v8f32>;
110 let ExeDomain = SSEPackedDouble in {
111 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64,
112 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
113 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
114 loadv2f64, loadv4f64, X86Fnmsub, v2f64,
118 let Constraints = "$src1 = $dst" in {
119 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
120 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
121 SDPatternOperator OpNode = null_frag> {
122 let usesCustomInserter = 1 in
123 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
124 (ins RC:$src1, RC:$src2, RC:$src3),
125 !strconcat(OpcodeStr,
126 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
128 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
131 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
132 (ins RC:$src1, RC:$src2, x86memop:$src3),
133 !strconcat(OpcodeStr,
134 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
136 (OpVT (OpNode RC:$src2, RC:$src1,
137 (mem_frag addr:$src3))))]>;
139 } // Constraints = "$src1 = $dst"
141 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
142 string OpStr, string PackTy, string PT2, Intrinsic Int,
143 SDNode OpNode, RegisterClass RC, ValueType OpVT,
144 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
145 ComplexPattern mem_cpat> {
146 let neverHasSideEffects = 1 in {
147 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
148 x86memop, RC, OpVT, mem_frag>;
149 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy),
150 x86memop, RC, OpVT, mem_frag>;
153 let isCommutable = 1 in
154 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy),
155 x86memop, RC, OpVT, mem_frag, OpNode>;
158 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
159 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
161 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", IntF32, OpNode,
162 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
163 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode,
164 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
166 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
168 (!cast<Instruction>(NAME#"SSr213r")
169 (COPY_TO_REGCLASS $src2, FR32),
170 (COPY_TO_REGCLASS $src1, FR32),
171 (COPY_TO_REGCLASS $src3, FR32)),
174 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
176 (!cast<Instruction>(NAME#"SDr213r")
177 (COPY_TO_REGCLASS $src2, FR64),
178 (COPY_TO_REGCLASS $src1, FR64),
179 (COPY_TO_REGCLASS $src3, FR64)),
183 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
184 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
185 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
186 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
188 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
189 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
190 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
191 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
194 //===----------------------------------------------------------------------===//
195 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
196 //===----------------------------------------------------------------------===//
199 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
200 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
202 let isCommutable = 1 in
203 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
204 (ins RC:$src1, RC:$src2, RC:$src3),
205 !strconcat(OpcodeStr,
206 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
208 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
209 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
210 (ins RC:$src1, RC:$src2, x86memop:$src3),
211 !strconcat(OpcodeStr,
212 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
213 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
214 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
215 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
216 (ins RC:$src1, x86memop:$src2, RC:$src3),
217 !strconcat(OpcodeStr,
218 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
222 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
223 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
224 (ins RC:$src1, RC:$src2, RC:$src3),
225 !strconcat(OpcodeStr,
226 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
230 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
231 ComplexPattern mem_cpat, Intrinsic Int> {
232 let isCodeGenOnly = 1 in {
233 let isCommutable = 1 in
234 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
235 (ins VR128:$src1, VR128:$src2, VR128:$src3),
236 !strconcat(OpcodeStr,
237 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
239 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
240 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
241 (ins VR128:$src1, VR128:$src2, memop:$src3),
242 !strconcat(OpcodeStr,
243 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
244 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
245 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4;
246 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
247 (ins VR128:$src1, memop:$src2, VR128:$src3),
248 !strconcat(OpcodeStr,
249 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
252 } // isCodeGenOnly = 1
255 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
256 ValueType OpVT128, ValueType OpVT256,
257 PatFrag ld_frag128, PatFrag ld_frag256> {
258 let isCommutable = 1 in
259 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
260 (ins VR128:$src1, VR128:$src2, VR128:$src3),
261 !strconcat(OpcodeStr,
262 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
264 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
266 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
267 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
268 !strconcat(OpcodeStr,
269 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
270 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
271 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
272 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
273 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
274 !strconcat(OpcodeStr,
275 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
277 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
278 let isCommutable = 1 in
279 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
280 (ins VR256:$src1, VR256:$src2, VR256:$src3),
281 !strconcat(OpcodeStr,
282 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
284 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
285 VEX_W, MemOp4, VEX_L;
286 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
287 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
288 !strconcat(OpcodeStr,
289 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
290 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
291 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L;
292 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
293 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
294 !strconcat(OpcodeStr,
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
296 [(set VR256:$dst, (OpNode VR256:$src1,
297 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
299 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
300 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
301 (ins VR128:$src1, VR128:$src2, VR128:$src3),
302 !strconcat(OpcodeStr,
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
304 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
305 (ins VR256:$src1, VR256:$src2, VR256:$src3),
306 !strconcat(OpcodeStr,
307 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
309 } // isCodeGenOnly = 1
312 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
313 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
314 int_x86_fma_vfmadd_ss>;
315 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
316 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
317 int_x86_fma_vfmadd_sd>;
318 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
319 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
320 int_x86_fma_vfmsub_ss>;
321 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
322 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
323 int_x86_fma_vfmsub_sd>;
324 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
326 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
327 int_x86_fma_vfnmadd_ss>;
328 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
330 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
331 int_x86_fma_vfnmadd_sd>;
332 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
334 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
335 int_x86_fma_vfnmsub_ss>;
336 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
338 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
339 int_x86_fma_vfnmsub_sd>;
341 let ExeDomain = SSEPackedSingle in {
342 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
343 loadv4f32, loadv8f32>;
344 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
345 loadv4f32, loadv8f32>;
346 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
347 loadv4f32, loadv8f32>;
348 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
349 loadv4f32, loadv8f32>;
350 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
351 loadv4f32, loadv8f32>;
352 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
353 loadv4f32, loadv8f32>;
356 let ExeDomain = SSEPackedDouble in {
357 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
358 loadv2f64, loadv4f64>;
359 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
360 loadv2f64, loadv4f64>;
361 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
362 loadv2f64, loadv4f64>;
363 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
364 loadv2f64, loadv4f64>;
365 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
366 loadv2f64, loadv4f64>;
367 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
368 loadv2f64, loadv4f64>;