1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
20 PatFrag MemFrag128, PatFrag MemFrag256,
21 ValueType OpVT128, ValueType OpVT256,
22 SDPatternOperator Op = null_frag> {
23 let usesCustomInserter = 1 in
24 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
25 (ins VR128:$src1, VR128:$src2, VR128:$src3),
27 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
28 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
29 VR128:$src1, VR128:$src3)))]>;
32 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
33 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
35 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
36 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
37 (MemFrag128 addr:$src3))))]>;
39 let usesCustomInserter = 1 in
40 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
41 (ins VR256:$src1, VR256:$src2, VR256:$src3),
43 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
44 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
45 VR256:$src3)))]>, VEX_L;
48 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
49 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
51 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
53 (OpVT256 (Op VR256:$src2, VR256:$src1,
54 (MemFrag256 addr:$src3))))]>, VEX_L;
56 } // Constraints = "$src1 = $dst"
58 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
59 string OpcodeStr, string PackTy,
60 PatFrag MemFrag128, PatFrag MemFrag256,
61 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
62 let isCommutable = 1 in
63 defm r213 : fma3p_rm<opc213,
64 !strconcat(OpcodeStr, "213", PackTy),
65 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
66 let neverHasSideEffects = 1 in {
67 defm r132 : fma3p_rm<opc132,
68 !strconcat(OpcodeStr, "132", PackTy),
69 MemFrag128, MemFrag256, OpTy128, OpTy256>;
70 let isCommutable = 1 in
71 defm r231 : fma3p_rm<opc231,
72 !strconcat(OpcodeStr, "231", PackTy),
73 MemFrag128, MemFrag256, OpTy128, OpTy256>;
74 } // neverHasSideEffects = 1
78 let ExeDomain = SSEPackedSingle in {
79 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32,
80 loadv8f32, X86Fmadd, v4f32, v8f32>;
81 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32,
82 loadv8f32, X86Fmsub, v4f32, v8f32>;
83 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
84 loadv4f32, loadv8f32, X86Fmaddsub,
86 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
87 loadv4f32, loadv8f32, X86Fmsubadd,
91 let ExeDomain = SSEPackedDouble in {
92 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64,
93 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
94 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64,
95 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
96 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
97 loadv2f64, loadv4f64, X86Fmaddsub,
99 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
100 loadv2f64, loadv4f64, X86Fmsubadd,
101 v2f64, v4f64>, VEX_W;
104 // Fused Negative Multiply-Add
105 let ExeDomain = SSEPackedSingle in {
106 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32,
107 loadv8f32, X86Fnmadd, v4f32, v8f32>;
108 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32,
109 loadv8f32, X86Fnmsub, v4f32, v8f32>;
111 let ExeDomain = SSEPackedDouble in {
112 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64,
113 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
114 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
115 loadv2f64, loadv4f64, X86Fnmsub, v2f64,
119 let Constraints = "$src1 = $dst" in {
120 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
121 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
122 SDPatternOperator OpNode = null_frag> {
123 let usesCustomInserter = 1 in
124 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
125 (ins RC:$src1, RC:$src2, RC:$src3),
126 !strconcat(OpcodeStr,
127 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
129 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
132 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
133 (ins RC:$src1, RC:$src2, x86memop:$src3),
134 !strconcat(OpcodeStr,
135 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
137 (OpVT (OpNode RC:$src2, RC:$src1,
138 (mem_frag addr:$src3))))]>;
140 } // Constraints = "$src1 = $dst"
142 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
143 string OpStr, string PackTy, string PT2, Intrinsic Int,
144 SDNode OpNode, RegisterClass RC, ValueType OpVT,
145 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
146 ComplexPattern mem_cpat> {
147 let neverHasSideEffects = 1 in {
148 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
149 x86memop, RC, OpVT, mem_frag>;
150 let isCommutable = 1 in
151 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy),
152 x86memop, RC, OpVT, mem_frag>;
155 let isCommutable = 1 in
156 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy),
157 x86memop, RC, OpVT, mem_frag, OpNode>;
160 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
161 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
163 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", IntF32, OpNode,
164 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
165 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode,
166 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
168 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
170 (!cast<Instruction>(NAME#"SSr213r")
171 (COPY_TO_REGCLASS $src2, FR32),
172 (COPY_TO_REGCLASS $src1, FR32),
173 (COPY_TO_REGCLASS $src3, FR32)),
176 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
178 (!cast<Instruction>(NAME#"SDr213r")
179 (COPY_TO_REGCLASS $src2, FR64),
180 (COPY_TO_REGCLASS $src1, FR64),
181 (COPY_TO_REGCLASS $src3, FR64)),
185 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
186 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
187 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
188 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
190 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
191 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
192 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
193 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
196 //===----------------------------------------------------------------------===//
197 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
198 //===----------------------------------------------------------------------===//
201 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
202 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
204 let isCommutable = 1 in
205 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
206 (ins RC:$src1, RC:$src2, RC:$src3),
207 !strconcat(OpcodeStr,
208 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
210 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
211 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
212 (ins RC:$src1, RC:$src2, x86memop:$src3),
213 !strconcat(OpcodeStr,
214 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
215 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
216 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
217 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
218 (ins RC:$src1, x86memop:$src2, RC:$src3),
219 !strconcat(OpcodeStr,
220 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
222 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
224 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
225 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
226 (ins RC:$src1, RC:$src2, RC:$src3),
227 !strconcat(OpcodeStr,
228 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
232 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
233 ComplexPattern mem_cpat, Intrinsic Int> {
234 let isCodeGenOnly = 1 in {
235 let isCommutable = 1 in
236 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
237 (ins VR128:$src1, VR128:$src2, VR128:$src3),
238 !strconcat(OpcodeStr,
239 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
241 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
242 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
243 (ins VR128:$src1, VR128:$src2, memop:$src3),
244 !strconcat(OpcodeStr,
245 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
246 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
247 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4;
248 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
249 (ins VR128:$src1, memop:$src2, VR128:$src3),
250 !strconcat(OpcodeStr,
251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
253 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
254 } // isCodeGenOnly = 1
257 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
258 ValueType OpVT128, ValueType OpVT256,
259 PatFrag ld_frag128, PatFrag ld_frag256> {
260 let isCommutable = 1 in
261 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
262 (ins VR128:$src1, VR128:$src2, VR128:$src3),
263 !strconcat(OpcodeStr,
264 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
266 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
268 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
269 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
270 !strconcat(OpcodeStr,
271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
272 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
273 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
274 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
275 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
276 !strconcat(OpcodeStr,
277 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
279 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
280 let isCommutable = 1 in
281 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
282 (ins VR256:$src1, VR256:$src2, VR256:$src3),
283 !strconcat(OpcodeStr,
284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
286 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
287 VEX_W, MemOp4, VEX_L;
288 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
289 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
290 !strconcat(OpcodeStr,
291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
292 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
293 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L;
294 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
295 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
296 !strconcat(OpcodeStr,
297 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
298 [(set VR256:$dst, (OpNode VR256:$src1,
299 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
301 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
302 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
303 (ins VR128:$src1, VR128:$src2, VR128:$src3),
304 !strconcat(OpcodeStr,
305 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
306 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
307 (ins VR256:$src1, VR256:$src2, VR256:$src3),
308 !strconcat(OpcodeStr,
309 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
311 } // isCodeGenOnly = 1
314 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
315 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
316 int_x86_fma_vfmadd_ss>;
317 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
318 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
319 int_x86_fma_vfmadd_sd>;
320 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
321 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
322 int_x86_fma_vfmsub_ss>;
323 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
324 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
325 int_x86_fma_vfmsub_sd>;
326 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
328 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
329 int_x86_fma_vfnmadd_ss>;
330 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
332 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
333 int_x86_fma_vfnmadd_sd>;
334 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
336 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
337 int_x86_fma_vfnmsub_ss>;
338 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
340 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
341 int_x86_fma_vfnmsub_sd>;
343 let ExeDomain = SSEPackedSingle in {
344 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
345 loadv4f32, loadv8f32>;
346 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
347 loadv4f32, loadv8f32>;
348 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
349 loadv4f32, loadv8f32>;
350 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
351 loadv4f32, loadv8f32>;
352 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
353 loadv4f32, loadv8f32>;
354 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
355 loadv4f32, loadv8f32>;
358 let ExeDomain = SSEPackedDouble in {
359 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
360 loadv2f64, loadv4f64>;
361 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
362 loadv2f64, loadv4f64>;
363 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
364 loadv2f64, loadv4f64>;
365 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
366 loadv2f64, loadv4f64>;
367 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
368 loadv2f64, loadv4f64>;
369 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
370 loadv2f64, loadv4f64>;