1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
20 PatFrag MemFrag128, PatFrag MemFrag256,
21 ValueType OpVT128, ValueType OpVT256,
22 SDPatternOperator Op = null_frag> {
23 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
24 (ins VR128:$src1, VR128:$src2, VR128:$src3),
26 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
27 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
28 VR128:$src1, VR128:$src3)))]>;
31 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
32 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
34 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
35 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
36 (MemFrag128 addr:$src3))))]>;
38 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
39 (ins VR256:$src1, VR256:$src2, VR256:$src3),
41 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
42 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
46 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
47 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
49 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 (OpVT256 (Op VR256:$src2, VR256:$src1,
52 (MemFrag256 addr:$src3))))]>;
54 } // Constraints = "$src1 = $dst"
56 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
57 string OpcodeStr, string PackTy,
58 PatFrag MemFrag128, PatFrag MemFrag256,
59 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
60 defm r213 : fma3p_rm<opc213,
61 !strconcat(OpcodeStr, !strconcat("213", PackTy)),
62 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
63 let neverHasSideEffects = 1 in {
64 defm r132 : fma3p_rm<opc132,
65 !strconcat(OpcodeStr, !strconcat("132", PackTy)),
66 MemFrag128, MemFrag256, OpTy128, OpTy256>;
67 defm r231 : fma3p_rm<opc231,
68 !strconcat(OpcodeStr, !strconcat("231", PackTy)),
69 MemFrag128, MemFrag256, OpTy128, OpTy256>;
70 } // neverHasSideEffects = 1
74 let ExeDomain = SSEPackedSingle in {
75 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
76 memopv8f32, X86Fmadd, v4f32, v8f32>;
77 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
78 memopv8f32, X86Fmsub, v4f32, v8f32>;
79 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
80 memopv4f32, memopv8f32, X86Fmaddsub,
82 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
83 memopv4f32, memopv8f32, X86Fmsubadd,
87 let ExeDomain = SSEPackedDouble in {
88 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
89 memopv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
90 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
91 memopv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
92 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
93 memopv2f64, memopv4f64, X86Fmaddsub,
95 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
96 memopv2f64, memopv4f64, X86Fmsubadd,
100 // Fused Negative Multiply-Add
101 let ExeDomain = SSEPackedSingle in {
102 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
103 memopv8f32, X86Fnmadd, v4f32, v8f32>;
104 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
105 memopv8f32, X86Fnmsub, v4f32, v8f32>;
107 let ExeDomain = SSEPackedDouble in {
108 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
109 memopv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
110 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
111 memopv2f64, memopv4f64, X86Fnmsub, v2f64,
115 let Constraints = "$src1 = $dst" in {
116 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
117 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
118 SDPatternOperator OpNode = null_frag> {
119 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
120 (ins RC:$src1, RC:$src2, RC:$src3),
121 !strconcat(OpcodeStr,
122 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
124 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
126 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
127 (ins RC:$src1, RC:$src2, x86memop:$src3),
128 !strconcat(OpcodeStr,
129 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
131 (OpVT (OpNode RC:$src2, RC:$src1,
132 (mem_frag addr:$src3))))]>;
135 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
136 ComplexPattern mem_cpat, Intrinsic IntId,
138 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
139 (ins VR128:$src1, VR128:$src2, VR128:$src3),
140 !strconcat(OpcodeStr,
141 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
142 [(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
144 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
145 (ins VR128:$src1, VR128:$src2, memop:$src3),
146 !strconcat(OpcodeStr,
147 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
149 (IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
151 } // Constraints = "$src1 = $dst"
153 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
154 string OpStr, string PackTy, Intrinsic Int,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
156 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
157 ComplexPattern mem_cpat> {
158 let neverHasSideEffects = 1 in {
159 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, !strconcat("132", PackTy)),
160 x86memop, RC, OpVT, mem_frag>;
161 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, !strconcat("231", PackTy)),
162 x86memop, RC, OpVT, mem_frag>;
165 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
166 x86memop, RC, OpVT, mem_frag, OpNode>,
167 fma3s_rm_int<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
168 memop, mem_cpat, Int, RC>;
171 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
172 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
174 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
175 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
176 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
177 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
180 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
181 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
182 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
183 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
185 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
186 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
187 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
188 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
191 //===----------------------------------------------------------------------===//
192 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
193 //===----------------------------------------------------------------------===//
196 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
197 ComplexPattern mem_cpat, Intrinsic Int> {
198 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
199 (ins VR128:$src1, VR128:$src2, VR128:$src3),
200 !strconcat(OpcodeStr,
201 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
203 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
204 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
205 (ins VR128:$src1, VR128:$src2, memop:$src3),
206 !strconcat(OpcodeStr,
207 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
209 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
210 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
211 (ins VR128:$src1, memop:$src2, VR128:$src3),
212 !strconcat(OpcodeStr,
213 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
215 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
217 let isCodeGenOnly = 1 in
218 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
219 (ins VR128:$src1, VR128:$src2, VR128:$src3),
220 !strconcat(OpcodeStr,
221 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
224 multiclass fma4p<bits<8> opc, string OpcodeStr,
225 Intrinsic Int128, Intrinsic Int256,
226 PatFrag ld_frag128, PatFrag ld_frag256> {
227 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
228 (ins VR128:$src1, VR128:$src2, VR128:$src3),
229 !strconcat(OpcodeStr,
230 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
232 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
233 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
234 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
235 !strconcat(OpcodeStr,
236 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
237 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
238 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
239 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
240 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
241 !strconcat(OpcodeStr,
242 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
244 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
245 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
246 (ins VR256:$src1, VR256:$src2, VR256:$src3),
247 !strconcat(OpcodeStr,
248 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
250 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
251 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
252 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
253 !strconcat(OpcodeStr,
254 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
255 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
256 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
257 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
258 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
259 !strconcat(OpcodeStr,
260 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
262 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
264 let isCodeGenOnly = 1 in {
265 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
266 (ins VR128:$src1, VR128:$src2, VR128:$src3),
267 !strconcat(OpcodeStr,
268 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
269 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
270 (ins VR256:$src1, VR256:$src2, VR256:$src3),
271 !strconcat(OpcodeStr,
272 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
273 } // isCodeGenOnly = 1
276 let Predicates = [HasFMA4] in {
278 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
279 int_x86_fma_vfmadd_ss>;
280 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
281 int_x86_fma_vfmadd_sd>;
282 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma_vfmadd_ps,
283 int_x86_fma_vfmadd_ps_256, memopv4f32, memopv8f32>;
284 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma_vfmadd_pd,
285 int_x86_fma_vfmadd_pd_256, memopv2f64, memopv4f64>;
286 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
287 int_x86_fma_vfmsub_ss>;
288 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
289 int_x86_fma_vfmsub_sd>;
290 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma_vfmsub_ps,
291 int_x86_fma_vfmsub_ps_256, memopv4f32, memopv8f32>;
292 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma_vfmsub_pd,
293 int_x86_fma_vfmsub_pd_256, memopv2f64, memopv4f64>;
294 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
295 int_x86_fma_vfnmadd_ss>;
296 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
297 int_x86_fma_vfnmadd_sd>;
298 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma_vfnmadd_ps,
299 int_x86_fma_vfnmadd_ps_256, memopv4f32, memopv8f32>;
300 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma_vfnmadd_pd,
301 int_x86_fma_vfnmadd_pd_256, memopv2f64, memopv4f64>;
302 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
303 int_x86_fma_vfnmsub_ss>;
304 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
305 int_x86_fma_vfnmsub_sd>;
306 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma_vfnmsub_ps,
307 int_x86_fma_vfnmsub_ps_256, memopv4f32, memopv8f32>;
308 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma_vfnmsub_pd,
309 int_x86_fma_vfnmsub_pd_256, memopv2f64, memopv4f64>;
310 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma_vfmaddsub_ps,
311 int_x86_fma_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
312 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma_vfmaddsub_pd,
313 int_x86_fma_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
314 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma_vfmsubadd_ps,
315 int_x86_fma_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
316 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma_vfmsubadd_pd,
317 int_x86_fma_vfmsubadd_pd_256, memopv2f64, memopv4f64>;