1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
20 PatFrag MemFrag128, PatFrag MemFrag256,
21 ValueType OpVT128, ValueType OpVT256,
22 SDPatternOperator Op = null_frag, bit MayLoad = 1> {
23 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
24 (ins VR128:$src1, VR128:$src2, VR128:$src3),
26 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
27 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
28 VR128:$src1, VR128:$src3)))]>;
30 let mayLoad = MayLoad in
31 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
32 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
34 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
35 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
36 (MemFrag128 addr:$src3))))]>;
38 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
39 (ins VR256:$src1, VR256:$src2, VR256:$src3),
41 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
42 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
45 let mayLoad = MayLoad in
46 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
47 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
49 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 (OpVT256 (Op VR256:$src2, VR256:$src1,
52 (MemFrag256 addr:$src3))))]>;
54 } // Constraints = "$src1 = $dst"
56 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
57 string OpcodeStr, string PackTy,
58 PatFrag MemFrag128, PatFrag MemFrag256,
59 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
60 defm r213 : fma3p_rm<opc213,
61 !strconcat(OpcodeStr, !strconcat("213", PackTy)),
62 MemFrag128, MemFrag256, OpTy128, OpTy256, Op, 0>;
63 let neverHasSideEffects = 1 in {
64 defm r132 : fma3p_rm<opc132,
65 !strconcat(OpcodeStr, !strconcat("132", PackTy)),
66 MemFrag128, MemFrag256, OpTy128, OpTy256>;
67 defm r231 : fma3p_rm<opc231,
68 !strconcat(OpcodeStr, !strconcat("231", PackTy)),
69 MemFrag128, MemFrag256, OpTy128, OpTy256>;
70 } // neverHasSideEffects = 1
74 let ExeDomain = SSEPackedSingle in {
75 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
76 memopv8f32, X86Fmadd, v4f32, v8f32>;
77 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
78 memopv8f32, X86Fmsub, v4f32, v8f32>;
79 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
80 memopv4f32, memopv8f32, X86Fmaddsub,
82 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
83 memopv4f32, memopv8f32, X86Fmsubadd,
87 let ExeDomain = SSEPackedDouble in {
88 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
89 memopv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
90 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
91 memopv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
92 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
93 memopv2f64, memopv4f64, X86Fmaddsub,
95 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
96 memopv2f64, memopv4f64, X86Fmsubadd,
100 // Fused Negative Multiply-Add
101 let ExeDomain = SSEPackedSingle in {
102 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
103 memopv8f32, X86Fnmadd, v4f32, v8f32>;
104 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
105 memopv8f32, X86Fnmsub, v4f32, v8f32>;
107 let ExeDomain = SSEPackedDouble in {
108 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
109 memopv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
110 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
111 memopv2f64, memopv4f64, X86Fnmsub, v2f64,
115 let Predicates = [HasFMA] in {
116 def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
117 (VFMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
118 def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1,
119 (memopv4f32 addr:$src3)),
120 (VFMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
121 def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
122 (VFMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
123 def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1,
124 (memopv4f32 addr:$src3)),
125 (VFMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
126 def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
127 (VFMADDSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
128 def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1,
129 (memopv4f32 addr:$src3)),
130 (VFMADDSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
131 def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
132 (VFMSUBADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
133 def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1,
134 (memopv4f32 addr:$src3)),
135 (VFMSUBADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
137 def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
138 (VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
139 def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1,
140 (memopv8f32 addr:$src3)),
141 (VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
142 def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
143 (VFMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
144 def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1,
145 (memopv8f32 addr:$src3)),
146 (VFMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
147 def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
148 (VFMADDSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
149 def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1,
150 (memopv8f32 addr:$src3)),
151 (VFMADDSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
152 def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
153 (VFMSUBADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
154 def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1,
155 (memopv8f32 addr:$src3)),
156 (VFMSUBADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
158 def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
159 (VFMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
160 def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1,
161 (memopv2f64 addr:$src3)),
162 (VFMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
163 def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
164 (VFMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
165 def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1,
166 (memopv2f64 addr:$src3)),
167 (VFMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
168 def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
169 (VFMADDSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
170 def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1,
171 (memopv2f64 addr:$src3)),
172 (VFMADDSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
173 def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
174 (VFMSUBADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
175 def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1,
176 (memopv2f64 addr:$src3)),
177 (VFMSUBADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
179 def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
180 (VFMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
181 def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1,
182 (memopv4f64 addr:$src3)),
183 (VFMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
184 def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
185 (VFMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
186 def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1,
187 (memopv4f64 addr:$src3)),
188 (VFMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
189 def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
190 (VFMADDSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
191 def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1,
192 (memopv4f64 addr:$src3)),
193 (VFMADDSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
194 def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
195 (VFMSUBADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
196 def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1,
197 (memopv4f64 addr:$src3)),
198 (VFMSUBADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
200 def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
201 (VFNMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
202 def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1,
203 (memopv4f32 addr:$src3)),
204 (VFNMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
205 def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
206 (VFNMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
207 def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1,
208 (memopv4f32 addr:$src3)),
209 (VFNMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
211 def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
212 (VFNMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
213 def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1,
214 (memopv8f32 addr:$src3)),
215 (VFNMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
216 def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
217 (VFNMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
218 def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1,
219 (memopv8f32 addr:$src3)),
220 (VFNMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
222 def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
223 (VFNMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
224 def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1,
225 (memopv2f64 addr:$src3)),
226 (VFNMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
227 def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
228 (VFNMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
229 def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1,
230 (memopv2f64 addr:$src3)),
231 (VFNMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
233 def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
234 (VFNMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
235 def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1,
236 (memopv4f64 addr:$src3)),
237 (VFNMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
238 def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
239 (VFNMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
240 def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1,
241 (memopv4f64 addr:$src3)),
242 (VFNMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
244 } // Predicates = [HasFMA]
246 let Constraints = "$src1 = $dst" in {
247 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
248 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
249 SDPatternOperator OpNode = null_frag, bit MayLoad = 1> {
250 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
251 (ins RC:$src1, RC:$src2, RC:$src3),
252 !strconcat(OpcodeStr,
253 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
255 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
256 let mayLoad = MayLoad in
257 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
258 (ins RC:$src1, RC:$src2, x86memop:$src3),
259 !strconcat(OpcodeStr,
260 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
262 (OpVT (OpNode RC:$src2, RC:$src1,
263 (mem_frag addr:$src3))))]>;
266 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
267 ComplexPattern mem_cpat, Intrinsic IntId,
269 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
270 (ins VR128:$src1, VR128:$src2, VR128:$src3),
271 !strconcat(OpcodeStr,
272 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
273 [(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
275 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
276 (ins VR128:$src1, VR128:$src2, memop:$src3),
277 !strconcat(OpcodeStr,
278 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
280 (IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
282 } // Constraints = "$src1 = $dst"
284 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
285 string OpStr, string PackTy, Intrinsic Int,
286 SDNode OpNode, RegisterClass RC, ValueType OpVT,
287 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
288 ComplexPattern mem_cpat> {
289 let neverHasSideEffects = 1 in {
290 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, !strconcat("132", PackTy)),
291 x86memop, RC, OpVT, mem_frag>;
292 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, !strconcat("231", PackTy)),
293 x86memop, RC, OpVT, mem_frag>;
296 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
297 x86memop, RC, OpVT, mem_frag, OpNode, 0>,
298 fma3s_rm_int<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
299 memop, mem_cpat, Int, RC>;
302 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
303 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
305 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
306 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
307 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
308 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
311 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
312 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
313 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
314 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
316 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
317 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
318 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
319 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
322 //===----------------------------------------------------------------------===//
323 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
324 //===----------------------------------------------------------------------===//
327 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
328 ComplexPattern mem_cpat, Intrinsic Int> {
329 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
330 (ins VR128:$src1, VR128:$src2, VR128:$src3),
331 !strconcat(OpcodeStr,
332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
335 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
336 (ins VR128:$src1, VR128:$src2, memop:$src3),
337 !strconcat(OpcodeStr,
338 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
340 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
341 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
342 (ins VR128:$src1, memop:$src2, VR128:$src3),
343 !strconcat(OpcodeStr,
344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
346 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
348 let isCodeGenOnly = 1 in
349 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
350 (ins VR128:$src1, VR128:$src2, VR128:$src3),
351 !strconcat(OpcodeStr,
352 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
355 multiclass fma4p<bits<8> opc, string OpcodeStr,
356 Intrinsic Int128, Intrinsic Int256,
357 PatFrag ld_frag128, PatFrag ld_frag256> {
358 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
359 (ins VR128:$src1, VR128:$src2, VR128:$src3),
360 !strconcat(OpcodeStr,
361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
363 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
364 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
365 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
366 !strconcat(OpcodeStr,
367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
368 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
369 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
370 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
371 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
372 !strconcat(OpcodeStr,
373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
375 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
376 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
377 (ins VR256:$src1, VR256:$src2, VR256:$src3),
378 !strconcat(OpcodeStr,
379 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
381 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
382 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
383 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
384 !strconcat(OpcodeStr,
385 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
386 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
387 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
388 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
389 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
390 !strconcat(OpcodeStr,
391 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
393 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
395 let isCodeGenOnly = 1 in {
396 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
397 (ins VR128:$src1, VR128:$src2, VR128:$src3),
398 !strconcat(OpcodeStr,
399 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
400 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
401 (ins VR256:$src1, VR256:$src2, VR256:$src3),
402 !strconcat(OpcodeStr,
403 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
404 } // isCodeGenOnly = 1
407 let Predicates = [HasFMA4] in {
409 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
410 int_x86_fma_vfmadd_ss>;
411 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
412 int_x86_fma_vfmadd_sd>;
413 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma_vfmadd_ps,
414 int_x86_fma_vfmadd_ps_256, memopv4f32, memopv8f32>;
415 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma_vfmadd_pd,
416 int_x86_fma_vfmadd_pd_256, memopv2f64, memopv4f64>;
417 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
418 int_x86_fma_vfmsub_ss>;
419 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
420 int_x86_fma_vfmsub_sd>;
421 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma_vfmsub_ps,
422 int_x86_fma_vfmsub_ps_256, memopv4f32, memopv8f32>;
423 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma_vfmsub_pd,
424 int_x86_fma_vfmsub_pd_256, memopv2f64, memopv4f64>;
425 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
426 int_x86_fma_vfnmadd_ss>;
427 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
428 int_x86_fma_vfnmadd_sd>;
429 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma_vfnmadd_ps,
430 int_x86_fma_vfnmadd_ps_256, memopv4f32, memopv8f32>;
431 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma_vfnmadd_pd,
432 int_x86_fma_vfnmadd_pd_256, memopv2f64, memopv4f64>;
433 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
434 int_x86_fma_vfnmsub_ss>;
435 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
436 int_x86_fma_vfnmsub_sd>;
437 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma_vfnmsub_ps,
438 int_x86_fma_vfnmsub_ps_256, memopv4f32, memopv8f32>;
439 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma_vfnmsub_pd,
440 int_x86_fma_vfnmsub_pd_256, memopv2f64, memopv4f64>;
441 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma_vfmaddsub_ps,
442 int_x86_fma_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
443 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma_vfmaddsub_pd,
444 int_x86_fma_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
445 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma_vfmsubadd_ps,
446 int_x86_fma_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
447 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma_vfmsubadd_pd,
448 int_x86_fma_vfmsubadd_pd_256, memopv2f64, memopv4f64>;