1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
23 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
24 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
25 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
26 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
30 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
31 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
32 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
33 [SDNPHasChain, SDNPOutFlag]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
40 def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
49 //===----------------------------------------------------------------------===//
50 // FPStack pattern fragments
51 //===----------------------------------------------------------------------===//
53 def fp32imm0 : PatLeaf<(f32 fpimm), [{
54 return N->isExactlyValue(+0.0);
57 def fp64imm0 : PatLeaf<(f64 fpimm), [{
58 return N->isExactlyValue(+0.0);
61 def fp64immneg0 : PatLeaf<(f64 fpimm), [{
62 return N->isExactlyValue(-0.0);
65 def fp64imm1 : PatLeaf<(f64 fpimm), [{
66 return N->isExactlyValue(+1.0);
69 def fp64immneg1 : PatLeaf<(f64 fpimm), [{
70 return N->isExactlyValue(-1.0);
73 def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
75 // Some 'special' instructions
76 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
77 def FP_TO_INT16_IN_MEM : I<0, Pseudo,
78 (ops i16mem:$dst, RFP:$src),
79 "#FP_TO_INT16_IN_MEM PSEUDO!",
80 [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
81 def FP_TO_INT32_IN_MEM : I<0, Pseudo,
82 (ops i32mem:$dst, RFP:$src),
83 "#FP_TO_INT32_IN_MEM PSEUDO!",
84 [(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
85 def FP_TO_INT64_IN_MEM : I<0, Pseudo,
86 (ops i64mem:$dst, RFP:$src),
87 "#FP_TO_INT64_IN_MEM PSEUDO!",
88 [(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
91 let isTerminator = 1 in
92 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
93 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
95 // All FP Stack operations are represented with two instructions here. The
96 // first instruction, generated by the instruction selector, uses "RFP"
97 // registers: a traditional register file to reference floating point values.
98 // These instructions are all psuedo instructions and use the "Fp" prefix.
99 // The second instruction is defined with FPI, which is the actual instruction
100 // emitted by the assembler. The FP stackifier pass converts one to the other
101 // after register allocation occurs.
103 // Note that the FpI instruction should have instruction selection info (e.g.
104 // a pattern) and the FPI instruction should have emission info (e.g. opcode
105 // encoding and asm printing info).
107 // FPI - Floating Point Instruction template.
108 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
110 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
111 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
112 : X86Inst<0, Pseudo, NoImm, ops, ""> {
113 let FPForm = fp; let FPFormBits = FPForm.Value;
114 let Pattern = pattern;
117 // Random Pseudo Instructions.
118 def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP,
119 [(set RFP:$dst, X86fpget)]>; // FPR = ST(0)
122 def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP,
123 [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
125 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
126 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
127 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
130 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
133 // Add, Sub, Mul, Div.
134 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
135 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
136 def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
137 [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>;
138 def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
139 [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>;
140 def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
141 [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>;
143 class FPST0rInst<bits<8> o, string asm>
144 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
145 class FPrST0Inst<bits<8> o, string asm>
146 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
147 class FPrST0PInst<bits<8> o, string asm>
148 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
150 // Binary Ops with a memory source.
151 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
152 [(set RFP:$dst, (fadd RFP:$src1,
153 (extloadf64f32 addr:$src2)))]>;
154 // ST(0) = ST(0) + [mem32]
155 def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
156 [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>;
157 // ST(0) = ST(0) + [mem64]
158 def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
159 [(set RFP:$dst, (fmul RFP:$src1,
160 (extloadf64f32 addr:$src2)))]>;
161 // ST(0) = ST(0) * [mem32]
162 def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
163 [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>;
164 // ST(0) = ST(0) * [mem64]
165 def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
166 [(set RFP:$dst, (fsub RFP:$src1,
167 (extloadf64f32 addr:$src2)))]>;
168 // ST(0) = ST(0) - [mem32]
169 def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
170 [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>;
171 // ST(0) = ST(0) - [mem64]
172 def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
173 [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2),
175 // ST(0) = [mem32] - ST(0)
176 def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
177 [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>;
178 // ST(0) = [mem64] - ST(0)
179 def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
180 [(set RFP:$dst, (fdiv RFP:$src1,
181 (extloadf64f32 addr:$src2)))]>;
182 // ST(0) = ST(0) / [mem32]
183 def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
184 [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>;
185 // ST(0) = ST(0) / [mem64]
186 def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
187 [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2),
189 // ST(0) = [mem32] / ST(0)
190 def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
191 [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>;
192 // ST(0) = [mem64] / ST(0)
195 def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">;
196 def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">;
197 def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">;
198 def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">;
199 def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">;
200 def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">;
201 def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">;
202 def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">;
203 def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">;
204 def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">;
205 def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
206 def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
208 def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
209 [(set RFP:$dst, (fadd RFP:$src1,
210 (X86fild addr:$src2, i16)))]>;
211 // ST(0) = ST(0) + [mem16int]
212 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
213 [(set RFP:$dst, (fadd RFP:$src1,
214 (X86fild addr:$src2, i32)))]>;
215 // ST(0) = ST(0) + [mem32int]
216 def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
217 [(set RFP:$dst, (fmul RFP:$src1,
218 (X86fild addr:$src2, i16)))]>;
219 // ST(0) = ST(0) * [mem16int]
220 def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
221 [(set RFP:$dst, (fmul RFP:$src1,
222 (X86fild addr:$src2, i32)))]>;
223 // ST(0) = ST(0) * [mem32int]
224 def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
225 [(set RFP:$dst, (fsub RFP:$src1,
226 (X86fild addr:$src2, i16)))]>;
227 // ST(0) = ST(0) - [mem16int]
228 def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
229 [(set RFP:$dst, (fsub RFP:$src1,
230 (X86fild addr:$src2, i32)))]>;
231 // ST(0) = ST(0) - [mem32int]
232 def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
233 [(set RFP:$dst, (fsub (X86fild addr:$src2, i16),
235 // ST(0) = [mem16int] - ST(0)
236 def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
237 [(set RFP:$dst, (fsub (X86fild addr:$src2, i32),
239 // ST(0) = [mem32int] - ST(0)
240 def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
241 [(set RFP:$dst, (fdiv RFP:$src1,
242 (X86fild addr:$src2, i16)))]>;
243 // ST(0) = ST(0) / [mem16int]
244 def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
245 [(set RFP:$dst, (fdiv RFP:$src1,
246 (X86fild addr:$src2, i32)))]>;
247 // ST(0) = ST(0) / [mem32int]
248 def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
249 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16),
251 // ST(0) = [mem16int] / ST(0)
252 def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
253 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32),
255 // ST(0) = [mem32int] / ST(0)
257 def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
258 def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
259 def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
260 def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
261 def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
262 def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
263 def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
264 def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
265 def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
266 def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">;
267 def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
268 def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">;
270 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
271 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
272 // we have to put some 'r's in and take them out of weird places.
273 def FADDST0r : FPST0rInst <0xC0, "fadd $op">;
274 def FADDrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
275 def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">;
276 def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">;
277 def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
278 def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
279 def FSUBST0r : FPST0rInst <0xE0, "fsub $op">;
280 def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
281 def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
282 def FMULST0r : FPST0rInst <0xC8, "fmul $op">;
283 def FMULrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
284 def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
285 def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">;
286 def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
287 def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
288 def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">;
289 def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
290 def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
294 def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
295 [(set RFP:$dst, (fneg RFP:$src))]>;
296 def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
297 [(set RFP:$dst, (fabs RFP:$src))]>;
298 def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
299 [(set RFP:$dst, (fsqrt RFP:$src))]>;
300 def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
301 [(set RFP:$dst, (fsin RFP:$src))]>;
302 def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
303 [(set RFP:$dst, (fcos RFP:$src))]>;
304 def FpTST : FpI<(ops RFP:$src), OneArgFP,
307 def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9;
308 def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9;
309 def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9;
310 def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9;
311 def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9;
312 def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
315 // Floating point cmovs.
316 let isTwoAddress = 1 in {
317 def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
318 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
320 def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
321 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
323 def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
324 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
326 def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
327 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
329 def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
330 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
332 def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
333 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
335 def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
336 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
338 def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
339 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
343 def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op),
344 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
345 def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
346 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
347 def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op),
348 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
349 def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
350 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
351 def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op),
352 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
353 def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
354 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
355 def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
356 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
357 def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),
358 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
360 // Floating point loads & stores.
361 def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP,
362 [(set RFP:$dst, (extloadf64f32 addr:$src))]>;
363 def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
364 [(set RFP:$dst, (loadf64 addr:$src))]>;
365 def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
366 [(set RFP:$dst, (X86fild addr:$src, i16))]>;
367 def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
368 [(set RFP:$dst, (X86fild addr:$src, i32))]>;
369 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
370 [(set RFP:$dst, (X86fild addr:$src, i64))]>;
372 def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
373 [(truncstore RFP:$src, addr:$op, f32)]>;
374 def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
375 [(store RFP:$src, addr:$op)]>;
377 def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
378 def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
379 def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
380 def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>;
381 def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>;
383 def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
384 def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
385 def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
386 def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
387 def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
388 def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
389 def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
390 def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
391 def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
392 def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
393 def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
394 def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
395 def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
396 def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
398 // FISTTP requires SSE3 even though it's a FPStack op.
399 def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP,
400 [(X86fp_to_i16mem RFP:$src, addr:$op)]>,
402 def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP,
403 [(X86fp_to_i32mem RFP:$src, addr:$op)]>,
405 def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP,
406 [(X86fp_to_i64mem RFP:$src, addr:$op)]>,
409 def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
410 def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
411 def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
413 // FP Stack manipulation instructions.
414 def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
415 def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
416 def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
417 def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
419 // Floating point constant loads.
420 def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
421 [(set RFP:$dst, fp64imm0)]>;
422 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
423 [(set RFP:$dst, fp64imm1)]>;
425 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
426 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
429 // Floating point compares.
430 def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
431 []>; // FPSW = cmp ST(0) with ST(i)
432 def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
433 [(X86cmp RFP:$lhs, RFP:$rhs)]>; // CC = cmp ST(0) with ST(i)
435 def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
437 "fucom $reg">, DD, Imp<[ST0],[]>;
438 def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
440 "fucomp $reg">, DD, Imp<[ST0],[]>;
441 def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
443 "fucompp">, DA, Imp<[ST0],[]>;
445 def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
447 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
448 def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
450 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
453 // Floating point flag ops.
454 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
455 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
457 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
458 (ops i16mem:$dst), "fnstcw $dst", []>;
459 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
460 (ops i16mem:$dst), "fldcw $dst", []>;
462 //===----------------------------------------------------------------------===//
463 // Non-Instruction Patterns
464 //===----------------------------------------------------------------------===//
466 // Required for RET of f32 / f64 values.
467 def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
468 def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
470 // Required for CALL which return f32 / f64 values.
471 def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
472 def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
474 // Floating point constant -0.0 and -1.0
475 def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
476 def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
478 // Used to conv. i64 to f64 since there isn't a SSE version.
479 def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>;