1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
22 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
23 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
25 SDTCisVT<2, OtherVT>]>;
26 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
28 SDTCisVT<2, OtherVT>]>;
29 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
30 SDTCisVT<2, OtherVT>]>;
31 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
33 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
35 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
36 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
37 def X86fpget2 : SDNode<"X86ISD::FP_GET_RESULT2", SDTX86FpGet2,
38 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
39 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
40 [SDNPHasChain, SDNPOutFlag]>;
41 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
42 [SDNPHasChain, SDNPMayLoad]>;
43 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
44 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
45 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
46 [SDNPHasChain, SDNPMayLoad]>;
47 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
48 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
49 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
50 [SDNPHasChain, SDNPMayStore]>;
51 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
52 [SDNPHasChain, SDNPMayStore]>;
53 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
54 [SDNPHasChain, SDNPMayStore]>;
55 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
56 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
58 //===----------------------------------------------------------------------===//
59 // FPStack pattern fragments
60 //===----------------------------------------------------------------------===//
62 def fpimm0 : PatLeaf<(fpimm), [{
63 return N->isExactlyValue(+0.0);
66 def fpimmneg0 : PatLeaf<(fpimm), [{
67 return N->isExactlyValue(-0.0);
70 def fpimm1 : PatLeaf<(fpimm), [{
71 return N->isExactlyValue(+1.0);
74 def fpimmneg1 : PatLeaf<(fpimm), [{
75 return N->isExactlyValue(-1.0);
78 // Some 'special' instructions
79 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
80 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
81 (outs), (ins i16mem:$dst, RFP32:$src),
82 "#FP32_TO_INT16_IN_MEM PSEUDO!",
83 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
84 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
85 (outs), (ins i32mem:$dst, RFP32:$src),
86 "#FP32_TO_INT32_IN_MEM PSEUDO!",
87 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
88 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
89 (outs), (ins i64mem:$dst, RFP32:$src),
90 "#FP32_TO_INT64_IN_MEM PSEUDO!",
91 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
92 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
93 (outs), (ins i16mem:$dst, RFP64:$src),
94 "#FP64_TO_INT16_IN_MEM PSEUDO!",
95 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
96 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
97 (outs), (ins i32mem:$dst, RFP64:$src),
98 "#FP64_TO_INT32_IN_MEM PSEUDO!",
99 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
100 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
101 (outs), (ins i64mem:$dst, RFP64:$src),
102 "#FP64_TO_INT64_IN_MEM PSEUDO!",
103 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
104 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
105 (outs), (ins i16mem:$dst, RFP80:$src),
106 "#FP80_TO_INT16_IN_MEM PSEUDO!",
107 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
108 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
109 (outs), (ins i32mem:$dst, RFP80:$src),
110 "#FP80_TO_INT32_IN_MEM PSEUDO!",
111 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
112 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
113 (outs), (ins i64mem:$dst, RFP80:$src),
114 "#FP80_TO_INT64_IN_MEM PSEUDO!",
115 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
118 let isTerminator = 1 in
119 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
120 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
122 // All FP Stack operations are represented with four instructions here. The
123 // first three instructions, generated by the instruction selector, use "RFP32"
124 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
125 // 64-bit or 80-bit floating point values. These sizes apply to the values,
126 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
127 // copied to each other without losing information. These instructions are all
128 // pseudo instructions and use the "_Fp" suffix.
129 // In some cases there are additional variants with a mixture of different
131 // The second instruction is defined with FPI, which is the actual instruction
132 // emitted by the assembler. These use "RST" registers, although frequently
133 // the actual register(s) used are implicit. These are always 80 bits.
134 // The FP stackifier pass converts one to the other after register allocation
137 // Note that the FpI instruction should have instruction selection info (e.g.
138 // a pattern) and the FPI instruction should have emission info (e.g. opcode
139 // encoding and asm printing info).
141 // Pseudo Instructions for FP stack return values.
142 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
143 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
145 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
146 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
148 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
149 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
151 def FpGETRESULT80x2 : FpI_<(outs RFP80:$dst1, RFP80:$dst2), (ins), SpecialFP,
152 []>; // FPR = ST(0), FPR = ST(1)
155 let Defs = [ST0] in {
156 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
157 [(X86fpset RFP32:$src)]>;// ST(0) = FPR
159 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
160 [(X86fpset RFP64:$src)]>;// ST(0) = FPR
162 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
163 [(X86fpset RFP80:$src)]>;// ST(0) = FPR
166 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
167 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
168 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
169 // f80 instructions cannot use SSE and use neither of these.
170 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
171 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
172 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
173 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
175 // Register copies. Just copies, the shortening ones do not truncate.
176 let neverHasSideEffects = 1 in {
177 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
178 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
179 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
180 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
181 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
182 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
183 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
184 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
185 def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
188 // Factoring for arithmetic.
189 multiclass FPBinary_rr<SDNode OpNode> {
190 // Register op register -> register
191 // These are separated out because they have no reversed form.
192 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
193 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
194 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
195 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
196 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
197 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
199 // The FopST0 series are not included here because of the irregularities
200 // in where the 'r' goes in assembly output.
201 // These instructions cannot address 80-bit memory.
202 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
203 // ST(0) = ST(0) + [mem]
204 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
206 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
207 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
209 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
210 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
212 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
213 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
215 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
216 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
218 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
219 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
220 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
221 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
222 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
223 // ST(0) = ST(0) + [memint]
224 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
225 [(set RFP32:$dst, (OpNode RFP32:$src1,
226 (X86fild addr:$src2, i16)))]>;
227 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
228 [(set RFP32:$dst, (OpNode RFP32:$src1,
229 (X86fild addr:$src2, i32)))]>;
230 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
231 [(set RFP64:$dst, (OpNode RFP64:$src1,
232 (X86fild addr:$src2, i16)))]>;
233 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
234 [(set RFP64:$dst, (OpNode RFP64:$src1,
235 (X86fild addr:$src2, i32)))]>;
236 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
237 [(set RFP80:$dst, (OpNode RFP80:$src1,
238 (X86fild addr:$src2, i16)))]>;
239 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
240 [(set RFP80:$dst, (OpNode RFP80:$src1,
241 (X86fild addr:$src2, i32)))]>;
242 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
243 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
244 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
245 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
248 defm ADD : FPBinary_rr<fadd>;
249 defm SUB : FPBinary_rr<fsub>;
250 defm MUL : FPBinary_rr<fmul>;
251 defm DIV : FPBinary_rr<fdiv>;
252 defm ADD : FPBinary<fadd, MRM0m, "add">;
253 defm SUB : FPBinary<fsub, MRM4m, "sub">;
254 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
255 defm MUL : FPBinary<fmul, MRM1m, "mul">;
256 defm DIV : FPBinary<fdiv, MRM6m, "div">;
257 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
259 class FPST0rInst<bits<8> o, string asm>
260 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
261 class FPrST0Inst<bits<8> o, string asm>
262 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
263 class FPrST0PInst<bits<8> o, string asm>
264 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
266 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
267 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
268 // we have to put some 'r's in and take them out of weird places.
269 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
270 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
271 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
272 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
273 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
274 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
275 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
276 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
277 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
278 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
279 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
280 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
281 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
282 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
283 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
284 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
285 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
286 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
289 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
290 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
291 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
292 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
293 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
294 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
295 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
296 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
299 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
300 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
301 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
302 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
303 defm COS : FPUnary<fcos, 0xFF, "fcos">;
305 let neverHasSideEffects = 1 in {
306 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
307 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
308 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
310 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
312 // Floating point cmovs.
313 multiclass FPCMov<PatLeaf cc> {
314 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
316 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
318 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
320 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
322 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
324 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
327 let Uses = [EFLAGS], isTwoAddress = 1 in {
328 defm CMOVB : FPCMov<X86_COND_B>;
329 defm CMOVBE : FPCMov<X86_COND_BE>;
330 defm CMOVE : FPCMov<X86_COND_E>;
331 defm CMOVP : FPCMov<X86_COND_P>;
332 defm CMOVNB : FPCMov<X86_COND_AE>;
333 defm CMOVNBE: FPCMov<X86_COND_A>;
334 defm CMOVNE : FPCMov<X86_COND_NE>;
335 defm CMOVNP : FPCMov<X86_COND_NP>;
338 // These are not factored because there's no clean way to pass DA/DB.
339 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
340 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
341 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
342 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
343 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
344 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
345 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
346 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
347 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
348 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
349 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
350 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
351 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
352 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
353 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
354 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
356 // Floating point loads & stores.
357 let isSimpleLoad = 1 in {
358 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
359 [(set RFP32:$dst, (loadf32 addr:$src))]>;
360 let isReMaterializable = 1, mayHaveSideEffects = 1 in
361 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
362 [(set RFP64:$dst, (loadf64 addr:$src))]>;
363 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
364 [(set RFP80:$dst, (loadf80 addr:$src))]>;
366 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
367 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
368 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
369 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
370 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
371 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
372 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
373 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
374 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
375 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
376 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
377 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
378 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
379 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
380 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
381 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
382 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
383 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
384 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
385 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
386 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
387 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
388 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
389 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
391 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
392 [(store RFP32:$src, addr:$op)]>;
393 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
394 [(truncstoref32 RFP64:$src, addr:$op)]>;
395 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
396 [(store RFP64:$src, addr:$op)]>;
397 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
398 [(truncstoref32 RFP80:$src, addr:$op)]>;
399 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
400 [(truncstoref64 RFP80:$src, addr:$op)]>;
401 // FST does not support 80-bit memory target; FSTP must be used.
403 let mayStore = 1, neverHasSideEffects = 1 in {
404 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
405 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
406 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
407 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
408 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
410 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
411 [(store RFP80:$src, addr:$op)]>;
412 let mayStore = 1, neverHasSideEffects = 1 in {
413 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
414 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
415 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
416 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
417 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
418 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
419 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
420 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
421 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
425 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
426 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
427 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
428 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
429 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
430 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
432 let mayStore = 1 in {
433 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
434 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
435 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
436 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
437 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
438 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
439 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
440 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
441 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
442 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
445 // FISTTP requires SSE3 even though it's a FPStack op.
446 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
447 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
449 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
450 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
452 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
453 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
455 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
456 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
458 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
459 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
461 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
462 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
464 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
465 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
467 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
468 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
470 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
471 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
474 let mayStore = 1 in {
475 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
476 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
477 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
480 // FP Stack manipulation instructions.
481 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
482 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
483 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
484 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
486 // Floating point constant loads.
487 let isReMaterializable = 1 in {
488 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
489 [(set RFP32:$dst, fpimm0)]>;
490 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
491 [(set RFP32:$dst, fpimm1)]>;
492 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
493 [(set RFP64:$dst, fpimm0)]>;
494 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
495 [(set RFP64:$dst, fpimm1)]>;
496 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
497 [(set RFP80:$dst, fpimm0)]>;
498 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
499 [(set RFP80:$dst, fpimm1)]>;
502 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
503 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
506 // Floating point compares.
507 let Defs = [EFLAGS] in {
508 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
509 []>; // FPSW = cmp ST(0) with ST(i)
510 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
511 []>; // FPSW = cmp ST(0) with ST(i)
512 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
513 []>; // FPSW = cmp ST(0) with ST(i)
515 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
516 [(X86cmp RFP32:$lhs, RFP32:$rhs),
517 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
518 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
519 [(X86cmp RFP64:$lhs, RFP64:$rhs),
520 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
521 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
522 [(X86cmp RFP80:$lhs, RFP80:$rhs),
523 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
526 let Defs = [EFLAGS], Uses = [ST0] in {
527 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
528 (outs), (ins RST:$reg),
530 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
531 (outs), (ins RST:$reg),
533 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
537 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
538 (outs), (ins RST:$reg),
539 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
540 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
541 (outs), (ins RST:$reg),
542 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
545 // Floating point flag ops.
547 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
548 (outs), (ins), "fnstsw", []>, DF;
550 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
551 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
552 [(X86fp_cwd_get16 addr:$dst)]>;
555 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
556 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
558 //===----------------------------------------------------------------------===//
559 // Non-Instruction Patterns
560 //===----------------------------------------------------------------------===//
562 // Required for RET of f32 / f64 / f80 values.
563 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
564 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
565 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
567 // Required for CALL which return f32 / f64 / f80 values.
568 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
569 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
570 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
571 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
572 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
573 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
575 // Floating point constant -0.0 and -1.0
576 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
577 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
578 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
579 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
580 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
581 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
583 // Used to conv. i64 to f64 since there isn't a SSE version.
584 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
586 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStackf32]>;
587 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStackf32]>;
588 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStackf64]>;