1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
43 [SDNPHasChain, SDNPMayStore]>;
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore]>;
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore]>;
48 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "##FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "##FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "##FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "##FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "##FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "##FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "##FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "##FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "##FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
136 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
137 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
139 // FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
140 // there are two values live out on the stack from a call or inlineasm. This
141 // magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and
142 // then FpGET_ST0*. In addition, it is invalid for any FP-using operations to
143 // occur between them.
144 def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
145 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
146 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
148 let Defs = [ST0] in {
149 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
150 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
151 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
154 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
155 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
156 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
157 // f80 instructions cannot use SSE and use neither of these.
158 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
159 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
160 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
161 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
163 // Register copies. Just copies, the shortening ones do not truncate.
164 let neverHasSideEffects = 1 in {
165 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
166 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
167 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
168 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
169 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
170 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
171 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
172 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
173 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
176 // Factoring for arithmetic.
177 multiclass FPBinary_rr<SDNode OpNode> {
178 // Register op register -> register
179 // These are separated out because they have no reversed form.
180 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
181 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
182 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
183 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
184 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
185 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
187 // The FopST0 series are not included here because of the irregularities
188 // in where the 'r' goes in assembly output.
189 // These instructions cannot address 80-bit memory.
190 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
191 // ST(0) = ST(0) + [mem]
192 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
194 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
195 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
197 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
198 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
200 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
201 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
203 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
204 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
206 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
207 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
208 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
209 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
210 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
211 // ST(0) = ST(0) + [memint]
212 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
213 [(set RFP32:$dst, (OpNode RFP32:$src1,
214 (X86fild addr:$src2, i16)))]>;
215 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
216 [(set RFP32:$dst, (OpNode RFP32:$src1,
217 (X86fild addr:$src2, i32)))]>;
218 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
219 [(set RFP64:$dst, (OpNode RFP64:$src1,
220 (X86fild addr:$src2, i16)))]>;
221 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
222 [(set RFP64:$dst, (OpNode RFP64:$src1,
223 (X86fild addr:$src2, i32)))]>;
224 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
225 [(set RFP80:$dst, (OpNode RFP80:$src1,
226 (X86fild addr:$src2, i16)))]>;
227 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
228 [(set RFP80:$dst, (OpNode RFP80:$src1,
229 (X86fild addr:$src2, i32)))]>;
230 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
231 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
232 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
233 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
236 defm ADD : FPBinary_rr<fadd>;
237 defm SUB : FPBinary_rr<fsub>;
238 defm MUL : FPBinary_rr<fmul>;
239 defm DIV : FPBinary_rr<fdiv>;
240 defm ADD : FPBinary<fadd, MRM0m, "add">;
241 defm SUB : FPBinary<fsub, MRM4m, "sub">;
242 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
243 defm MUL : FPBinary<fmul, MRM1m, "mul">;
244 defm DIV : FPBinary<fdiv, MRM6m, "div">;
245 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
247 class FPST0rInst<bits<8> o, string asm>
248 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
249 class FPrST0Inst<bits<8> o, string asm>
250 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
251 class FPrST0PInst<bits<8> o, string asm>
252 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
254 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
255 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
256 // we have to put some 'r's in and take them out of weird places.
257 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
258 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
259 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
260 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
261 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
262 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
263 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
264 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
265 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
266 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
267 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
268 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
269 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
270 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
271 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
272 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
273 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
274 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
277 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
278 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
279 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
280 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
281 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
282 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
283 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
284 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
287 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
288 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
289 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
290 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
291 defm COS : FPUnary<fcos, 0xFF, "fcos">;
293 let neverHasSideEffects = 1 in {
294 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
295 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
296 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
298 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
300 // Floating point cmovs.
301 multiclass FPCMov<PatLeaf cc> {
302 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
304 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
306 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
308 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
310 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
312 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
315 let Uses = [EFLAGS], isTwoAddress = 1 in {
316 defm CMOVB : FPCMov<X86_COND_B>;
317 defm CMOVBE : FPCMov<X86_COND_BE>;
318 defm CMOVE : FPCMov<X86_COND_E>;
319 defm CMOVP : FPCMov<X86_COND_P>;
320 defm CMOVNB : FPCMov<X86_COND_AE>;
321 defm CMOVNBE: FPCMov<X86_COND_A>;
322 defm CMOVNE : FPCMov<X86_COND_NE>;
323 defm CMOVNP : FPCMov<X86_COND_NP>;
326 // These are not factored because there's no clean way to pass DA/DB.
327 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
328 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
329 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
330 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
331 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
332 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
333 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
334 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
335 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
336 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
337 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
338 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
339 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
340 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
341 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
342 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
344 // Floating point loads & stores.
345 let canFoldAsLoad = 1 in {
346 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
347 [(set RFP32:$dst, (loadf32 addr:$src))]>;
348 let isReMaterializable = 1, mayHaveSideEffects = 1 in
349 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
350 [(set RFP64:$dst, (loadf64 addr:$src))]>;
351 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
352 [(set RFP80:$dst, (loadf80 addr:$src))]>;
354 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
355 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
356 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
357 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
358 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
359 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
360 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
361 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
362 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
363 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
364 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
365 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
366 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
367 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
368 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
369 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
370 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
371 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
372 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
373 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
374 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
375 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
376 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
377 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
379 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
380 [(store RFP32:$src, addr:$op)]>;
381 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
382 [(truncstoref32 RFP64:$src, addr:$op)]>;
383 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
384 [(store RFP64:$src, addr:$op)]>;
385 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
386 [(truncstoref32 RFP80:$src, addr:$op)]>;
387 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
388 [(truncstoref64 RFP80:$src, addr:$op)]>;
389 // FST does not support 80-bit memory target; FSTP must be used.
391 let mayStore = 1, neverHasSideEffects = 1 in {
392 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
393 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
394 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
395 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
396 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
398 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
399 [(store RFP80:$src, addr:$op)]>;
400 let mayStore = 1, neverHasSideEffects = 1 in {
401 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
402 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
403 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
404 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
405 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
406 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
407 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
408 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
409 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
413 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
414 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
415 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
416 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
417 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
418 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
420 let mayStore = 1 in {
421 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
422 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
423 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
424 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
425 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
426 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
427 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
428 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
429 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
430 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
433 // FISTTP requires SSE3 even though it's a FPStack op.
434 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
435 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
437 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
438 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
440 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
441 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
443 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
444 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
446 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
447 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
449 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
450 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
452 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
453 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
455 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
456 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
458 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
459 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
462 let mayStore = 1 in {
463 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
464 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
465 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
468 // FP Stack manipulation instructions.
469 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
470 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
471 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
472 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
474 // Floating point constant loads.
475 let isReMaterializable = 1 in {
476 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
477 [(set RFP32:$dst, fpimm0)]>;
478 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
479 [(set RFP32:$dst, fpimm1)]>;
480 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
481 [(set RFP64:$dst, fpimm0)]>;
482 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
483 [(set RFP64:$dst, fpimm1)]>;
484 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
485 [(set RFP80:$dst, fpimm0)]>;
486 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
487 [(set RFP80:$dst, fpimm1)]>;
490 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
491 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
494 // Floating point compares.
495 let Defs = [EFLAGS] in {
496 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
497 []>; // FPSW = cmp ST(0) with ST(i)
498 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
499 []>; // FPSW = cmp ST(0) with ST(i)
500 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
501 []>; // FPSW = cmp ST(0) with ST(i)
503 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
504 [(X86cmp RFP32:$lhs, RFP32:$rhs),
505 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
506 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
507 [(X86cmp RFP64:$lhs, RFP64:$rhs),
508 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
509 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
510 [(X86cmp RFP80:$lhs, RFP80:$rhs),
511 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
514 let Defs = [EFLAGS], Uses = [ST0] in {
515 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
516 (outs), (ins RST:$reg),
518 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
519 (outs), (ins RST:$reg),
521 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
525 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
526 (outs), (ins RST:$reg),
527 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
528 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
529 (outs), (ins RST:$reg),
530 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
533 // Floating point flag ops.
535 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
536 (outs), (ins), "fnstsw", []>, DF;
538 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
539 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
540 [(X86fp_cwd_get16 addr:$dst)]>;
543 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
544 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
546 //===----------------------------------------------------------------------===//
547 // Non-Instruction Patterns
548 //===----------------------------------------------------------------------===//
550 // Required for RET of f32 / f64 / f80 values.
551 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
552 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
553 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
555 // Required for CALL which return f32 / f64 / f80 values.
556 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
557 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
558 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
559 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
560 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
561 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
563 // Floating point constant -0.0 and -1.0
564 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
565 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
566 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
567 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
568 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
569 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
571 // Used to conv. i64 to f64 since there isn't a SSE version.
572 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
574 // FP extensions map onto simple pseudo-value conversions if they are to/from
576 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>,
577 Requires<[FPStackf32]>;
578 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>,
579 Requires<[FPStackf32]>;
580 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>,
581 Requires<[FPStackf64]>;
583 // FP truncations map onto simple pseudo-value conversions if they are to/from
584 // the FP stack. We have validated that only value-preserving truncations make
586 def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>,
587 Requires<[FPStackf32]>;
588 def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>,
589 Requires<[FPStackf32]>;
590 def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>,
591 Requires<[FPStackf64]>;