1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
43 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
48 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
52 //===----------------------------------------------------------------------===//
53 // FPStack pattern fragments
54 //===----------------------------------------------------------------------===//
56 def fpimm0 : PatLeaf<(fpimm), [{
57 return N->isExactlyValue(+0.0);
60 def fpimmneg0 : PatLeaf<(fpimm), [{
61 return N->isExactlyValue(-0.0);
64 def fpimm1 : PatLeaf<(fpimm), [{
65 return N->isExactlyValue(+1.0);
68 def fpimmneg1 : PatLeaf<(fpimm), [{
69 return N->isExactlyValue(-1.0);
72 // Some 'special' instructions
73 let usesCustomInserter = 1 in { // Expanded after instruction selection.
74 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
75 (outs), (ins i16mem:$dst, RFP32:$src),
76 "##FP32_TO_INT16_IN_MEM PSEUDO!",
77 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
78 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
79 (outs), (ins i32mem:$dst, RFP32:$src),
80 "##FP32_TO_INT32_IN_MEM PSEUDO!",
81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
82 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
83 (outs), (ins i64mem:$dst, RFP32:$src),
84 "##FP32_TO_INT64_IN_MEM PSEUDO!",
85 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
86 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
87 (outs), (ins i16mem:$dst, RFP64:$src),
88 "##FP64_TO_INT16_IN_MEM PSEUDO!",
89 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
90 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
91 (outs), (ins i32mem:$dst, RFP64:$src),
92 "##FP64_TO_INT32_IN_MEM PSEUDO!",
93 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
94 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
95 (outs), (ins i64mem:$dst, RFP64:$src),
96 "##FP64_TO_INT64_IN_MEM PSEUDO!",
97 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
98 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
99 (outs), (ins i16mem:$dst, RFP80:$src),
100 "##FP80_TO_INT16_IN_MEM PSEUDO!",
101 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
102 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
103 (outs), (ins i32mem:$dst, RFP80:$src),
104 "##FP80_TO_INT32_IN_MEM PSEUDO!",
105 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
106 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
107 (outs), (ins i64mem:$dst, RFP80:$src),
108 "##FP80_TO_INT64_IN_MEM PSEUDO!",
109 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
112 // All FP Stack operations are represented with four instructions here. The
113 // first three instructions, generated by the instruction selector, use "RFP32"
114 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
115 // 64-bit or 80-bit floating point values. These sizes apply to the values,
116 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
117 // copied to each other without losing information. These instructions are all
118 // pseudo instructions and use the "_Fp" suffix.
119 // In some cases there are additional variants with a mixture of different
121 // The second instruction is defined with FPI, which is the actual instruction
122 // emitted by the assembler. These use "RST" registers, although frequently
123 // the actual register(s) used are implicit. These are always 80 bits.
124 // The FP stackifier pass converts one to the other after register allocation
127 // Note that the FpI instruction should have instruction selection info (e.g.
128 // a pattern) and the FPI instruction should have emission info (e.g. opcode
129 // encoding and asm printing info).
131 // Pseudo Instructions for FP stack return values.
132 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
133 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
134 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
136 // FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
137 // there are two values live out on the stack from a call or inlineasm. This
138 // magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and
139 // then FpGET_ST0*. In addition, it is invalid for any FP-using operations to
140 // occur between them.
141 def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
142 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
143 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
145 let Defs = [ST0] in {
146 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
147 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
148 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
151 let Defs = [ST1] in {
152 def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
153 def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
154 def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
157 // FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
158 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
159 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
160 // f80 instructions cannot use SSE and use neither of these.
161 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
162 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
163 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
164 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
166 // Register copies. Just copies, the shortening ones do not truncate.
167 let neverHasSideEffects = 1 in {
168 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
169 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
170 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
171 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
172 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
173 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
174 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
175 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
176 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
179 // Factoring for arithmetic.
180 multiclass FPBinary_rr<SDNode OpNode> {
181 // Register op register -> register
182 // These are separated out because they have no reversed form.
183 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
184 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
185 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
186 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
187 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
188 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
190 // The FopST0 series are not included here because of the irregularities
191 // in where the 'r' goes in assembly output.
192 // These instructions cannot address 80-bit memory.
193 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
194 // ST(0) = ST(0) + [mem]
195 def _Fp32m : FpIf32<(outs RFP32:$dst),
196 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
198 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
199 def _Fp64m : FpIf64<(outs RFP64:$dst),
200 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
202 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
203 def _Fp64m32: FpIf64<(outs RFP64:$dst),
204 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
206 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
207 def _Fp80m32: FpI_<(outs RFP80:$dst),
208 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
210 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
211 def _Fp80m64: FpI_<(outs RFP80:$dst),
212 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
214 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
215 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
216 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> {
219 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
220 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> {
223 // ST(0) = ST(0) + [memint]
224 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),
226 [(set RFP32:$dst, (OpNode RFP32:$src1,
227 (X86fild addr:$src2, i16)))]>;
228 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),
230 [(set RFP32:$dst, (OpNode RFP32:$src1,
231 (X86fild addr:$src2, i32)))]>;
232 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),
234 [(set RFP64:$dst, (OpNode RFP64:$src1,
235 (X86fild addr:$src2, i16)))]>;
236 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),
238 [(set RFP64:$dst, (OpNode RFP64:$src1,
239 (X86fild addr:$src2, i32)))]>;
240 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),
242 [(set RFP80:$dst, (OpNode RFP80:$src1,
243 (X86fild addr:$src2, i16)))]>;
244 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),
246 [(set RFP80:$dst, (OpNode RFP80:$src1,
247 (X86fild addr:$src2, i32)))]>;
248 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
249 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> {
252 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
253 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> {
258 defm ADD : FPBinary_rr<fadd>;
259 defm SUB : FPBinary_rr<fsub>;
260 defm MUL : FPBinary_rr<fmul>;
261 defm DIV : FPBinary_rr<fdiv>;
262 defm ADD : FPBinary<fadd, MRM0m, "add">;
263 defm SUB : FPBinary<fsub, MRM4m, "sub">;
264 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
265 defm MUL : FPBinary<fmul, MRM1m, "mul">;
266 defm DIV : FPBinary<fdiv, MRM6m, "div">;
267 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
269 class FPST0rInst<bits<8> o, string asm>
270 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
271 class FPrST0Inst<bits<8> o, string asm>
272 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
273 class FPrST0PInst<bits<8> o, string asm>
274 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
276 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
277 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
278 // we have to put some 'r's in and take them out of weird places.
279 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
280 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
281 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
282 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
283 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
284 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
285 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
286 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
287 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
288 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
289 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
290 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
291 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
292 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
293 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
294 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
295 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
296 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
298 def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
299 def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">;
302 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
303 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
304 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
305 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
306 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
307 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
308 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
309 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
312 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
313 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
314 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
315 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
316 defm COS : FPUnary<fcos, 0xFF, "fcos">;
318 let neverHasSideEffects = 1 in {
319 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
320 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
321 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
323 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
325 // Versions of FP instructions that take a single memory operand. Added for the
326 // disassembler; remove as they are included with patterns elsewhere.
327 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
328 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
330 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
331 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
333 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
334 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
336 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
337 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
339 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
340 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
341 def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
343 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
344 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
346 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
347 def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
349 // Floating point cmovs.
350 class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
351 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
352 class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
353 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
355 multiclass FPCMov<PatLeaf cc> {
356 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
358 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
360 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
362 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
364 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
366 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
371 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
372 defm CMOVB : FPCMov<X86_COND_B>;
373 defm CMOVBE : FPCMov<X86_COND_BE>;
374 defm CMOVE : FPCMov<X86_COND_E>;
375 defm CMOVP : FPCMov<X86_COND_P>;
376 defm CMOVNB : FPCMov<X86_COND_AE>;
377 defm CMOVNBE: FPCMov<X86_COND_A>;
378 defm CMOVNE : FPCMov<X86_COND_NE>;
379 defm CMOVNP : FPCMov<X86_COND_NP>;
380 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
382 let Predicates = [HasCMov] in {
383 // These are not factored because there's no clean way to pass DA/DB.
384 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
385 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
386 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
387 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
388 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
389 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
390 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
391 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
392 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
393 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
394 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
395 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
396 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
397 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
398 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
399 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
400 } // Predicates = [HasCMov]
402 // Floating point loads & stores.
403 let canFoldAsLoad = 1 in {
404 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
405 [(set RFP32:$dst, (loadf32 addr:$src))]>;
406 let isReMaterializable = 1 in
407 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
408 [(set RFP64:$dst, (loadf64 addr:$src))]>;
409 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
410 [(set RFP80:$dst, (loadf80 addr:$src))]>;
412 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
413 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
414 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
415 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
416 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
417 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
418 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
419 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
420 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
421 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
422 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
423 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
424 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
425 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
426 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
427 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
428 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
429 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
430 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
431 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
432 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
433 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
434 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
435 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
437 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
438 [(store RFP32:$src, addr:$op)]>;
439 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
440 [(truncstoref32 RFP64:$src, addr:$op)]>;
441 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
442 [(store RFP64:$src, addr:$op)]>;
443 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
444 [(truncstoref32 RFP80:$src, addr:$op)]>;
445 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
446 [(truncstoref64 RFP80:$src, addr:$op)]>;
447 // FST does not support 80-bit memory target; FSTP must be used.
449 let mayStore = 1, neverHasSideEffects = 1 in {
450 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
451 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
452 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
453 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
454 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
456 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
457 [(store RFP80:$src, addr:$op)]>;
458 let mayStore = 1, neverHasSideEffects = 1 in {
459 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
460 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
461 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
462 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
463 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
464 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
465 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
466 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
467 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
471 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
472 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
473 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
474 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
475 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
476 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
478 let mayStore = 1 in {
479 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
480 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
481 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
482 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
483 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
484 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
485 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
486 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
487 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
488 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
491 // FISTTP requires SSE3 even though it's a FPStack op.
492 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
493 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
495 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
496 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
498 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
499 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
501 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
502 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
504 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
505 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
507 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
508 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
510 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
511 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
513 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
514 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
516 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
517 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
520 let mayStore = 1 in {
521 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
522 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
523 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
527 // FP Stack manipulation instructions.
528 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
529 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
530 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
531 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
533 // Floating point constant loads.
534 let isReMaterializable = 1 in {
535 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
536 [(set RFP32:$dst, fpimm0)]>;
537 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
538 [(set RFP32:$dst, fpimm1)]>;
539 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
540 [(set RFP64:$dst, fpimm0)]>;
541 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
542 [(set RFP64:$dst, fpimm1)]>;
543 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
544 [(set RFP80:$dst, fpimm0)]>;
545 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
546 [(set RFP80:$dst, fpimm1)]>;
549 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
550 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
553 // Floating point compares.
554 let Defs = [EFLAGS] in {
555 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
556 []>; // FPSW = cmp ST(0) with ST(i)
557 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
558 []>; // FPSW = cmp ST(0) with ST(i)
559 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
560 []>; // FPSW = cmp ST(0) with ST(i)
562 // CC = ST(0) cmp ST(i)
563 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
564 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>;
565 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
566 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>;
567 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
568 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
571 let Defs = [EFLAGS], Uses = [ST0] in {
572 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
573 (outs), (ins RST:$reg),
575 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
576 (outs), (ins RST:$reg),
578 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
582 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
583 (outs), (ins RST:$reg),
584 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
585 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
586 (outs), (ins RST:$reg),
587 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
590 def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
591 "fcomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
592 def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
593 "fcomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
595 // Floating point flag ops.
597 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
598 (outs), (ins), "fnstsw %ax", []>, DF;
600 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
601 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
602 [(X86fp_cwd_get16 addr:$dst)]>;
605 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
606 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
610 def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
615 def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
617 // Operandless floating-point instructions for the disassembler
619 def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
620 def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
621 def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", []>, D9;
622 def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", []>, D9;
623 def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", []>, D9;
624 def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", []>, D9;
625 def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", []>, D9;
626 def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", []>, D9;
627 def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", []>, D9;
628 def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", []>, D9;
629 def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", []>, D9;
630 def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", []>, D9;
631 def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", []>, D9;
632 def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", []>, D9;
633 def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", []>, D9;
634 def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", []>, D9;
635 def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", []>, D9;
636 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
637 def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", []>, D9;
638 def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", []>, D9;
639 def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", []>, DE;
641 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
642 "fxsave\t$dst", []>, TB;
643 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
644 "fxrstor\t$src", []>, TB;
646 //===----------------------------------------------------------------------===//
647 // Non-Instruction Patterns
648 //===----------------------------------------------------------------------===//
650 // Required for RET of f32 / f64 / f80 values.
651 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
652 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
653 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
655 // Required for CALL which return f32 / f64 / f80 values.
656 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
657 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op,
659 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
660 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op,
662 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op,
664 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op,
667 // Floating point constant -0.0 and -1.0
668 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
669 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
670 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
671 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
672 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
673 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
675 // Used to conv. i64 to f64 since there isn't a SSE version.
676 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
678 // FP extensions map onto simple pseudo-value conversions if they are to/from
680 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
681 Requires<[FPStackf32]>;
682 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
683 Requires<[FPStackf32]>;
684 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
685 Requires<[FPStackf64]>;
687 // FP truncations map onto simple pseudo-value conversions if they are to/from
688 // the FP stack. We have validated that only value-preserving truncations make
690 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
691 Requires<[FPStackf32]>;
692 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
693 Requires<[FPStackf32]>;
694 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
695 Requires<[FPStackf64]>;