1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
33 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
34 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
35 [SDNPHasChain, SDNPOutFlag]>;
36 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
38 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
39 [SDNPHasChain, SDNPInFlag]>;
40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
43 [SDNPHasChain, SDNPOutFlag]>;
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
51 def extloadf80f32 : PatFrag<(ops node:$ptr), (f80 (extloadf32 node:$ptr))>;
52 def extloadf80f64 : PatFrag<(ops node:$ptr), (f80 (extloadf64 node:$ptr))>;
53 def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>;
55 //===----------------------------------------------------------------------===//
56 // FPStack pattern fragments
57 //===----------------------------------------------------------------------===//
59 def fpimm0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(+0.0);
63 def fpimmneg0 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(-0.0);
67 def fpimm1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+1.0);
71 def fpimmneg1 : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-1.0);
75 // Some 'special' instructions
76 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
77 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
78 (outs), (ins i16mem:$dst, RFP32:$src),
79 "#FP32_TO_INT16_IN_MEM PSEUDO!",
80 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
82 (outs), (ins i32mem:$dst, RFP32:$src),
83 "#FP32_TO_INT32_IN_MEM PSEUDO!",
84 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
85 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
86 (outs), (ins i64mem:$dst, RFP32:$src),
87 "#FP32_TO_INT64_IN_MEM PSEUDO!",
88 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
89 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
90 (outs), (ins i16mem:$dst, RFP64:$src),
91 "#FP64_TO_INT16_IN_MEM PSEUDO!",
92 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
94 (outs), (ins i32mem:$dst, RFP64:$src),
95 "#FP64_TO_INT32_IN_MEM PSEUDO!",
96 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
97 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
98 (outs), (ins i64mem:$dst, RFP64:$src),
99 "#FP64_TO_INT64_IN_MEM PSEUDO!",
100 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
103 let isTerminator = 1 in
104 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
105 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
107 // All FP Stack operations are represented with three instructions here. The
108 // first two instructions, generated by the instruction selector, uses "RFP32"
109 // or "RFP64" registers: traditional register files to reference 32-bit or
110 // 64-bit floating point values. These sizes apply to the values, not the
111 // registers, which are always 64 bits; RFP32 and RFP64 can be copied to
112 // each other without losing information. These instructions are all psuedo
113 // instructions and use the "_Fp" suffix.
114 // In some cases there are additional variants with a mixture of 32-bit and
116 // The second instruction is defined with FPI, which is the actual instruction
117 // emitted by the assembler. These use "RST" registers, although frequently
118 // the actual register(s) used are implicit. These are always 64-bits.
119 // The FP stackifier pass converts one to the other after register allocation
122 // Note that the FpI instruction should have instruction selection info (e.g.
123 // a pattern) and the FPI instruction should have emission info (e.g. opcode
124 // encoding and asm printing info).
126 // Random Pseudo Instructions.
127 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
128 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
130 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
131 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
133 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
134 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
136 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
137 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
139 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
140 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
142 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
143 [(X86fpset RFP80:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
145 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
146 class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
147 FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;
149 // Register copies. Just copies, the shortening ones do not truncate.
150 def MOV_Fp3232 : FpI<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
151 def MOV_Fp3264 : FpI<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
152 def MOV_Fp6432 : FpI<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
153 def MOV_Fp6464 : FpI<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
154 def MOV_Fp8032 : FpI<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
155 def MOV_Fp3280 : FpI<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
156 def MOV_Fp8064 : FpI<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
157 def MOV_Fp6480 : FpI<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
158 def MOV_Fp8080 : FpI<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
160 // Factoring for arithmetic.
161 multiclass FPBinary_rr<SDNode OpNode> {
162 // Register op register -> register
163 // These are separated out because they have no reversed form.
164 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
165 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
166 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
167 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
168 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
169 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
171 // The FopST0 series are not included here because of the irregularities
172 // in where the 'r' goes in assembly output.
173 // These instructions cannot address 80-bit memory.
174 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
175 // ST(0) = ST(0) + [mem]
176 def _Fp32m : FpI<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
178 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
179 def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
181 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
182 def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
184 (OpNode RFP64:$src1, (extloadf64f32 addr:$src2)))]>;
185 def _Fp80m32: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
187 (OpNode RFP80:$src1, (extloadf80f32 addr:$src2)))]>;
188 def _Fp80m64: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
190 (OpNode RFP80:$src1, (extloadf80f64 addr:$src2)))]>;
191 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
192 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
193 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
194 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
195 // ST(0) = ST(0) + [memint]
196 def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
197 [(set RFP32:$dst, (OpNode RFP32:$src1,
198 (X86fild addr:$src2, i16)))]>;
199 def _FpI32m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
200 [(set RFP32:$dst, (OpNode RFP32:$src1,
201 (X86fild addr:$src2, i32)))]>;
202 def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
203 [(set RFP64:$dst, (OpNode RFP64:$src1,
204 (X86fild addr:$src2, i16)))]>;
205 def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
206 [(set RFP64:$dst, (OpNode RFP64:$src1,
207 (X86fild addr:$src2, i32)))]>;
208 def _FpI16m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
209 [(set RFP80:$dst, (OpNode RFP80:$src1,
210 (X86fild addr:$src2, i16)))]>;
211 def _FpI32m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
212 [(set RFP80:$dst, (OpNode RFP80:$src1,
213 (X86fild addr:$src2, i32)))]>;
214 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
215 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
216 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
217 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
220 defm ADD : FPBinary_rr<fadd>;
221 defm SUB : FPBinary_rr<fsub>;
222 defm MUL : FPBinary_rr<fmul>;
223 defm DIV : FPBinary_rr<fdiv>;
224 defm ADD : FPBinary<fadd, MRM0m, "add">;
225 defm SUB : FPBinary<fsub, MRM4m, "sub">;
226 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
227 defm MUL : FPBinary<fmul, MRM1m, "mul">;
228 defm DIV : FPBinary<fdiv, MRM6m, "div">;
229 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
231 class FPST0rInst<bits<8> o, string asm>
232 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
233 class FPrST0Inst<bits<8> o, string asm>
234 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
235 class FPrST0PInst<bits<8> o, string asm>
236 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
238 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
239 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
240 // we have to put some 'r's in and take them out of weird places.
241 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
242 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
243 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
244 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
245 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
246 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
247 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
248 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
249 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
250 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
251 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
252 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
253 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
254 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
255 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
256 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
257 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
258 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
261 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
262 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
263 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
264 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
265 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
266 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
267 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
268 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
271 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
272 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
273 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
274 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
275 defm COS : FPUnary<fcos, 0xFF, "fcos">;
277 def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP,
279 def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP,
281 def TST_Fp80 : FpI<(outs), (ins RFP80:$src), OneArgFP,
283 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
285 // Floating point cmovs.
286 multiclass FPCMov<PatLeaf cc> {
287 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
288 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
290 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
291 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
293 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
294 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
297 let isTwoAddress = 1 in {
298 defm CMOVB : FPCMov<X86_COND_B>;
299 defm CMOVBE : FPCMov<X86_COND_BE>;
300 defm CMOVE : FPCMov<X86_COND_E>;
301 defm CMOVP : FPCMov<X86_COND_P>;
302 defm CMOVNB : FPCMov<X86_COND_AE>;
303 defm CMOVNBE: FPCMov<X86_COND_A>;
304 defm CMOVNE : FPCMov<X86_COND_NE>;
305 defm CMOVNP : FPCMov<X86_COND_NP>;
308 // These are not factored because there's no clean way to pass DA/DB.
309 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
310 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
311 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
312 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
313 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
314 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
315 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
316 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
317 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
318 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
319 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
320 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
321 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
322 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
323 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
324 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
326 // Floating point loads & stores.
327 def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
328 [(set RFP32:$dst, (loadf32 addr:$src))]>;
329 def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
330 [(set RFP64:$dst, (loadf64 addr:$src))]>;
331 def LD_Fp80m : FpI<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
332 [(set RFP80:$dst, (loadf80 addr:$src))]>;
333 def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
334 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
335 def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
336 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
337 def ILD_Fp64m32: FpI<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
338 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
339 def ILD_Fp16m64: FpI<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
340 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
341 def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
342 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
343 def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
344 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
345 def ILD_Fp16m80: FpI<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
346 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
347 def ILD_Fp32m80: FpI<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
348 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
349 def ILD_Fp64m80: FpI<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
350 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
352 def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
353 [(store RFP32:$src, addr:$op)]>;
354 def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
355 [(truncstoref32 RFP64:$src, addr:$op)]>;
356 def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
357 [(store RFP64:$src, addr:$op)]>;
358 def ST_Fp80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
359 [(truncstoref32 RFP80:$src, addr:$op)]>;
360 def ST_Fp80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
361 [(truncstoref64 RFP80:$src, addr:$op)]>;
362 // FST does not support 80-bit memory target; FSTP must be used.
364 def ST_FpP32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
365 def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
366 def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
367 def ST_FpP80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
368 def ST_FpP80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
369 def ST_FpP80m : FpI<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
370 [(store RFP80:$src, addr:$op)]>;
371 def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
372 def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
373 def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
374 def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
375 def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
376 def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
377 def IST_Fp16m80 : FpI<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
378 def IST_Fp32m80 : FpI<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
379 def IST_Fp64m80 : FpI<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
381 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
382 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
383 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
384 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
385 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
386 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
387 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
388 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
389 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
390 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
391 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
392 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
393 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
394 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
395 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
396 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
398 // FISTTP requires SSE3 even though it's a FPStack op.
399 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
400 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
402 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
403 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
405 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
406 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
408 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
409 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
411 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
412 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
414 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
415 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
418 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
419 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
420 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
422 // FP Stack manipulation instructions.
423 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
424 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
425 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
426 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
428 // Floating point constant loads.
429 let isReMaterializable = 1 in {
430 def LD_Fp032 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
431 [(set RFP32:$dst, fpimm0)]>;
432 def LD_Fp132 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
433 [(set RFP32:$dst, fpimm1)]>;
434 def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
435 [(set RFP64:$dst, fpimm0)]>;
436 def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
437 [(set RFP64:$dst, fpimm1)]>;
438 def LD_Fp080 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
439 [(set RFP80:$dst, fpimm0)]>;
440 def LD_Fp180 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
441 [(set RFP80:$dst, fpimm1)]>;
444 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
445 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
448 // Floating point compares.
449 def UCOM_Fpr32 : FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
450 []>; // FPSW = cmp ST(0) with ST(i)
451 def UCOM_FpIr32: FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
452 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
453 def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
454 []>; // FPSW = cmp ST(0) with ST(i)
455 def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
456 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
457 def UCOM_Fpr80 : FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
458 []>; // FPSW = cmp ST(0) with ST(i)
459 def UCOM_FpIr80: FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
460 [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
462 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
463 (outs), (ins RST:$reg),
464 "fucom\t$reg">, DD, Imp<[ST0],[]>;
465 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
466 (outs), (ins RST:$reg),
467 "fucomp\t$reg">, DD, Imp<[ST0],[]>;
468 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
470 "fucompp">, DA, Imp<[ST0],[]>;
472 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
473 (outs), (ins RST:$reg),
474 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
475 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
476 (outs), (ins RST:$reg),
477 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
479 // Floating point flag ops.
480 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
481 (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
483 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
484 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
485 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
486 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
488 //===----------------------------------------------------------------------===//
489 // Non-Instruction Patterns
490 //===----------------------------------------------------------------------===//
492 // Required for RET of f32 / f64 values.
493 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
494 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
495 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
497 // Required for CALL which return f32 / f64 values.
498 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
499 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
500 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
502 // Floating point constant -0.0 and -1.0
503 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
504 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
505 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
506 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
507 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>, Requires<[FPStack]>;
508 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>, Requires<[FPStack]>;
510 // Used to conv. i64 to f64 since there isn't a SSE version.
511 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
513 def : Pat<(extloadf80f32 addr:$src),
514 (MOV_Fp3280 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
515 def : Pat<(extloadf80f64 addr:$src),
516 (MOV_Fp6480 (LD_Fp64m addr:$src))>, Requires<[FPStack]>;
517 def : Pat<(extloadf64f32 addr:$src),
518 (MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
520 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;
521 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStack]>;
522 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStack]>;