1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Some 'special' instructions
17 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
18 def FP_TO_INT16_IN_MEM : I<0, Pseudo,
19 (ops i16mem:$dst, RFP:$src),
20 "#FP_TO_INT16_IN_MEM PSEUDO!",
21 [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
22 def FP_TO_INT32_IN_MEM : I<0, Pseudo,
23 (ops i32mem:$dst, RFP:$src),
24 "#FP_TO_INT32_IN_MEM PSEUDO!",
25 [(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
26 def FP_TO_INT64_IN_MEM : I<0, Pseudo,
27 (ops i64mem:$dst, RFP:$src),
28 "#FP_TO_INT64_IN_MEM PSEUDO!",
29 [(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
32 let isTerminator = 1 in
33 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
34 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
36 // All FP Stack operations are represented with two instructions here. The
37 // first instruction, generated by the instruction selector, uses "RFP"
38 // registers: a traditional register file to reference floating point values.
39 // These instructions are all psuedo instructions and use the "Fp" prefix.
40 // The second instruction is defined with FPI, which is the actual instruction
41 // emitted by the assembler. The FP stackifier pass converts one to the other
42 // after register allocation occurs.
44 // Note that the FpI instruction should have instruction selection info (e.g.
45 // a pattern) and the FPI instruction should have emission info (e.g. opcode
46 // encoding and asm printing info).
48 // FPI - Floating Point Instruction template.
49 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
51 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
52 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
53 : X86Inst<0, Pseudo, NoImm, ops, ""> {
54 let FPForm = fp; let FPFormBits = FPForm.Value;
55 let Pattern = pattern;
58 // Random Pseudo Instructions.
59 def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP,
60 [(set RFP:$dst, X86fpget)]>; // FPR = ST(0)
63 def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP,
64 [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
66 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
67 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
68 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
71 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
74 // Add, Sub, Mul, Div.
75 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
76 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
77 def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
78 [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>;
79 def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
80 [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>;
81 def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
82 [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>;
84 class FPST0rInst<bits<8> o, string asm>
85 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
86 class FPrST0Inst<bits<8> o, string asm>
87 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
88 class FPrST0PInst<bits<8> o, string asm>
89 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
91 // Binary Ops with a memory source.
92 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
93 [(set RFP:$dst, (fadd RFP:$src1,
94 (extloadf64f32 addr:$src2)))]>;
95 // ST(0) = ST(0) + [mem32]
96 def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
97 [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>;
98 // ST(0) = ST(0) + [mem64]
99 def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
100 [(set RFP:$dst, (fmul RFP:$src1,
101 (extloadf64f32 addr:$src2)))]>;
102 // ST(0) = ST(0) * [mem32]
103 def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
104 [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>;
105 // ST(0) = ST(0) * [mem64]
106 def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
107 [(set RFP:$dst, (fsub RFP:$src1,
108 (extloadf64f32 addr:$src2)))]>;
109 // ST(0) = ST(0) - [mem32]
110 def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
111 [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>;
112 // ST(0) = ST(0) - [mem64]
113 def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
114 [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2),
116 // ST(0) = [mem32] - ST(0)
117 def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
118 [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>;
119 // ST(0) = [mem64] - ST(0)
120 def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
121 [(set RFP:$dst, (fdiv RFP:$src1,
122 (extloadf64f32 addr:$src2)))]>;
123 // ST(0) = ST(0) / [mem32]
124 def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
125 [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>;
126 // ST(0) = ST(0) / [mem64]
127 def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
128 [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2),
130 // ST(0) = [mem32] / ST(0)
131 def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
132 [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>;
133 // ST(0) = [mem64] / ST(0)
136 def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">;
137 def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">;
138 def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">;
139 def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">;
140 def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">;
141 def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">;
142 def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">;
143 def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">;
144 def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">;
145 def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">;
146 def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
147 def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
149 def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
150 [(set RFP:$dst, (fadd RFP:$src1,
151 (X86fild addr:$src2, i16)))]>;
152 // ST(0) = ST(0) + [mem16int]
153 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
154 [(set RFP:$dst, (fadd RFP:$src1,
155 (X86fild addr:$src2, i32)))]>;
156 // ST(0) = ST(0) + [mem32int]
157 def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
158 [(set RFP:$dst, (fmul RFP:$src1,
159 (X86fild addr:$src2, i16)))]>;
160 // ST(0) = ST(0) * [mem16int]
161 def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
162 [(set RFP:$dst, (fmul RFP:$src1,
163 (X86fild addr:$src2, i32)))]>;
164 // ST(0) = ST(0) * [mem32int]
165 def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
166 [(set RFP:$dst, (fsub RFP:$src1,
167 (X86fild addr:$src2, i16)))]>;
168 // ST(0) = ST(0) - [mem16int]
169 def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
170 [(set RFP:$dst, (fsub RFP:$src1,
171 (X86fild addr:$src2, i32)))]>;
172 // ST(0) = ST(0) - [mem32int]
173 def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
174 [(set RFP:$dst, (fsub (X86fild addr:$src2, i16),
176 // ST(0) = [mem16int] - ST(0)
177 def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
178 [(set RFP:$dst, (fsub (X86fild addr:$src2, i32),
180 // ST(0) = [mem32int] - ST(0)
181 def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
182 [(set RFP:$dst, (fdiv RFP:$src1,
183 (X86fild addr:$src2, i16)))]>;
184 // ST(0) = ST(0) / [mem16int]
185 def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
186 [(set RFP:$dst, (fdiv RFP:$src1,
187 (X86fild addr:$src2, i32)))]>;
188 // ST(0) = ST(0) / [mem32int]
189 def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
190 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16),
192 // ST(0) = [mem16int] / ST(0)
193 def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
194 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32),
196 // ST(0) = [mem32int] / ST(0)
198 def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
199 def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
200 def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
201 def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
202 def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
203 def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
204 def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
205 def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
206 def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
207 def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">;
208 def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
209 def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">;
211 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
212 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
213 // we have to put some 'r's in and take them out of weird places.
214 def FADDST0r : FPST0rInst <0xC0, "fadd $op">;
215 def FADDrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
216 def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">;
217 def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">;
218 def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
219 def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
220 def FSUBST0r : FPST0rInst <0xE0, "fsub $op">;
221 def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
222 def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
223 def FMULST0r : FPST0rInst <0xC8, "fmul $op">;
224 def FMULrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
225 def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
226 def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">;
227 def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
228 def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
229 def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">;
230 def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
231 def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
235 def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
236 [(set RFP:$dst, (fneg RFP:$src))]>;
237 def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
238 [(set RFP:$dst, (fabs RFP:$src))]>;
239 def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
240 [(set RFP:$dst, (fsqrt RFP:$src))]>;
241 def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
242 [(set RFP:$dst, (fsin RFP:$src))]>;
243 def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
244 [(set RFP:$dst, (fcos RFP:$src))]>;
245 def FpTST : FpI<(ops RFP:$src), OneArgFP,
248 def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9;
249 def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9;
250 def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9;
251 def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9;
252 def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9;
253 def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
256 // Floating point cmovs.
257 let isTwoAddress = 1 in {
258 def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
259 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
261 def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
262 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
264 def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
265 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
267 def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
268 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
270 def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
271 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
273 def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
274 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
276 def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
277 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
279 def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
280 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
284 def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op),
285 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
286 def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
287 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
288 def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op),
289 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
290 def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
291 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
292 def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op),
293 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
294 def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
295 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
296 def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
297 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
298 def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),
299 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
301 // Floating point loads & stores.
302 def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP,
303 [(set RFP:$dst, (extloadf64f32 addr:$src))]>;
304 def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
305 [(set RFP:$dst, (loadf64 addr:$src))]>;
306 def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
307 [(set RFP:$dst, (X86fild addr:$src, i16))]>;
308 def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
309 [(set RFP:$dst, (X86fild addr:$src, i32))]>;
310 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
311 [(set RFP:$dst, (X86fild addr:$src, i64))]>;
313 def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
314 [(truncstore RFP:$src, addr:$op, f32)]>;
315 def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
316 [(store RFP:$src, addr:$op)]>;
318 def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
319 def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
320 def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
321 def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>;
322 def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>;
324 def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
325 def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
326 def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
327 def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
328 def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
329 def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
330 def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
331 def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
332 def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
333 def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
334 def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
335 def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
336 def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
337 def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
339 // FISTTP requires SSE3 even though it's a FPStack op.
340 def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP,
341 [(X86fp_to_i16mem RFP:$src, addr:$op)]>,
343 def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP,
344 [(X86fp_to_i32mem RFP:$src, addr:$op)]>,
346 def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP,
347 [(X86fp_to_i64mem RFP:$src, addr:$op)]>,
350 def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
351 def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
352 def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
354 // FP Stack manipulation instructions.
355 def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
356 def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
357 def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
358 def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
360 // Floating point constant loads.
361 def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
362 [(set RFP:$dst, fp64imm0)]>;
363 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
364 [(set RFP:$dst, fp64imm1)]>;
366 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
367 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
370 // Floating point compares.
371 def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
372 []>; // FPSW = cmp ST(0) with ST(i)
373 def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
374 [(X86cmp RFP:$lhs, RFP:$rhs)]>; // CC = cmp ST(0) with ST(i)
376 def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
378 "fucom $reg">, DD, Imp<[ST0],[]>;
379 def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
381 "fucomp $reg">, DD, Imp<[ST0],[]>;
382 def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
384 "fucompp">, DA, Imp<[ST0],[]>;
386 def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
388 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
389 def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
391 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
394 // Floating point flag ops.
395 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
396 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
398 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
399 (ops i16mem:$dst), "fnstcw $dst", []>;
400 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
401 (ops i16mem:$dst), "fldcw $dst", []>;
403 //===----------------------------------------------------------------------===//
404 // Non-Instruction Patterns
405 //===----------------------------------------------------------------------===//
407 // Required for RET of f32 / f64 values.
408 def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
409 def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
411 // Required for CALL which return f32 / f64 values.
412 def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
413 def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
415 // Floating point constant -0.0 and -1.0
416 def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
417 def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
419 // Used to conv. i64 to f64 since there isn't a SSE version.
420 def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>;