1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
43 [SDNPHasChain, SDNPMayStore]>;
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore]>;
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore]>;
48 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomInserter = 1 in { // Expanded after instruction selection.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "##FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "##FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "##FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "##FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "##FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "##FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "##FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "##FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "##FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
136 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
137 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
139 // FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
140 // there are two values live out on the stack from a call or inlineasm. This
141 // magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and
142 // then FpGET_ST0*. In addition, it is invalid for any FP-using operations to
143 // occur between them.
144 def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
145 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
146 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
148 let Defs = [ST0] in {
149 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
150 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
151 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
154 let Defs = [ST1] in {
155 def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
156 def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
157 def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
160 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
161 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
162 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
163 // f80 instructions cannot use SSE and use neither of these.
164 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
165 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
166 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
167 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
169 // Register copies. Just copies, the shortening ones do not truncate.
170 let neverHasSideEffects = 1 in {
171 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
172 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
173 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
174 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
175 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
176 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
177 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
178 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
179 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
182 // Factoring for arithmetic.
183 multiclass FPBinary_rr<SDNode OpNode> {
184 // Register op register -> register
185 // These are separated out because they have no reversed form.
186 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
187 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
188 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
189 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
190 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
191 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
193 // The FopST0 series are not included here because of the irregularities
194 // in where the 'r' goes in assembly output.
195 // These instructions cannot address 80-bit memory.
196 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
197 // ST(0) = ST(0) + [mem]
198 def _Fp32m : FpIf32<(outs RFP32:$dst),
199 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
201 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
202 def _Fp64m : FpIf64<(outs RFP64:$dst),
203 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
205 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
206 def _Fp64m32: FpIf64<(outs RFP64:$dst),
207 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
209 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
210 def _Fp80m32: FpI_<(outs RFP80:$dst),
211 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
213 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
214 def _Fp80m64: FpI_<(outs RFP80:$dst),
215 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
217 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
218 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
219 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> {
222 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
223 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> {
226 // ST(0) = ST(0) + [memint]
227 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),
229 [(set RFP32:$dst, (OpNode RFP32:$src1,
230 (X86fild addr:$src2, i16)))]>;
231 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),
233 [(set RFP32:$dst, (OpNode RFP32:$src1,
234 (X86fild addr:$src2, i32)))]>;
235 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),
237 [(set RFP64:$dst, (OpNode RFP64:$src1,
238 (X86fild addr:$src2, i16)))]>;
239 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),
241 [(set RFP64:$dst, (OpNode RFP64:$src1,
242 (X86fild addr:$src2, i32)))]>;
243 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),
245 [(set RFP80:$dst, (OpNode RFP80:$src1,
246 (X86fild addr:$src2, i16)))]>;
247 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),
249 [(set RFP80:$dst, (OpNode RFP80:$src1,
250 (X86fild addr:$src2, i32)))]>;
251 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
252 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> {
255 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
256 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> {
261 defm ADD : FPBinary_rr<fadd>;
262 defm SUB : FPBinary_rr<fsub>;
263 defm MUL : FPBinary_rr<fmul>;
264 defm DIV : FPBinary_rr<fdiv>;
265 defm ADD : FPBinary<fadd, MRM0m, "add">;
266 defm SUB : FPBinary<fsub, MRM4m, "sub">;
267 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
268 defm MUL : FPBinary<fmul, MRM1m, "mul">;
269 defm DIV : FPBinary<fdiv, MRM6m, "div">;
270 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
272 class FPST0rInst<bits<8> o, string asm>
273 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
274 class FPrST0Inst<bits<8> o, string asm>
275 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
276 class FPrST0PInst<bits<8> o, string asm>
277 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
279 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
280 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
281 // we have to put some 'r's in and take them out of weird places.
282 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
283 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
284 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
285 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
286 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
287 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
288 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
289 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
290 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
291 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
292 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
293 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
294 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
295 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
296 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
297 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
298 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
299 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
301 def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
302 def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">;
305 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
306 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
307 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
308 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
309 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
310 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
311 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
312 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
315 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
316 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
317 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
318 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
319 defm COS : FPUnary<fcos, 0xFF, "fcos">;
321 let neverHasSideEffects = 1 in {
322 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
323 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
324 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
326 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
328 // Versions of FP instructions that take a single memory operand. Added for the
329 // disassembler; remove as they are included with patterns elsewhere.
330 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{l}\t$src">;
331 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{l}\t$src">;
333 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
334 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
336 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
337 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
339 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{ll}\t$src">;
340 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{ll}\t$src">;
342 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
343 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
344 def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
346 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{w}\t$src">;
347 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{w}\t$src">;
349 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
350 def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
352 // Floating point cmovs.
353 multiclass FPCMov<PatLeaf cc> {
354 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
356 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
358 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
360 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
362 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
364 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
367 let Uses = [EFLAGS], isTwoAddress = 1 in {
368 defm CMOVB : FPCMov<X86_COND_B>;
369 defm CMOVBE : FPCMov<X86_COND_BE>;
370 defm CMOVE : FPCMov<X86_COND_E>;
371 defm CMOVP : FPCMov<X86_COND_P>;
372 defm CMOVNB : FPCMov<X86_COND_AE>;
373 defm CMOVNBE: FPCMov<X86_COND_A>;
374 defm CMOVNE : FPCMov<X86_COND_NE>;
375 defm CMOVNP : FPCMov<X86_COND_NP>;
378 // These are not factored because there's no clean way to pass DA/DB.
379 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
380 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
381 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
382 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
383 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
384 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
385 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
386 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
387 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
388 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
389 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
390 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
391 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
392 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
393 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
394 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
396 // Floating point loads & stores.
397 let canFoldAsLoad = 1 in {
398 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
399 [(set RFP32:$dst, (loadf32 addr:$src))]>;
400 let isReMaterializable = 1 in
401 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
402 [(set RFP64:$dst, (loadf64 addr:$src))]>;
403 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
404 [(set RFP80:$dst, (loadf80 addr:$src))]>;
406 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
407 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
408 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
409 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
410 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
411 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
412 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
413 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
414 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
415 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
416 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
417 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
418 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
419 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
420 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
421 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
422 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
423 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
424 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
425 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
426 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
427 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
428 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
429 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
431 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
432 [(store RFP32:$src, addr:$op)]>;
433 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
434 [(truncstoref32 RFP64:$src, addr:$op)]>;
435 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
436 [(store RFP64:$src, addr:$op)]>;
437 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
438 [(truncstoref32 RFP80:$src, addr:$op)]>;
439 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
440 [(truncstoref64 RFP80:$src, addr:$op)]>;
441 // FST does not support 80-bit memory target; FSTP must be used.
443 let mayStore = 1, neverHasSideEffects = 1 in {
444 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
445 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
446 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
447 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
448 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
450 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
451 [(store RFP80:$src, addr:$op)]>;
452 let mayStore = 1, neverHasSideEffects = 1 in {
453 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
454 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
455 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
456 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
457 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
458 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
459 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
460 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
461 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
465 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
466 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
467 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
468 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
469 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
470 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
472 let mayStore = 1 in {
473 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
474 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
475 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
476 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
477 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
478 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
479 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
480 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
481 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
482 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
485 // FISTTP requires SSE3 even though it's a FPStack op.
486 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
487 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
489 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
490 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
492 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
493 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
495 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
496 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
498 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
499 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
501 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
502 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
504 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
505 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
507 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
508 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
510 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
511 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
514 let mayStore = 1 in {
515 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
516 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
517 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
521 // FP Stack manipulation instructions.
522 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
523 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
524 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
525 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
527 // Floating point constant loads.
528 let isReMaterializable = 1 in {
529 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
530 [(set RFP32:$dst, fpimm0)]>;
531 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
532 [(set RFP32:$dst, fpimm1)]>;
533 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
534 [(set RFP64:$dst, fpimm0)]>;
535 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
536 [(set RFP64:$dst, fpimm1)]>;
537 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
538 [(set RFP80:$dst, fpimm0)]>;
539 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
540 [(set RFP80:$dst, fpimm1)]>;
543 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
544 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
547 // Floating point compares.
548 let Defs = [EFLAGS] in {
549 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
550 []>; // FPSW = cmp ST(0) with ST(i)
551 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
552 []>; // FPSW = cmp ST(0) with ST(i)
553 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
554 []>; // FPSW = cmp ST(0) with ST(i)
556 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
557 [(X86cmp RFP32:$lhs, RFP32:$rhs),
558 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
559 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
560 [(X86cmp RFP64:$lhs, RFP64:$rhs),
561 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
562 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
563 [(X86cmp RFP80:$lhs, RFP80:$rhs),
564 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
567 let Defs = [EFLAGS], Uses = [ST0] in {
568 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
569 (outs), (ins RST:$reg),
571 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
572 (outs), (ins RST:$reg),
574 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
578 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
579 (outs), (ins RST:$reg),
580 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
581 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
582 (outs), (ins RST:$reg),
583 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
586 def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
587 "fcomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
588 def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
589 "fcomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
591 // Floating point flag ops.
593 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
594 (outs), (ins), "fnstsw %ax", []>, DF;
596 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
597 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
598 [(X86fp_cwd_get16 addr:$dst)]>;
601 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
602 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
606 def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
611 def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
613 // Operandless floating-point instructions for the disassembler
615 def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
616 def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
617 def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", []>, D9;
618 def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", []>, D9;
619 def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", []>, D9;
620 def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", []>, D9;
621 def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", []>, D9;
622 def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", []>, D9;
623 def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", []>, D9;
624 def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", []>, D9;
625 def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", []>, D9;
626 def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", []>, D9;
627 def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", []>, D9;
628 def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", []>, D9;
629 def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", []>, D9;
630 def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", []>, D9;
631 def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", []>, D9;
632 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
633 def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", []>, D9;
634 def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", []>, D9;
635 def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", []>, DE;
637 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
638 "fxsave\t$dst", []>, TB;
639 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
640 "fxrstor\t$src", []>, TB;
642 //===----------------------------------------------------------------------===//
643 // Non-Instruction Patterns
644 //===----------------------------------------------------------------------===//
646 // Required for RET of f32 / f64 / f80 values.
647 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
648 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
649 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
651 // Required for CALL which return f32 / f64 / f80 values.
652 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
653 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op,
655 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
656 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op,
658 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op,
660 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op,
663 // Floating point constant -0.0 and -1.0
664 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
665 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
666 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
667 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
668 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
669 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
671 // Used to conv. i64 to f64 since there isn't a SSE version.
672 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
674 // FP extensions map onto simple pseudo-value conversions if they are to/from
676 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>,
677 Requires<[FPStackf32]>;
678 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>,
679 Requires<[FPStackf32]>;
680 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>,
681 Requires<[FPStackf64]>;
683 // FP truncations map onto simple pseudo-value conversions if they are to/from
684 // the FP stack. We have validated that only value-preserving truncations make
686 def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>,
687 Requires<[FPStackf32]>;
688 def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>,
689 Requires<[FPStackf32]>;
690 def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>,
691 Requires<[FPStackf64]>;