1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInGlue, SDNPMayStore,
39 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
40 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
41 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
42 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
50 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
51 [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
54 //===----------------------------------------------------------------------===//
55 // FPStack pattern fragments
56 //===----------------------------------------------------------------------===//
58 def fpimm0 : PatLeaf<(fpimm), [{
59 return N->isExactlyValue(+0.0);
62 def fpimmneg0 : PatLeaf<(fpimm), [{
63 return N->isExactlyValue(-0.0);
66 def fpimm1 : PatLeaf<(fpimm), [{
67 return N->isExactlyValue(+1.0);
70 def fpimmneg1 : PatLeaf<(fpimm), [{
71 return N->isExactlyValue(-1.0);
74 // Some 'special' instructions
75 let usesCustomInserter = 1 in { // Expanded after instruction selection.
76 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
77 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
78 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
79 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
80 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
81 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
82 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
83 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
84 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
85 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
86 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
87 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
88 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
89 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
90 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
91 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
92 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
93 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
96 // All FP Stack operations are represented with four instructions here. The
97 // first three instructions, generated by the instruction selector, use "RFP32"
98 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
99 // 64-bit or 80-bit floating point values. These sizes apply to the values,
100 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
101 // copied to each other without losing information. These instructions are all
102 // pseudo instructions and use the "_Fp" suffix.
103 // In some cases there are additional variants with a mixture of different
105 // The second instruction is defined with FPI, which is the actual instruction
106 // emitted by the assembler. These use "RST" registers, although frequently
107 // the actual register(s) used are implicit. These are always 80 bits.
108 // The FP stackifier pass converts one to the other after register allocation
111 // Note that the FpI instruction should have instruction selection info (e.g.
112 // a pattern) and the FPI instruction should have emission info (e.g. opcode
113 // encoding and asm printing info).
115 // Pseudo Instructions for FP stack return values.
116 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
117 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
118 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
120 // FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
121 // there are two values live out on the stack from a call or inlineasm. This
122 // magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and
123 // then FpGET_ST0*. In addition, it is invalid for any FP-using operations to
124 // occur between them.
125 def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
126 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
127 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
129 let Defs = [ST0] in {
130 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
131 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
132 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
135 let Defs = [ST1] in {
136 def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
137 def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
138 def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
141 // FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
142 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
143 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
144 // f80 instructions cannot use SSE and use neither of these.
145 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
146 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
147 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
148 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
150 // Register copies. Just copies, the shortening ones do not truncate.
151 let neverHasSideEffects = 1 in {
152 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
153 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
154 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
155 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
156 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
157 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
158 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
159 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
160 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
163 // Factoring for arithmetic.
164 multiclass FPBinary_rr<SDNode OpNode> {
165 // Register op register -> register
166 // These are separated out because they have no reversed form.
167 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
168 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
169 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
170 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
171 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
172 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
174 // The FopST0 series are not included here because of the irregularities
175 // in where the 'r' goes in assembly output.
176 // These instructions cannot address 80-bit memory.
177 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
178 // ST(0) = ST(0) + [mem]
179 def _Fp32m : FpIf32<(outs RFP32:$dst),
180 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
182 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
183 def _Fp64m : FpIf64<(outs RFP64:$dst),
184 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
186 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
187 def _Fp64m32: FpIf64<(outs RFP64:$dst),
188 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
190 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
191 def _Fp80m32: FpI_<(outs RFP80:$dst),
192 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
194 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
195 def _Fp80m64: FpI_<(outs RFP80:$dst),
196 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
198 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
199 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
200 !strconcat("f", asmstring, "{s}\t$src")> {
203 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
204 !strconcat("f", asmstring, "{l}\t$src")> {
207 // ST(0) = ST(0) + [memint]
208 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),
210 [(set RFP32:$dst, (OpNode RFP32:$src1,
211 (X86fild addr:$src2, i16)))]>;
212 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),
214 [(set RFP32:$dst, (OpNode RFP32:$src1,
215 (X86fild addr:$src2, i32)))]>;
216 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),
218 [(set RFP64:$dst, (OpNode RFP64:$src1,
219 (X86fild addr:$src2, i16)))]>;
220 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),
222 [(set RFP64:$dst, (OpNode RFP64:$src1,
223 (X86fild addr:$src2, i32)))]>;
224 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),
226 [(set RFP80:$dst, (OpNode RFP80:$src1,
227 (X86fild addr:$src2, i16)))]>;
228 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),
230 [(set RFP80:$dst, (OpNode RFP80:$src1,
231 (X86fild addr:$src2, i32)))]>;
232 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
233 !strconcat("fi", asmstring, "{s}\t$src")> {
236 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
237 !strconcat("fi", asmstring, "{l}\t$src")> {
242 defm ADD : FPBinary_rr<fadd>;
243 defm SUB : FPBinary_rr<fsub>;
244 defm MUL : FPBinary_rr<fmul>;
245 defm DIV : FPBinary_rr<fdiv>;
246 defm ADD : FPBinary<fadd, MRM0m, "add">;
247 defm SUB : FPBinary<fsub, MRM4m, "sub">;
248 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
249 defm MUL : FPBinary<fmul, MRM1m, "mul">;
250 defm DIV : FPBinary<fdiv, MRM6m, "div">;
251 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
253 class FPST0rInst<bits<8> o, string asm>
254 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
255 class FPrST0Inst<bits<8> o, string asm>
256 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
257 class FPrST0PInst<bits<8> o, string asm>
258 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
260 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
261 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
262 // we have to put some 'r's in and take them out of weird places.
263 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
264 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
265 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
266 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
267 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
268 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
269 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
270 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
271 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
272 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
273 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
274 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
275 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
276 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
277 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
278 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
279 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
280 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
282 def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
283 def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">;
286 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
287 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
288 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
289 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
290 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
291 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
292 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
293 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
296 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
297 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
298 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
299 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
300 defm COS : FPUnary<fcos, 0xFF, "fcos">;
302 let neverHasSideEffects = 1 in {
303 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
304 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
305 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
307 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
309 // Versions of FP instructions that take a single memory operand. Added for the
310 // disassembler; remove as they are included with patterns elsewhere.
311 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
312 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
314 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
315 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
317 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
318 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
320 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
321 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
323 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
324 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
325 def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
327 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
328 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
330 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
331 def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
333 // Floating point cmovs.
334 class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
335 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
336 class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
337 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
339 multiclass FPCMov<PatLeaf cc> {
340 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
342 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
344 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
346 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
348 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
350 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
355 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
356 defm CMOVB : FPCMov<X86_COND_B>;
357 defm CMOVBE : FPCMov<X86_COND_BE>;
358 defm CMOVE : FPCMov<X86_COND_E>;
359 defm CMOVP : FPCMov<X86_COND_P>;
360 defm CMOVNB : FPCMov<X86_COND_AE>;
361 defm CMOVNBE: FPCMov<X86_COND_A>;
362 defm CMOVNE : FPCMov<X86_COND_NE>;
363 defm CMOVNP : FPCMov<X86_COND_NP>;
364 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
366 let Predicates = [HasCMov] in {
367 // These are not factored because there's no clean way to pass DA/DB.
368 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
369 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
370 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
371 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
372 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
373 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
374 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
375 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
376 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
377 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
378 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
379 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
380 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
381 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
382 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
383 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
384 } // Predicates = [HasCMov]
386 // Floating point loads & stores.
387 let canFoldAsLoad = 1 in {
388 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
389 [(set RFP32:$dst, (loadf32 addr:$src))]>;
390 let isReMaterializable = 1 in
391 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
392 [(set RFP64:$dst, (loadf64 addr:$src))]>;
393 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
394 [(set RFP80:$dst, (loadf80 addr:$src))]>;
396 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
397 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
398 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
399 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
400 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
401 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
402 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
403 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
404 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
405 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
406 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
407 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
408 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
409 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
410 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
411 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
412 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
413 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
414 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
415 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
416 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
417 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
418 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
419 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
421 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
422 [(store RFP32:$src, addr:$op)]>;
423 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
424 [(truncstoref32 RFP64:$src, addr:$op)]>;
425 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
426 [(store RFP64:$src, addr:$op)]>;
427 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
428 [(truncstoref32 RFP80:$src, addr:$op)]>;
429 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
430 [(truncstoref64 RFP80:$src, addr:$op)]>;
431 // FST does not support 80-bit memory target; FSTP must be used.
433 let mayStore = 1, neverHasSideEffects = 1 in {
434 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
435 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
436 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
437 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
438 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
440 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
441 [(store RFP80:$src, addr:$op)]>;
442 let mayStore = 1, neverHasSideEffects = 1 in {
443 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
444 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
445 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
446 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
447 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
448 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
449 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
450 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
451 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
455 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
456 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
457 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
458 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
459 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
460 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
462 let mayStore = 1 in {
463 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
464 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
465 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
466 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
467 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
468 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
469 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
470 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
471 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
472 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
475 // FISTTP requires SSE3 even though it's a FPStack op.
476 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
477 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
479 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
480 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
482 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
483 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
485 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
486 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
488 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
489 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
491 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
492 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
494 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
495 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
497 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
498 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
500 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
501 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
504 let mayStore = 1 in {
505 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
506 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
507 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
511 // FP Stack manipulation instructions.
512 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
513 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
514 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
515 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
517 // Floating point constant loads.
518 let isReMaterializable = 1 in {
519 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
520 [(set RFP32:$dst, fpimm0)]>;
521 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
522 [(set RFP32:$dst, fpimm1)]>;
523 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
524 [(set RFP64:$dst, fpimm0)]>;
525 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
526 [(set RFP64:$dst, fpimm1)]>;
527 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
528 [(set RFP80:$dst, fpimm0)]>;
529 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
530 [(set RFP80:$dst, fpimm1)]>;
533 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
534 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
537 // Floating point compares.
538 let Defs = [EFLAGS] in {
539 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
540 []>; // FPSW = cmp ST(0) with ST(i)
541 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
542 []>; // FPSW = cmp ST(0) with ST(i)
543 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
544 []>; // FPSW = cmp ST(0) with ST(i)
546 // CC = ST(0) cmp ST(i)
547 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
548 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>;
549 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
550 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>;
551 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
552 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
555 let Defs = [EFLAGS], Uses = [ST0] in {
556 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
557 (outs), (ins RST:$reg),
559 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
560 (outs), (ins RST:$reg),
562 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
566 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
567 (outs), (ins RST:$reg),
569 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
570 (outs), (ins RST:$reg),
571 "fucompi\t$reg">, DF;
574 def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
576 def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
579 // Floating point flag ops.
581 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
582 (outs), (ins), "fnstsw %ax", []>, DF;
584 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
585 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
586 [(X86fp_cwd_get16 addr:$dst)]>;
589 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
590 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
592 // FPU control instructions
593 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
594 def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
599 def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
601 // Operandless floating-point instructions for the disassembler.
602 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
604 def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
605 def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
606 def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", []>, D9;
607 def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", []>, D9;
608 def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", []>, D9;
609 def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", []>, D9;
610 def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", []>, D9;
611 def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", []>, D9;
612 def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", []>, D9;
613 def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", []>, D9;
614 def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", []>, D9;
615 def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", []>, D9;
616 def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", []>, D9;
617 def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", []>, D9;
618 def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", []>, D9;
619 def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", []>, D9;
620 def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", []>, D9;
621 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
622 def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", []>, D9;
623 def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", []>, D9;
624 def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", []>, DE;
626 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
627 "fxsave\t$dst", []>, TB;
628 def FXSAVE64 : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
629 "fxsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
630 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
631 "fxrstor\t$src", []>, TB;
632 def FXRSTOR64 : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
633 "fxrstorq\t$src", []>, TB, REX_W, Requires<[In64BitMode]>;
635 //===----------------------------------------------------------------------===//
636 // Non-Instruction Patterns
637 //===----------------------------------------------------------------------===//
639 // Required for RET of f32 / f64 / f80 values.
640 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
641 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
642 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
644 // Required for CALL which return f32 / f64 / f80 values.
645 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
646 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op,
648 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
649 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op,
651 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op,
653 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op,
656 // Floating point constant -0.0 and -1.0
657 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
658 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
659 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
660 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
661 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
662 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
664 // Used to conv. i64 to f64 since there isn't a SSE version.
665 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
667 // FP extensions map onto simple pseudo-value conversions if they are to/from
669 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
670 Requires<[FPStackf32]>;
671 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
672 Requires<[FPStackf32]>;
673 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
674 Requires<[FPStackf64]>;
676 // FP truncations map onto simple pseudo-value conversions if they are to/from
677 // the FP stack. We have validated that only value-preserving truncations make
679 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
680 Requires<[FPStackf32]>;
681 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
682 Requires<[FPStackf32]>;
683 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
684 Requires<[FPStackf64]>;