1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
33 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
34 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
35 [SDNPHasChain, SDNPOutFlag]>;
36 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
38 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
39 [SDNPHasChain, SDNPInFlag]>;
40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
43 [SDNPHasChain, SDNPOutFlag]>;
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "#FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "#FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "#FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "#FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "#FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "#FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "#FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "#FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "#FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
136 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
138 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
139 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
141 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
142 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
144 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
145 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
147 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
148 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
150 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
151 [(X86fpset RFP80:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
153 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
154 // Note that f80-only instructions are used even in SSE mode and use FpI_
155 // not this predicate.
156 class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
157 FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;
159 // Register copies. Just copies, the shortening ones do not truncate.
160 def MOV_Fp3232 : FpI<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
161 def MOV_Fp3264 : FpI<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
162 def MOV_Fp6432 : FpI<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
163 def MOV_Fp6464 : FpI<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
164 def MOV_Fp8032 : FpI<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
165 def MOV_Fp3280 : FpI<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
166 def MOV_Fp8064 : FpI<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
167 def MOV_Fp6480 : FpI<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
168 def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
170 // Factoring for arithmetic.
171 multiclass FPBinary_rr<SDNode OpNode> {
172 // Register op register -> register
173 // These are separated out because they have no reversed form.
174 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
175 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
176 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
177 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
178 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
179 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
181 // The FopST0 series are not included here because of the irregularities
182 // in where the 'r' goes in assembly output.
183 // These instructions cannot address 80-bit memory.
184 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
185 // ST(0) = ST(0) + [mem]
186 def _Fp32m : FpI<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
188 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
189 def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
191 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
192 def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
194 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
195 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
197 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
198 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
200 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
201 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
202 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
203 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
204 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
205 // ST(0) = ST(0) + [memint]
206 def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
207 [(set RFP32:$dst, (OpNode RFP32:$src1,
208 (X86fild addr:$src2, i16)))]>;
209 def _FpI32m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
210 [(set RFP32:$dst, (OpNode RFP32:$src1,
211 (X86fild addr:$src2, i32)))]>;
212 def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
213 [(set RFP64:$dst, (OpNode RFP64:$src1,
214 (X86fild addr:$src2, i16)))]>;
215 def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
216 [(set RFP64:$dst, (OpNode RFP64:$src1,
217 (X86fild addr:$src2, i32)))]>;
218 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
219 [(set RFP80:$dst, (OpNode RFP80:$src1,
220 (X86fild addr:$src2, i16)))]>;
221 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
222 [(set RFP80:$dst, (OpNode RFP80:$src1,
223 (X86fild addr:$src2, i32)))]>;
224 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
225 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
226 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
227 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
230 defm ADD : FPBinary_rr<fadd>;
231 defm SUB : FPBinary_rr<fsub>;
232 defm MUL : FPBinary_rr<fmul>;
233 defm DIV : FPBinary_rr<fdiv>;
234 defm ADD : FPBinary<fadd, MRM0m, "add">;
235 defm SUB : FPBinary<fsub, MRM4m, "sub">;
236 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
237 defm MUL : FPBinary<fmul, MRM1m, "mul">;
238 defm DIV : FPBinary<fdiv, MRM6m, "div">;
239 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
241 class FPST0rInst<bits<8> o, string asm>
242 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
243 class FPrST0Inst<bits<8> o, string asm>
244 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
245 class FPrST0PInst<bits<8> o, string asm>
246 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
248 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
249 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
250 // we have to put some 'r's in and take them out of weird places.
251 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
252 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
253 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
254 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
255 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
256 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
257 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
258 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
259 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
260 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
261 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
262 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
263 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
264 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
265 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
266 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
267 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
268 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
271 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
272 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
273 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
274 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
275 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
276 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
277 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
278 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
281 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
282 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
283 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
284 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
285 defm COS : FPUnary<fcos, 0xFF, "fcos">;
287 def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP,
289 def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP,
291 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP,
293 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
295 // Floating point cmovs.
296 multiclass FPCMov<PatLeaf cc> {
297 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
298 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
300 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
301 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
303 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
304 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
307 let isTwoAddress = 1 in {
308 defm CMOVB : FPCMov<X86_COND_B>;
309 defm CMOVBE : FPCMov<X86_COND_BE>;
310 defm CMOVE : FPCMov<X86_COND_E>;
311 defm CMOVP : FPCMov<X86_COND_P>;
312 defm CMOVNB : FPCMov<X86_COND_AE>;
313 defm CMOVNBE: FPCMov<X86_COND_A>;
314 defm CMOVNE : FPCMov<X86_COND_NE>;
315 defm CMOVNP : FPCMov<X86_COND_NP>;
318 // These are not factored because there's no clean way to pass DA/DB.
319 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
320 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
321 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
322 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
323 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
324 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
325 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
326 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
327 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
328 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
329 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
330 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
331 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
332 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
333 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
334 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
336 // Floating point loads & stores.
337 def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
338 [(set RFP32:$dst, (loadf32 addr:$src))]>;
339 def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
340 [(set RFP64:$dst, (loadf64 addr:$src))]>;
341 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
342 [(set RFP80:$dst, (loadf80 addr:$src))]>;
343 def LD_Fp32m64 : FpI<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
344 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
345 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
346 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
347 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
348 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
349 def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
350 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
351 def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
352 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
353 def ILD_Fp64m32: FpI<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
354 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
355 def ILD_Fp16m64: FpI<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
356 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
357 def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
358 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
359 def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
360 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
361 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
362 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
363 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
364 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
365 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
366 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
368 def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
369 [(store RFP32:$src, addr:$op)]>;
370 def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
371 [(truncstoref32 RFP64:$src, addr:$op)]>;
372 def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
373 [(store RFP64:$src, addr:$op)]>;
374 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
375 [(truncstoref32 RFP80:$src, addr:$op)]>;
376 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
377 [(truncstoref64 RFP80:$src, addr:$op)]>;
378 // FST does not support 80-bit memory target; FSTP must be used.
380 def ST_FpP32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
381 def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
382 def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
383 def ST_FpP80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
384 def ST_FpP80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
385 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
386 [(store RFP80:$src, addr:$op)]>;
387 def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
388 def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
389 def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
390 def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
391 def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
392 def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
393 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
394 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
395 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
397 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
398 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
399 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
400 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
401 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
402 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
403 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
404 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
405 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
406 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
407 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
408 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
409 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
410 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
411 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
412 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
414 // FISTTP requires SSE3 even though it's a FPStack op.
415 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
416 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
418 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
419 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
421 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
422 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
424 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
425 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
427 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
428 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
430 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
431 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
433 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
434 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
436 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
437 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
439 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
440 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
443 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
444 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
445 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
447 // FP Stack manipulation instructions.
448 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
449 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
450 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
451 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
453 // Floating point constant loads.
454 let isReMaterializable = 1 in {
455 def LD_Fp032 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
456 [(set RFP32:$dst, fpimm0)]>;
457 def LD_Fp132 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
458 [(set RFP32:$dst, fpimm1)]>;
459 def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
460 [(set RFP64:$dst, fpimm0)]>;
461 def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
462 [(set RFP64:$dst, fpimm1)]>;
463 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
464 [(set RFP80:$dst, fpimm0)]>;
465 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
466 [(set RFP80:$dst, fpimm1)]>;
469 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
470 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
473 // Floating point compares.
474 def UCOM_Fpr32 : FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
475 []>; // FPSW = cmp ST(0) with ST(i)
476 def UCOM_FpIr32: FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
477 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
478 def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
479 []>; // FPSW = cmp ST(0) with ST(i)
480 def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
481 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
482 def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
483 []>; // FPSW = cmp ST(0) with ST(i)
484 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
485 [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
487 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
488 (outs), (ins RST:$reg),
489 "fucom\t$reg">, DD, Imp<[ST0],[]>;
490 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
491 (outs), (ins RST:$reg),
492 "fucomp\t$reg">, DD, Imp<[ST0],[]>;
493 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
495 "fucompp">, DA, Imp<[ST0],[]>;
497 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
498 (outs), (ins RST:$reg),
499 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
500 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
501 (outs), (ins RST:$reg),
502 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
504 // Floating point flag ops.
505 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
506 (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
508 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
509 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
510 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
511 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
513 //===----------------------------------------------------------------------===//
514 // Non-Instruction Patterns
515 //===----------------------------------------------------------------------===//
517 // Required for RET of f32 / f64 / f80 values.
518 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
519 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
520 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
522 // Required for CALL which return f32 / f64 / f80 values.
523 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
524 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
525 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
526 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
527 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
528 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
530 // Floating point constant -0.0 and -1.0
531 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
532 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
533 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
534 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
535 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
536 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
538 // Used to conv. i64 to f64 since there isn't a SSE version.
539 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
541 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;
542 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStack]>;
543 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStack]>;