1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
46 def MRM_D4 : Format<47>;
47 def MRM_D5 : Format<48>;
48 def MRM_D8 : Format<49>;
49 def MRM_D9 : Format<50>;
50 def MRM_DA : Format<51>;
51 def MRM_DB : Format<52>;
52 def MRM_DC : Format<53>;
53 def MRM_DD : Format<54>;
54 def MRM_DE : Format<55>;
55 def MRM_DF : Format<56>;
57 // ImmType - This specifies the immediate type used by an instruction. This is
58 // part of the ad-hoc solution used to emit machine instruction encodings by our
59 // machine code emitter.
60 class ImmType<bits<3> val> {
63 def NoImm : ImmType<0>;
64 def Imm8 : ImmType<1>;
65 def Imm8PCRel : ImmType<2>;
66 def Imm16 : ImmType<3>;
67 def Imm16PCRel : ImmType<4>;
68 def Imm32 : ImmType<5>;
69 def Imm32PCRel : ImmType<6>;
70 def Imm64 : ImmType<7>;
72 // FPFormat - This specifies what form this FP instruction has. This is used by
73 // the Floating-Point stackifier pass.
74 class FPFormat<bits<3> val> {
77 def NotFP : FPFormat<0>;
78 def ZeroArgFP : FPFormat<1>;
79 def OneArgFP : FPFormat<2>;
80 def OneArgFPRW : FPFormat<3>;
81 def TwoArgFP : FPFormat<4>;
82 def CompareFP : FPFormat<5>;
83 def CondMovFP : FPFormat<6>;
84 def SpecialFP : FPFormat<7>;
86 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
87 // Keep in sync with tables in X86InstrInfo.cpp.
88 class Domain<bits<2> val> {
91 def GenericDomain : Domain<0>;
92 def SSEPackedSingle : Domain<1>;
93 def SSEPackedDouble : Domain<2>;
94 def SSEPackedInt : Domain<3>;
96 // Prefix byte classes which are used to indicate to the ad-hoc machine code
97 // emitter that various prefix bytes are required.
98 class OpSize { bit hasOpSizePrefix = 1; }
99 class AdSize { bit hasAdSizePrefix = 1; }
100 class REX_W { bit hasREX_WPrefix = 1; }
101 class LOCK { bit hasLockPrefix = 1; }
102 class SegFS { bits<2> SegOvrBits = 1; }
103 class SegGS { bits<2> SegOvrBits = 2; }
104 class TB { bits<5> Prefix = 1; }
105 class REP { bits<5> Prefix = 2; }
106 class D8 { bits<5> Prefix = 3; }
107 class D9 { bits<5> Prefix = 4; }
108 class DA { bits<5> Prefix = 5; }
109 class DB { bits<5> Prefix = 6; }
110 class DC { bits<5> Prefix = 7; }
111 class DD { bits<5> Prefix = 8; }
112 class DE { bits<5> Prefix = 9; }
113 class DF { bits<5> Prefix = 10; }
114 class XD { bits<5> Prefix = 11; }
115 class XS { bits<5> Prefix = 12; }
116 class T8 { bits<5> Prefix = 13; }
117 class TA { bits<5> Prefix = 14; }
118 class A6 { bits<5> Prefix = 15; }
119 class A7 { bits<5> Prefix = 16; }
120 class T8XD { bits<5> Prefix = 17; }
121 class T8XS { bits<5> Prefix = 18; }
122 class TAXD { bits<5> Prefix = 19; }
123 class XOP8 { bits<5> Prefix = 20; }
124 class XOP9 { bits<5> Prefix = 21; }
125 class VEX { bit hasVEXPrefix = 1; }
126 class VEX_W { bit hasVEX_WPrefix = 1; }
127 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
128 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
129 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
130 class VEX_L { bit hasVEX_L = 1; }
131 class VEX_LIG { bit ignoresVEX_L = 1; }
132 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
133 class MemOp4 { bit hasMemOp4Prefix = 1; }
134 class XOP { bit hasXOP_Prefix = 1; }
135 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
138 Domain d = GenericDomain>
140 let Namespace = "X86";
142 bits<8> Opcode = opcod;
144 bits<6> FormBits = Form.Value;
147 dag OutOperandList = outs;
148 dag InOperandList = ins;
149 string AsmString = AsmStr;
151 // If this is a pseudo instruction, mark it isCodeGenOnly.
152 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
154 let Itinerary = itin;
157 // Attributes specific to X86 instructions...
159 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
160 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
162 bits<5> Prefix = 0; // Which prefix byte does this inst have?
163 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
164 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
165 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
166 bits<2> SegOvrBits = 0; // Segment override prefix.
167 Domain ExeDomain = d;
168 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
169 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
170 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
171 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
172 // encode the third operand?
173 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
174 // to be encoded in a immediate field?
175 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
176 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
177 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
178 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
179 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
181 // TSFlags layout should be kept in sync with X86InstrInfo.h.
182 let TSFlags{5-0} = FormBits;
183 let TSFlags{6} = hasOpSizePrefix;
184 let TSFlags{7} = hasAdSizePrefix;
185 let TSFlags{12-8} = Prefix;
186 let TSFlags{13} = hasREX_WPrefix;
187 let TSFlags{16-14} = ImmT.Value;
188 let TSFlags{19-17} = FPForm.Value;
189 let TSFlags{20} = hasLockPrefix;
190 let TSFlags{22-21} = SegOvrBits;
191 let TSFlags{24-23} = ExeDomain.Value;
192 let TSFlags{32-25} = Opcode;
193 let TSFlags{33} = hasVEXPrefix;
194 let TSFlags{34} = hasVEX_WPrefix;
195 let TSFlags{35} = hasVEX_4VPrefix;
196 let TSFlags{36} = hasVEX_4VOp3Prefix;
197 let TSFlags{37} = hasVEX_i8ImmReg;
198 let TSFlags{38} = hasVEX_L;
199 let TSFlags{39} = ignoresVEX_L;
200 let TSFlags{40} = has3DNow0F0FOpcode;
201 let TSFlags{41} = hasMemOp4Prefix;
202 let TSFlags{42} = hasXOP_Prefix;
205 class PseudoI<dag oops, dag iops, list<dag> pattern>
206 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
207 let Pattern = pattern;
210 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
211 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
212 Domain d = GenericDomain>
213 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
214 let Pattern = pattern;
217 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
218 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
219 Domain d = GenericDomain>
220 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
221 let Pattern = pattern;
224 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
225 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
226 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
227 let Pattern = pattern;
230 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
231 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
232 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
233 let Pattern = pattern;
236 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
237 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
238 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
239 let Pattern = pattern;
243 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
244 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
245 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
246 let Pattern = pattern;
250 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
251 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
252 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
253 let Pattern = pattern;
257 // FPStack Instruction Templates:
258 // FPI - Floating Point Instruction template.
259 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
260 InstrItinClass itin = IIC_DEFAULT>
261 : I<o, F, outs, ins, asm, [], itin> {}
263 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
264 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
265 InstrItinClass itin = IIC_DEFAULT>
266 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
268 let Pattern = pattern;
271 // Templates for instructions that use a 16- or 32-bit segmented address as
272 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
274 // Iseg16 - 16-bit segment selector, 16-bit offset
275 // Iseg32 - 16-bit segment selector, 32-bit offset
277 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
278 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
279 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
280 let Pattern = pattern;
284 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
285 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
286 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
287 let Pattern = pattern;
293 // SI - SSE 1 & 2 scalar instructions
294 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
295 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
296 : I<o, F, outs, ins, asm, pattern, itin> {
297 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
298 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
300 // AVX instructions have a 'v' prefix in the mnemonic
301 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
304 // SIi8 - SSE 1 & 2 scalar instructions
305 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
306 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
307 : Ii8<o, F, outs, ins, asm, pattern, itin> {
308 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
309 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
311 // AVX instructions have a 'v' prefix in the mnemonic
312 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
315 // PI - SSE 1 & 2 packed instructions
316 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
317 InstrItinClass itin, Domain d>
318 : I<o, F, outs, ins, asm, pattern, itin, d> {
319 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
320 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
322 // AVX instructions have a 'v' prefix in the mnemonic
323 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
326 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
327 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
328 InstrItinClass itin, Domain d>
329 : I<o, F, outs, ins, asm, pattern, itin, d> {
330 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
333 // PIi8 - SSE 1 & 2 packed instructions with immediate
334 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
335 list<dag> pattern, InstrItinClass itin, Domain d>
336 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
337 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
338 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
340 // AVX instructions have a 'v' prefix in the mnemonic
341 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
344 // SSE1 Instruction Templates:
346 // SSI - SSE1 instructions with XS prefix.
347 // PSI - SSE1 instructions with TB prefix.
348 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
349 // VSSI - SSE1 instructions with XS prefix in AVX form.
350 // VPSI - SSE1 instructions with TB prefix in AVX form.
352 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
353 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
354 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
355 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
356 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
357 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
358 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
359 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
360 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
362 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
363 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
364 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
366 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
367 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
368 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
370 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
371 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
372 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
375 // SSE2 Instruction Templates:
377 // SDI - SSE2 instructions with XD prefix.
378 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
379 // S2SI - SSE2 instructions with XS prefix.
380 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
381 // PDI - SSE2 instructions with TB and OpSize prefixes.
382 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
383 // VSDI - SSE2 instructions with XD prefix in AVX form.
384 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
385 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
387 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
390 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
391 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
392 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
393 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
394 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
395 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
396 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
397 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
398 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
399 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
400 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
401 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
402 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
403 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
404 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
406 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
407 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
408 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
410 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
412 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
414 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
415 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
416 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
418 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
419 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
420 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
421 OpSize, Requires<[HasAVX]>;
422 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
423 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
424 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
425 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
426 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
427 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
429 // SSE3 Instruction Templates:
431 // S3I - SSE3 instructions with TB and OpSize prefixes.
432 // S3SI - SSE3 instructions with XS prefix.
433 // S3DI - SSE3 instructions with XD prefix.
435 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
436 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
437 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
439 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
440 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
441 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
443 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
444 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
445 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
449 // SSSE3 Instruction Templates:
451 // SS38I - SSSE3 instructions with T8 prefix.
452 // SS3AI - SSSE3 instructions with TA prefix.
453 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
454 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
456 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
457 // uses the MMX registers. The 64-bit versions are grouped with the MMX
458 // classes. They need to be enabled even if AVX is enabled.
460 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
461 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
462 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
463 Requires<[UseSSSE3]>;
464 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
465 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
466 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
467 Requires<[UseSSSE3]>;
468 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
469 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
470 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
471 Requires<[HasSSSE3]>;
472 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
473 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
474 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
475 Requires<[HasSSSE3]>;
477 // SSE4.1 Instruction Templates:
479 // SS48I - SSE 4.1 instructions with T8 prefix.
480 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
482 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
483 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
484 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
485 Requires<[UseSSE41]>;
486 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
487 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
488 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
489 Requires<[UseSSE41]>;
491 // SSE4.2 Instruction Templates:
493 // SS428I - SSE 4.2 instructions with T8 prefix.
494 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
495 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
496 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
497 Requires<[UseSSE42]>;
499 // SS42FI - SSE 4.2 instructions with T8XD prefix.
500 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
501 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
502 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
503 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
505 // SS42AI = SSE 4.2 instructions with TA prefix
506 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
508 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
509 Requires<[UseSSE42]>;
511 // AVX Instruction Templates:
512 // Instructions introduced in AVX (no SSE equivalent forms)
514 // AVX8I - AVX instructions with T8 and OpSize prefix.
515 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
516 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
517 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
518 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
520 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
521 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
522 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
525 // AVX2 Instruction Templates:
526 // Instructions introduced in AVX2 (no SSE equivalent forms)
528 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
529 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
530 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
531 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
532 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
534 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
535 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
536 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
539 // AES Instruction Templates:
542 // These use the same encoding as the SSE4.2 T8 and TA encodings.
543 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
544 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
545 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
548 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
549 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
550 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
553 // PCLMUL Instruction Templates
554 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
555 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
556 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
557 OpSize, Requires<[HasPCLMUL]>;
559 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
560 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
561 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
562 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
564 // FMA3 Instruction Templates
565 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
566 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
567 : I<o, F, outs, ins, asm, pattern, itin>, T8,
568 OpSize, VEX_4V, Requires<[HasFMA]>;
570 // FMA4 Instruction Templates
571 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
572 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
573 : I<o, F, outs, ins, asm, pattern, itin>, TA,
574 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
576 // XOP 2, 3 and 4 Operand Instruction Template
577 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
578 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
579 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
580 XOP, XOP9, Requires<[HasXOP]>;
582 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
583 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
584 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
585 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
586 XOP, XOP8, Requires<[HasXOP]>;
588 // XOP 5 operand instruction (VEX encoding!)
589 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
590 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
591 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
592 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
594 // X86-64 Instruction templates...
597 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
599 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
600 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
601 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
602 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
603 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
605 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
607 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
608 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
609 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
610 let Pattern = pattern;
614 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
615 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
616 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
617 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
618 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
619 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
620 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
621 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
622 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
623 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
625 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
627 // MMX Instruction templates
630 // MMXI - MMX instructions with TB prefix.
631 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
632 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
633 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
634 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
635 // MMXID - MMX instructions with XD prefix.
636 // MMXIS - MMX instructions with XS prefix.
637 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
638 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
639 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
640 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
641 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
642 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
643 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
644 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
645 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
646 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
647 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
648 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
649 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
650 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
651 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
652 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
653 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
654 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
655 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
656 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
657 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;