1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def RawFrmImm8 : Format<11>;
28 def RawFrmImm16 : Format<12>;
29 def MRMXr : Format<14>; def MRMXm : Format<15>;
30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
32 def MRM6r : Format<22>; def MRM7r : Format<23>;
33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
35 def MRM6m : Format<30>; def MRM7m : Format<31>;
36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
39 def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>;
40 def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>;
41 def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>;
42 def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>;
43 def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>;
44 def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>;
45 def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>;
46 def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>;
47 def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>;
48 def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>;
49 def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>;
50 def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>;
51 def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>;
52 def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>;
53 def MRM_FE : Format<83>; def MRM_FF : Format<84>;
55 // ImmType - This specifies the immediate type used by an instruction. This is
56 // part of the ad-hoc solution used to emit machine instruction encodings by our
57 // machine code emitter.
58 class ImmType<bits<4> val> {
61 def NoImm : ImmType<0>;
62 def Imm8 : ImmType<1>;
63 def Imm8PCRel : ImmType<2>;
64 def Imm16 : ImmType<3>;
65 def Imm16PCRel : ImmType<4>;
66 def Imm32 : ImmType<5>;
67 def Imm32PCRel : ImmType<6>;
68 def Imm32S : ImmType<7>;
69 def Imm64 : ImmType<8>;
71 // FPFormat - This specifies what form this FP instruction has. This is used by
72 // the Floating-Point stackifier pass.
73 class FPFormat<bits<3> val> {
76 def NotFP : FPFormat<0>;
77 def ZeroArgFP : FPFormat<1>;
78 def OneArgFP : FPFormat<2>;
79 def OneArgFPRW : FPFormat<3>;
80 def TwoArgFP : FPFormat<4>;
81 def CompareFP : FPFormat<5>;
82 def CondMovFP : FPFormat<6>;
83 def SpecialFP : FPFormat<7>;
85 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
86 // Keep in sync with tables in X86InstrInfo.cpp.
87 class Domain<bits<2> val> {
90 def GenericDomain : Domain<0>;
91 def SSEPackedSingle : Domain<1>;
92 def SSEPackedDouble : Domain<2>;
93 def SSEPackedInt : Domain<3>;
95 // Class specifying the vector form of the decompressed
96 // displacement of 8-bit.
97 class CD8VForm<bits<3> val> {
100 def CD8VF : CD8VForm<0>; // v := VL
101 def CD8VH : CD8VForm<1>; // v := VL/2
102 def CD8VQ : CD8VForm<2>; // v := VL/4
103 def CD8VO : CD8VForm<3>; // v := VL/8
104 def CD8VT1 : CD8VForm<4>; // v := 1
105 def CD8VT2 : CD8VForm<5>; // v := 2
106 def CD8VT4 : CD8VForm<6>; // v := 4
107 def CD8VT8 : CD8VForm<7>; // v := 8
109 // Class specifying the prefix used an opcode extension.
110 class Prefix<bits<3> val> {
113 def NoPrfx : Prefix<0>;
119 // Class specifying the opcode map.
120 class Map<bits<3> val> {
131 // Class specifying the encoding
132 class Encoding<bits<2> val> {
135 def EncNormal : Encoding<0>;
136 def EncVEX : Encoding<1>;
137 def EncXOP : Encoding<2>;
138 def EncEVEX : Encoding<3>;
140 // Operand size for encodings that change based on mode.
141 class OperandSize<bits<2> val> {
144 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
145 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
146 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
148 // Prefix byte classes which are used to indicate to the ad-hoc machine code
149 // emitter that various prefix bytes are required.
150 class OpSize16 { OperandSize OpSize = OpSize16; }
151 class OpSize32 { OperandSize OpSize = OpSize32; }
152 class AdSize { bit hasAdSizePrefix = 1; }
153 class REX_W { bit hasREX_WPrefix = 1; }
154 class LOCK { bit hasLockPrefix = 1; }
155 class REP { bit hasREPPrefix = 1; }
156 class TB { Map OpMap = TB; }
157 class T8 { Map OpMap = T8; }
158 class TA { Map OpMap = TA; }
159 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
160 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
161 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
162 class OBXS { Prefix OpPrefix = XS; }
163 class PS : TB { Prefix OpPrefix = PS; }
164 class PD : TB { Prefix OpPrefix = PD; }
165 class XD : TB { Prefix OpPrefix = XD; }
166 class XS : TB { Prefix OpPrefix = XS; }
167 class T8PS : T8 { Prefix OpPrefix = PS; }
168 class T8PD : T8 { Prefix OpPrefix = PD; }
169 class T8XD : T8 { Prefix OpPrefix = XD; }
170 class T8XS : T8 { Prefix OpPrefix = XS; }
171 class TAPS : TA { Prefix OpPrefix = PS; }
172 class TAPD : TA { Prefix OpPrefix = PD; }
173 class TAXD : TA { Prefix OpPrefix = XD; }
174 class VEX { Encoding OpEnc = EncVEX; }
175 class VEX_W { bit hasVEX_WPrefix = 1; }
176 class VEX_4V : VEX { bit hasVEX_4V = 1; }
177 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; }
178 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
179 class VEX_L { bit hasVEX_L = 1; }
180 class VEX_LIG { bit ignoresVEX_L = 1; }
181 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
182 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
183 class EVEX_K { bit hasEVEX_K = 1; }
184 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
185 class EVEX_B { bit hasEVEX_B = 1; }
186 class EVEX_RC { bit hasEVEX_RC = 1; }
187 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
188 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }
189 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }
191 // Specify AVX512 8-bit compressed displacement encoding based on the vector
192 // element size in bits (8, 16, 32, 64) and the CDisp8 form.
193 class EVEX_CD8<int esize, CD8VForm form> {
194 int CD8_EltSize = !srl(esize, 3);
195 bits<3> CD8_Form = form.Value;
198 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
199 class MemOp4 { bit hasMemOp4Prefix = 1; }
200 class XOP { Encoding OpEnc = EncXOP; }
201 class XOP_4V : XOP { bit hasVEX_4V = 1; }
202 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; }
204 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
207 Domain d = GenericDomain>
209 let Namespace = "X86";
211 bits<8> Opcode = opcod;
213 bits<7> FormBits = Form.Value;
216 dag OutOperandList = outs;
217 dag InOperandList = ins;
218 string AsmString = AsmStr;
220 // If this is a pseudo instruction, mark it isCodeGenOnly.
221 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
223 let Itinerary = itin;
226 // Attributes specific to X86 instructions...
228 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
229 // isCodeGenonly. Needed to hide an ambiguous
230 // AsmString from the parser, but still disassemble.
232 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
233 // based on operand size of the mode
234 bits<2> OpSizeBits = OpSize.Value;
235 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
237 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
238 bits<3> OpPrefixBits = OpPrefix.Value;
239 Map OpMap = OB; // Which opcode map does this inst have?
240 bits<3> OpMapBits = OpMap.Value;
241 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
242 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
243 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
244 Domain ExeDomain = d;
245 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
246 Encoding OpEnc = EncNormal; // Encoding used by this instruction
247 bits<2> OpEncBits = OpEnc.Value;
248 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
249 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
250 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to
251 // encode the third operand?
252 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
253 // to be encoded in a immediate field?
254 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
255 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
256 bit hasEVEX_K = 0; // Does this inst require masking?
257 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
258 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
259 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
260 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
261 // Declare it int rather than bits<4> so that all bits are defined when
262 // assigning to bits<7>.
263 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
264 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
265 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
266 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
269 let EVEX_LL{0} = hasVEX_L;
270 let EVEX_LL{1} = hasEVEX_L2;
271 // Vector size in bytes.
272 bits<7> VectSize = !shl(16, EVEX_LL);
274 // The scaling factor for AVX512's compressed displacement is either
275 // - the size of a power-of-two number of elements or
276 // - the size of a single element for broadcasts or
277 // - the total vector size divided by a power-of-two number.
278 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
279 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
281 !shl(CD8_EltSize, CD8_Form{1-0}),
284 !srl(VectSize, CD8_Form{1-0}))), 0);
286 // TSFlags layout should be kept in sync with X86InstrInfo.h.
287 let TSFlags{6-0} = FormBits;
288 let TSFlags{8-7} = OpSizeBits;
289 let TSFlags{9} = hasAdSizePrefix;
290 let TSFlags{12-10} = OpPrefixBits;
291 let TSFlags{15-13} = OpMapBits;
292 let TSFlags{16} = hasREX_WPrefix;
293 let TSFlags{20-17} = ImmT.Value;
294 let TSFlags{23-21} = FPForm.Value;
295 let TSFlags{24} = hasLockPrefix;
296 let TSFlags{25} = hasREPPrefix;
297 let TSFlags{27-26} = ExeDomain.Value;
298 let TSFlags{29-28} = OpEncBits;
299 let TSFlags{37-30} = Opcode;
300 let TSFlags{38} = hasVEX_WPrefix;
301 let TSFlags{39} = hasVEX_4V;
302 let TSFlags{40} = hasVEX_4VOp3;
303 let TSFlags{41} = hasVEX_i8ImmReg;
304 let TSFlags{42} = hasVEX_L;
305 let TSFlags{43} = ignoresVEX_L;
306 let TSFlags{44} = hasEVEX_K;
307 let TSFlags{45} = hasEVEX_Z;
308 let TSFlags{46} = hasEVEX_L2;
309 let TSFlags{47} = hasEVEX_B;
310 // If we run out of TSFlags bits, it's possible to encode this in 3 bits.
311 let TSFlags{54-48} = CD8_Scale;
312 let TSFlags{55} = has3DNow0F0FOpcode;
313 let TSFlags{56} = hasMemOp4Prefix;
314 let TSFlags{57} = hasEVEX_RC;
317 class PseudoI<dag oops, dag iops, list<dag> pattern>
318 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
319 let Pattern = pattern;
322 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
323 list<dag> pattern, InstrItinClass itin = NoItinerary,
324 Domain d = GenericDomain>
325 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
326 let Pattern = pattern;
329 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
330 list<dag> pattern, InstrItinClass itin = NoItinerary,
331 Domain d = GenericDomain>
332 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
333 let Pattern = pattern;
336 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
337 list<dag> pattern, InstrItinClass itin = NoItinerary>
338 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
339 let Pattern = pattern;
342 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
343 list<dag> pattern, InstrItinClass itin = NoItinerary>
344 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
345 let Pattern = pattern;
348 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
349 list<dag> pattern, InstrItinClass itin = NoItinerary>
350 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
351 let Pattern = pattern;
354 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
355 list<dag> pattern, InstrItinClass itin = NoItinerary>
356 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
357 let Pattern = pattern;
361 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
362 list<dag> pattern, InstrItinClass itin = NoItinerary>
363 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
364 let Pattern = pattern;
368 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
369 list<dag> pattern, InstrItinClass itin = NoItinerary>
370 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
371 let Pattern = pattern;
375 // FPStack Instruction Templates:
376 // FPI - Floating Point Instruction template.
377 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
378 InstrItinClass itin = NoItinerary>
379 : I<o, F, outs, ins, asm, [], itin> {}
381 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
382 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
383 InstrItinClass itin = NoItinerary>
384 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
386 let Pattern = pattern;
389 // Templates for instructions that use a 16- or 32-bit segmented address as
390 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
392 // Iseg16 - 16-bit segment selector, 16-bit offset
393 // Iseg32 - 16-bit segment selector, 32-bit offset
395 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
396 list<dag> pattern, InstrItinClass itin = NoItinerary>
397 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
398 let Pattern = pattern;
402 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
403 list<dag> pattern, InstrItinClass itin = NoItinerary>
404 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
405 let Pattern = pattern;
409 // SI - SSE 1 & 2 scalar instructions
410 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 list<dag> pattern, InstrItinClass itin = NoItinerary>
412 : I<o, F, outs, ins, asm, pattern, itin> {
413 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
414 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
415 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
416 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
417 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
420 // AVX instructions have a 'v' prefix in the mnemonic
421 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
422 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
426 // SIi8 - SSE 1 & 2 scalar instructions
427 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
428 list<dag> pattern, InstrItinClass itin = NoItinerary>
429 : Ii8<o, F, outs, ins, asm, pattern, itin> {
430 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
431 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
432 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
435 // AVX instructions have a 'v' prefix in the mnemonic
436 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
437 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
441 // PI - SSE 1 & 2 packed instructions
442 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
443 InstrItinClass itin, Domain d>
444 : I<o, F, outs, ins, asm, pattern, itin, d> {
445 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
446 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
447 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
450 // AVX instructions have a 'v' prefix in the mnemonic
451 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
452 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
456 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
457 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
458 InstrItinClass itin, Domain d>
459 : I<o, F, outs, ins, asm, pattern, itin, d> {
460 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
464 // PIi8 - SSE 1 & 2 packed instructions with immediate
465 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin, Domain d>
467 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
468 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
469 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
470 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
473 // AVX instructions have a 'v' prefix in the mnemonic
474 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
475 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
479 // SSE1 Instruction Templates:
481 // SSI - SSE1 instructions with XS prefix.
482 // PSI - SSE1 instructions with PS prefix.
483 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
484 // VSSI - SSE1 instructions with XS prefix in AVX form.
485 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
487 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
488 list<dag> pattern, InstrItinClass itin = NoItinerary>
489 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
490 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
491 list<dag> pattern, InstrItinClass itin = NoItinerary>
492 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
493 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
494 list<dag> pattern, InstrItinClass itin = NoItinerary>
495 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
497 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
498 list<dag> pattern, InstrItinClass itin = NoItinerary>
499 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
501 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
502 list<dag> pattern, InstrItinClass itin = NoItinerary>
503 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
505 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
506 list<dag> pattern, InstrItinClass itin = NoItinerary>
507 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
510 // SSE2 Instruction Templates:
512 // SDI - SSE2 instructions with XD prefix.
513 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
514 // S2SI - SSE2 instructions with XS prefix.
515 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
516 // PDI - SSE2 instructions with PD prefix, packed double domain.
517 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
518 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
519 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
520 // packed double domain.
521 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
522 // S2I - SSE2 scalar instructions with PD prefix.
523 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
525 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
528 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
529 list<dag> pattern, InstrItinClass itin = NoItinerary>
530 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
531 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
534 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
535 list<dag> pattern, InstrItinClass itin = NoItinerary>
536 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
537 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
538 list<dag> pattern, InstrItinClass itin = NoItinerary>
539 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
540 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
541 list<dag> pattern, InstrItinClass itin = NoItinerary>
542 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
544 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
545 list<dag> pattern, InstrItinClass itin = NoItinerary>
546 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
548 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
549 list<dag> pattern, InstrItinClass itin = NoItinerary>
550 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
552 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
553 list<dag> pattern, InstrItinClass itin = NoItinerary>
554 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
556 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
557 list<dag> pattern, InstrItinClass itin = NoItinerary>
558 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
559 PD, Requires<[HasAVX]>;
560 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
561 list<dag> pattern, InstrItinClass itin = NoItinerary>
562 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
564 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
565 list<dag> pattern, InstrItinClass itin = NoItinerary>
566 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
567 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
568 list<dag> pattern, InstrItinClass itin = NoItinerary>
569 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
570 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
571 list<dag> pattern, InstrItinClass itin = NoItinerary>
572 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
574 // SSE3 Instruction Templates:
576 // S3I - SSE3 instructions with PD prefixes.
577 // S3SI - SSE3 instructions with XS prefix.
578 // S3DI - SSE3 instructions with XD prefix.
580 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
581 list<dag> pattern, InstrItinClass itin = NoItinerary>
582 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
584 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
585 list<dag> pattern, InstrItinClass itin = NoItinerary>
586 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
588 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
589 list<dag> pattern, InstrItinClass itin = NoItinerary>
590 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
594 // SSSE3 Instruction Templates:
596 // SS38I - SSSE3 instructions with T8 prefix.
597 // SS3AI - SSSE3 instructions with TA prefix.
598 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
599 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
601 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
602 // uses the MMX registers. The 64-bit versions are grouped with the MMX
603 // classes. They need to be enabled even if AVX is enabled.
605 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = NoItinerary>
607 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
608 Requires<[UseSSSE3]>;
609 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
610 list<dag> pattern, InstrItinClass itin = NoItinerary>
611 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
612 Requires<[UseSSSE3]>;
613 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
614 list<dag> pattern, InstrItinClass itin = NoItinerary>
615 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
616 Requires<[HasSSSE3]>;
617 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
618 list<dag> pattern, InstrItinClass itin = NoItinerary>
619 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
620 Requires<[HasSSSE3]>;
622 // SSE4.1 Instruction Templates:
624 // SS48I - SSE 4.1 instructions with T8 prefix.
625 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
627 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
628 list<dag> pattern, InstrItinClass itin = NoItinerary>
629 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
630 Requires<[UseSSE41]>;
631 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
632 list<dag> pattern, InstrItinClass itin = NoItinerary>
633 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
634 Requires<[UseSSE41]>;
636 // SSE4.2 Instruction Templates:
638 // SS428I - SSE 4.2 instructions with T8 prefix.
639 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
640 list<dag> pattern, InstrItinClass itin = NoItinerary>
641 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
642 Requires<[UseSSE42]>;
644 // SS42FI - SSE 4.2 instructions with T8XD prefix.
645 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
646 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
647 list<dag> pattern, InstrItinClass itin = NoItinerary>
648 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
650 // SS42AI = SSE 4.2 instructions with TA prefix
651 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
652 list<dag> pattern, InstrItinClass itin = NoItinerary>
653 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
654 Requires<[UseSSE42]>;
656 // AVX Instruction Templates:
657 // Instructions introduced in AVX (no SSE equivalent forms)
659 // AVX8I - AVX instructions with T8PD prefix.
660 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
661 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
662 list<dag> pattern, InstrItinClass itin = NoItinerary>
663 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
665 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
666 list<dag> pattern, InstrItinClass itin = NoItinerary>
667 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
670 // AVX2 Instruction Templates:
671 // Instructions introduced in AVX2 (no SSE equivalent forms)
673 // AVX28I - AVX2 instructions with T8PD prefix.
674 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
675 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
676 list<dag> pattern, InstrItinClass itin = NoItinerary>
677 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
679 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
680 list<dag> pattern, InstrItinClass itin = NoItinerary>
681 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
685 // AVX-512 Instruction Templates:
686 // Instructions introduced in AVX-512 (no SSE equivalent forms)
688 // AVX5128I - AVX-512 instructions with T8PD prefix.
689 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
690 // AVX512PDI - AVX-512 instructions with PD, double packed.
691 // AVX512PSI - AVX-512 instructions with PS, single packed.
692 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
693 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
694 // AVX512BI - AVX-512 instructions with PD, int packed domain.
695 // AVX512SI - AVX-512 scalar instructions with PD prefix.
697 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
698 list<dag> pattern, InstrItinClass itin = NoItinerary>
699 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
700 Requires<[HasAVX512]>;
701 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
702 list<dag> pattern, InstrItinClass itin = NoItinerary>
703 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
704 Requires<[HasAVX512]>;
705 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
706 list<dag> pattern, InstrItinClass itin = NoItinerary>
707 : I<o, F, outs, ins, asm, pattern, itin>, XS,
708 Requires<[HasAVX512]>;
709 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
710 list<dag> pattern, InstrItinClass itin = NoItinerary>
711 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
712 Requires<[HasAVX512]>;
713 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
714 list<dag> pattern, InstrItinClass itin = NoItinerary>
715 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
716 Requires<[HasAVX512]>;
717 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
718 list<dag> pattern, InstrItinClass itin = NoItinerary>
719 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
720 Requires<[HasAVX512]>;
721 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
722 list<dag> pattern, InstrItinClass itin = NoItinerary>
723 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
724 Requires<[HasAVX512]>;
725 class AVX512AIi8Base: TAPD {
726 Domain ExeDomain = SSEPackedInt;
729 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
730 list<dag> pattern, InstrItinClass itin = NoItinerary>
731 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
732 Requires<[HasAVX512]>;
733 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
734 list<dag> pattern, InstrItinClass itin = NoItinerary>
735 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
736 Requires<[HasAVX512]>;
737 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
738 list<dag> pattern, InstrItinClass itin = NoItinerary>
739 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
740 Requires<[HasAVX512]>;
741 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
742 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
743 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
744 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
745 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
746 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
747 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
748 list<dag>pattern, InstrItinClass itin = NoItinerary>
749 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
750 EVEX_4V, Requires<[HasAVX512]>;
752 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
753 list<dag>pattern, InstrItinClass itin = NoItinerary>
754 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>;
756 // AES Instruction Templates:
759 // These use the same encoding as the SSE4.2 T8 and TA encodings.
760 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
761 list<dag>pattern, InstrItinClass itin = IIC_AES>
762 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
765 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
766 list<dag> pattern, InstrItinClass itin = NoItinerary>
767 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
770 // PCLMUL Instruction Templates
771 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
772 list<dag>pattern, InstrItinClass itin = NoItinerary>
773 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
774 Requires<[HasPCLMUL]>;
776 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
777 list<dag>pattern, InstrItinClass itin = NoItinerary>
778 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
779 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
781 // FMA3 Instruction Templates
782 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
783 list<dag>pattern, InstrItinClass itin = NoItinerary>
784 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
785 VEX_4V, FMASC, Requires<[HasFMA]>;
787 // FMA4 Instruction Templates
788 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
789 list<dag>pattern, InstrItinClass itin = NoItinerary>
790 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
791 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
793 // XOP 2, 3 and 4 Operand Instruction Template
794 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
795 list<dag> pattern, InstrItinClass itin = NoItinerary>
796 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
797 XOP9, Requires<[HasXOP]>;
799 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
800 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
801 list<dag> pattern, InstrItinClass itin = NoItinerary>
802 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
803 XOP8, Requires<[HasXOP]>;
805 // XOP 5 operand instruction (VEX encoding!)
806 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
807 list<dag>pattern, InstrItinClass itin = NoItinerary>
808 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
809 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
811 // X86-64 Instruction templates...
814 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
815 list<dag> pattern, InstrItinClass itin = NoItinerary>
816 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
817 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
818 list<dag> pattern, InstrItinClass itin = NoItinerary>
819 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
820 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
821 list<dag> pattern, InstrItinClass itin = NoItinerary>
822 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
823 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
824 list<dag> pattern, InstrItinClass itin = NoItinerary>
825 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
826 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
827 list<dag> pattern, InstrItinClass itin = NoItinerary>
828 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
830 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
831 list<dag> pattern, InstrItinClass itin = NoItinerary>
832 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
833 let Pattern = pattern;
837 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
838 list<dag> pattern, InstrItinClass itin = NoItinerary>
839 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
840 let Pattern = pattern;
844 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
845 list<dag> pattern, InstrItinClass itin = NoItinerary>
846 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
847 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
848 list<dag> pattern, InstrItinClass itin = NoItinerary>
849 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
851 // MMX Instruction templates
854 // MMXI - MMX instructions with TB prefix.
855 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
856 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
857 // MMX2I - MMX / SSE2 instructions with PD prefix.
858 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
859 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
860 // MMXID - MMX instructions with XD prefix.
861 // MMXIS - MMX instructions with XS prefix.
862 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
863 list<dag> pattern, InstrItinClass itin = NoItinerary>
864 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
865 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
866 list<dag> pattern, InstrItinClass itin = NoItinerary>
867 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
868 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
869 list<dag> pattern, InstrItinClass itin = NoItinerary>
870 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
871 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
872 list<dag> pattern, InstrItinClass itin = NoItinerary>
873 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
874 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
875 list<dag> pattern, InstrItinClass itin = NoItinerary>
876 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
877 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
878 list<dag> pattern, InstrItinClass itin = NoItinerary>
879 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
880 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
881 list<dag> pattern, InstrItinClass itin = NoItinerary>
882 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
883 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
884 list<dag> pattern, InstrItinClass itin = NoItinerary>
885 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;