1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<3> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
44 def Imm64 : ImmType<4>;
46 // FPFormat - This specifies what form this FP instruction has. This is used by
47 // the Floating-Point stackifier pass.
48 class FPFormat<bits<3> val> {
51 def NotFP : FPFormat<0>;
52 def ZeroArgFP : FPFormat<1>;
53 def OneArgFP : FPFormat<2>;
54 def OneArgFPRW : FPFormat<3>;
55 def TwoArgFP : FPFormat<4>;
56 def CompareFP : FPFormat<5>;
57 def CondMovFP : FPFormat<6>;
58 def SpecialFP : FPFormat<7>;
60 // Prefix byte classes which are used to indicate to the ad-hoc machine code
61 // emitter that various prefix bytes are required.
62 class OpSize { bit hasOpSizePrefix = 1; }
63 class AdSize { bit hasAdSizePrefix = 1; }
64 class REX_W { bit hasREX_WPrefix = 1; }
65 class LOCK { bit hasLockPrefix = 1; }
66 class TB { bits<4> Prefix = 1; }
67 class REP { bits<4> Prefix = 2; }
68 class D8 { bits<4> Prefix = 3; }
69 class D9 { bits<4> Prefix = 4; }
70 class DA { bits<4> Prefix = 5; }
71 class DB { bits<4> Prefix = 6; }
72 class DC { bits<4> Prefix = 7; }
73 class DD { bits<4> Prefix = 8; }
74 class DE { bits<4> Prefix = 9; }
75 class DF { bits<4> Prefix = 10; }
76 class XD { bits<4> Prefix = 11; }
77 class XS { bits<4> Prefix = 12; }
78 class T8 { bits<4> Prefix = 13; }
79 class TA { bits<4> Prefix = 14; }
81 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
84 let Namespace = "X86";
86 bits<8> Opcode = opcod;
88 bits<6> FormBits = Form.Value;
90 bits<3> ImmTypeBits = ImmT.Value;
92 dag OutOperandList = outs;
93 dag InOperandList = ins;
94 string AsmString = AsmStr;
97 // Attributes specific to X86 instructions...
99 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
100 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
102 bits<4> Prefix = 0; // Which prefix byte does this inst have?
103 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
104 FPFormat FPForm; // What flavor of FP instruction is this?
105 bits<3> FPFormBits = 0;
106 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
109 class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
110 : X86Inst<o, f, NoImm, outs, ins, asm> {
111 let Pattern = pattern;
114 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
115 : X86Inst<o, f, Imm8 , outs, ins, asm> {
116 let Pattern = pattern;
119 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
120 : X86Inst<o, f, Imm16, outs, ins, asm> {
121 let Pattern = pattern;
124 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
125 : X86Inst<o, f, Imm32, outs, ins, asm> {
126 let Pattern = pattern;
130 // FPStack Instruction Templates:
131 // FPI - Floating Point Instruction template.
132 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
133 : I<o, F, outs, ins, asm, []> {}
135 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
136 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
137 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
138 let FPForm = fp; let FPFormBits = FPForm.Value;
139 let Pattern = pattern;
142 // SSE1 Instruction Templates:
144 // SSI - SSE1 instructions with XS prefix.
145 // PSI - SSE1 instructions with TB prefix.
146 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
148 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
149 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
150 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
151 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
152 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
153 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
154 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
156 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
158 // SSE2 Instruction Templates:
160 // SDI - SSE2 instructions with XD prefix.
161 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
162 // PDI - SSE2 instructions with TB and OpSize prefixes.
163 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
165 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
166 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
167 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
169 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
170 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
171 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
172 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
174 : Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
176 // SSE3 Instruction Templates:
178 // S3I - SSE3 instructions with TB and OpSize prefixes.
179 // S3SI - SSE3 instructions with XS prefix.
180 // S3DI - SSE3 instructions with XD prefix.
182 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
183 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
184 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
185 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
186 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
187 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
190 // SSSE3 Instruction Templates:
192 // SS38I - SSSE3 instructions with T8 prefix.
193 // SS3AI - SSSE3 instructions with TA prefix.
195 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
196 // uses the MMX registers. We put those instructions here because they better
197 // fit into the SSSE3 instruction category rather than the MMX category.
199 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
201 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
202 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
204 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
206 // SSE4.1 Instruction Templates:
208 // SS48I - SSE 4.1 instructions with T8 prefix.
209 // SS41AI - SSE 4.1 instructions with TA prefix.
211 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
213 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
214 class SS4AI<bits<8> o, Format F, dag outs, dag ins, string asm,
216 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
219 // X86-64 Instruction templates...
222 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
223 : I<o, F, outs, ins, asm, pattern>, REX_W;
224 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
226 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
227 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
229 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
231 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
233 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
234 let Pattern = pattern;
238 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
240 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
241 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
243 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
244 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
246 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
248 // MMX Instruction templates
251 // MMXI - MMX instructions with TB prefix.
252 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
253 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
254 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
255 // MMXID - MMX instructions with XD prefix.
256 // MMXIS - MMX instructions with XS prefix.
257 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
258 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
259 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
260 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
261 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
262 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
263 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
264 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
265 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
266 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
267 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
268 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;