1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm16 : Format<43>;
44 // ImmType - This specifies the immediate type used by an instruction. This is
45 // part of the ad-hoc solution used to emit machine instruction encodings by our
46 // machine code emitter.
47 class ImmType<bits<3> val> {
50 def NoImm : ImmType<0>;
51 def Imm8 : ImmType<1>;
52 def Imm8PCRel : ImmType<2>;
53 def Imm16 : ImmType<3>;
54 def Imm16PCRel : ImmType<4>;
55 def Imm32 : ImmType<5>;
56 def Imm32PCRel : ImmType<6>;
57 def Imm64 : ImmType<7>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def CompareFP : FPFormat<5>;
70 def CondMovFP : FPFormat<6>;
71 def SpecialFP : FPFormat<7>;
73 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
74 // Keep in sync with tables in X86InstrInfo.cpp.
75 class Domain<bits<2> val> {
78 def GenericDomain : Domain<0>;
79 def SSEPackedSingle : Domain<1>;
80 def SSEPackedDouble : Domain<2>;
81 def SSEPackedInt : Domain<3>;
83 // Prefix byte classes which are used to indicate to the ad-hoc machine code
84 // emitter that various prefix bytes are required.
85 class OpSize { bit hasOpSizePrefix = 1; }
86 class AdSize { bit hasAdSizePrefix = 1; }
87 class REX_W { bit hasREX_WPrefix = 1; }
88 class LOCK { bit hasLockPrefix = 1; }
89 class SegFS { bits<2> SegOvrBits = 1; }
90 class SegGS { bits<2> SegOvrBits = 2; }
91 class TB { bits<4> Prefix = 1; }
92 class REP { bits<4> Prefix = 2; }
93 class D8 { bits<4> Prefix = 3; }
94 class D9 { bits<4> Prefix = 4; }
95 class DA { bits<4> Prefix = 5; }
96 class DB { bits<4> Prefix = 6; }
97 class DC { bits<4> Prefix = 7; }
98 class DD { bits<4> Prefix = 8; }
99 class DE { bits<4> Prefix = 9; }
100 class DF { bits<4> Prefix = 10; }
101 class XD { bits<4> Prefix = 11; }
102 class XS { bits<4> Prefix = 12; }
103 class T8 { bits<4> Prefix = 13; }
104 class TA { bits<4> Prefix = 14; }
105 class TF { bits<4> Prefix = 15; }
106 class VEX { bit hasVEXPrefix = 1; }
107 class VEX_W { bit hasVEX_WPrefix = 1; }
108 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
109 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
110 class VEX_L { bit hasVEX_L = 1; }
112 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
113 string AsmStr, Domain d = GenericDomain>
115 let Namespace = "X86";
117 bits<8> Opcode = opcod;
119 bits<6> FormBits = Form.Value;
122 dag OutOperandList = outs;
123 dag InOperandList = ins;
124 string AsmString = AsmStr;
127 // Attributes specific to X86 instructions...
129 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
130 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
132 bits<4> Prefix = 0; // Which prefix byte does this inst have?
133 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
134 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
135 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
136 bits<2> SegOvrBits = 0; // Segment override prefix.
137 Domain ExeDomain = d;
138 bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix?
139 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
140 bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field?
141 bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register
142 // to be encoded in a immediate field?
143 bit hasVEX_L = 0; // Does this inst uses large (256-bit) registers?
145 // TSFlags layout should be kept in sync with X86InstrInfo.h.
146 let TSFlags{5-0} = FormBits;
147 let TSFlags{6} = hasOpSizePrefix;
148 let TSFlags{7} = hasAdSizePrefix;
149 let TSFlags{11-8} = Prefix;
150 let TSFlags{12} = hasREX_WPrefix;
151 let TSFlags{15-13} = ImmT.Value;
152 let TSFlags{18-16} = FPForm.Value;
153 let TSFlags{19} = hasLockPrefix;
154 let TSFlags{21-20} = SegOvrBits;
155 let TSFlags{23-22} = ExeDomain.Value;
156 let TSFlags{31-24} = Opcode;
157 let TSFlags{32} = hasVEXPrefix;
158 let TSFlags{33} = hasVEX_WPrefix;
159 let TSFlags{34} = hasVEX_4VPrefix;
160 let TSFlags{35} = hasVEX_i8ImmReg;
161 let TSFlags{36} = hasVEX_L;
164 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
165 list<dag> pattern, Domain d = GenericDomain>
166 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
167 let Pattern = pattern;
170 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
171 list<dag> pattern, Domain d = GenericDomain>
172 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
173 let Pattern = pattern;
176 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
178 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
179 let Pattern = pattern;
182 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
184 : X86Inst<o, f, Imm16, outs, ins, asm> {
185 let Pattern = pattern;
188 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
190 : X86Inst<o, f, Imm32, outs, ins, asm> {
191 let Pattern = pattern;
195 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
197 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
198 let Pattern = pattern;
202 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
204 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
205 let Pattern = pattern;
209 // FPStack Instruction Templates:
210 // FPI - Floating Point Instruction template.
211 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
212 : I<o, F, outs, ins, asm, []> {}
214 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
215 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
216 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
218 let Pattern = pattern;
221 // Templates for instructions that use a 16- or 32-bit segmented address as
222 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
224 // Iseg16 - 16-bit segment selector, 16-bit offset
225 // Iseg32 - 16-bit segment selector, 32-bit offset
227 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
228 list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
229 let Pattern = pattern;
233 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
234 list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
235 let Pattern = pattern;
239 // SI - SSE 1 & 2 scalar instructions
240 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
241 : I<o, F, outs, ins, asm, pattern> {
242 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
243 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
245 // AVX instructions have a 'v' prefix in the mnemonic
246 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
249 // SIi8 - SSE 1 & 2 scalar instructions
250 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
252 : Ii8<o, F, outs, ins, asm, pattern> {
253 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
254 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
256 // AVX instructions have a 'v' prefix in the mnemonic
257 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
260 // PI - SSE 1 & 2 packed instructions
261 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
263 : I<o, F, outs, ins, asm, pattern, d> {
264 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
265 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
267 // AVX instructions have a 'v' prefix in the mnemonic
268 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
271 // PIi8 - SSE 1 & 2 packed instructions with immediate
272 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
273 list<dag> pattern, Domain d>
274 : Ii8<o, F, outs, ins, asm, pattern, d> {
275 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
276 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
278 // AVX instructions have a 'v' prefix in the mnemonic
279 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
282 // SSE1 Instruction Templates:
284 // SSI - SSE1 instructions with XS prefix.
285 // PSI - SSE1 instructions with TB prefix.
286 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
287 // VSSI - SSE1 instructions with XS prefix in AVX form.
288 // VPSI - SSE1 instructions with TB prefix in AVX form.
290 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
291 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
292 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
294 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
295 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
296 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
298 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
300 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
302 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
304 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
306 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
308 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
311 // SSE2 Instruction Templates:
313 // SDI - SSE2 instructions with XD prefix.
314 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
315 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
316 // PDI - SSE2 instructions with TB and OpSize prefixes.
317 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
318 // VSDI - SSE2 instructions with XD prefix in AVX form.
319 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
321 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
322 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
323 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
325 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
326 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
328 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
329 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
330 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
332 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
334 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
336 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
338 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
340 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
342 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
343 OpSize, Requires<[HasAVX]>;
345 // SSE3 Instruction Templates:
347 // S3I - SSE3 instructions with TB and OpSize prefixes.
348 // S3SI - SSE3 instructions with XS prefix.
349 // S3DI - SSE3 instructions with XD prefix.
351 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
353 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
355 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
357 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
359 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
360 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
364 // SSSE3 Instruction Templates:
366 // SS38I - SSSE3 instructions with T8 prefix.
367 // SS3AI - SSSE3 instructions with TA prefix.
369 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
370 // uses the MMX registers. We put those instructions here because they better
371 // fit into the SSSE3 instruction category rather than the MMX category.
373 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
375 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
376 Requires<[HasSSSE3]>;
377 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
379 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
380 Requires<[HasSSSE3]>;
382 // SSE4.1 Instruction Templates:
384 // SS48I - SSE 4.1 instructions with T8 prefix.
385 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
387 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
389 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
390 Requires<[HasSSE41]>;
391 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
393 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
394 Requires<[HasSSE41]>;
396 // SSE4.2 Instruction Templates:
398 // SS428I - SSE 4.2 instructions with T8 prefix.
399 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
401 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
402 Requires<[HasSSE42]>;
404 // SS42FI - SSE 4.2 instructions with TF prefix.
405 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
407 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
409 // SS42AI = SSE 4.2 instructions with TA prefix
410 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
412 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
413 Requires<[HasSSE42]>;
415 // AVX Instruction Templates:
416 // Instructions introduced in AVX (no SSE equivalent forms)
418 // AVX8I - AVX instructions with T8 and OpSize prefix.
419 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
420 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
422 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
424 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
426 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
429 // AES Instruction Templates:
432 // These use the same encoding as the SSE4.2 T8 and TA encodings.
433 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
435 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
438 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
440 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
443 // CLMUL Instruction Templates
444 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
446 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
447 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
449 // FMA3 Instruction Templates
450 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
452 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
453 OpSize, VEX_4V, Requires<[HasFMA3]>;
455 // X86-64 Instruction templates...
458 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
459 : I<o, F, outs, ins, asm, pattern>, REX_W;
460 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
462 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
463 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
465 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
467 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
469 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
470 let Pattern = pattern;
474 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
476 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
477 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
479 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
480 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
482 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
484 // MMX Instruction templates
487 // MMXI - MMX instructions with TB prefix.
488 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
489 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
490 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
491 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
492 // MMXID - MMX instructions with XD prefix.
493 // MMXIS - MMX instructions with XS prefix.
494 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
496 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
497 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
499 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
500 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
502 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
503 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
505 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
506 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
508 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
509 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
511 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
512 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
514 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;