1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_CA : Format<39>;
39 def MRM_CB : Format<40>;
40 def MRM_E8 : Format<41>;
41 def MRM_F0 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_F8 : Format<45>;
45 def MRM_F9 : Format<46>;
46 def MRM_D0 : Format<47>;
47 def MRM_D1 : Format<48>;
48 def MRM_D4 : Format<49>;
49 def MRM_D5 : Format<50>;
50 def MRM_D6 : Format<51>;
51 def MRM_D8 : Format<52>;
52 def MRM_D9 : Format<53>;
53 def MRM_DA : Format<54>;
54 def MRM_DB : Format<55>;
55 def MRM_DC : Format<56>;
56 def MRM_DD : Format<57>;
57 def MRM_DE : Format<58>;
58 def MRM_DF : Format<59>;
60 // ImmType - This specifies the immediate type used by an instruction. This is
61 // part of the ad-hoc solution used to emit machine instruction encodings by our
62 // machine code emitter.
63 class ImmType<bits<3> val> {
66 def NoImm : ImmType<0>;
67 def Imm8 : ImmType<1>;
68 def Imm8PCRel : ImmType<2>;
69 def Imm16 : ImmType<3>;
70 def Imm16PCRel : ImmType<4>;
71 def Imm32 : ImmType<5>;
72 def Imm32PCRel : ImmType<6>;
73 def Imm64 : ImmType<7>;
75 // FPFormat - This specifies what form this FP instruction has. This is used by
76 // the Floating-Point stackifier pass.
77 class FPFormat<bits<3> val> {
80 def NotFP : FPFormat<0>;
81 def ZeroArgFP : FPFormat<1>;
82 def OneArgFP : FPFormat<2>;
83 def OneArgFPRW : FPFormat<3>;
84 def TwoArgFP : FPFormat<4>;
85 def CompareFP : FPFormat<5>;
86 def CondMovFP : FPFormat<6>;
87 def SpecialFP : FPFormat<7>;
89 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
90 // Keep in sync with tables in X86InstrInfo.cpp.
91 class Domain<bits<2> val> {
94 def GenericDomain : Domain<0>;
95 def SSEPackedSingle : Domain<1>;
96 def SSEPackedDouble : Domain<2>;
97 def SSEPackedInt : Domain<3>;
99 // Prefix byte classes which are used to indicate to the ad-hoc machine code
100 // emitter that various prefix bytes are required.
101 class OpSize { bit hasOpSizePrefix = 1; }
102 class AdSize { bit hasAdSizePrefix = 1; }
103 class REX_W { bit hasREX_WPrefix = 1; }
104 class LOCK { bit hasLockPrefix = 1; }
105 class SegFS { bits<2> SegOvrBits = 1; }
106 class SegGS { bits<2> SegOvrBits = 2; }
107 class TB { bits<5> Prefix = 1; }
108 class REP { bits<5> Prefix = 2; }
109 class D8 { bits<5> Prefix = 3; }
110 class D9 { bits<5> Prefix = 4; }
111 class DA { bits<5> Prefix = 5; }
112 class DB { bits<5> Prefix = 6; }
113 class DC { bits<5> Prefix = 7; }
114 class DD { bits<5> Prefix = 8; }
115 class DE { bits<5> Prefix = 9; }
116 class DF { bits<5> Prefix = 10; }
117 class XD { bits<5> Prefix = 11; }
118 class XS { bits<5> Prefix = 12; }
119 class T8 { bits<5> Prefix = 13; }
120 class TA { bits<5> Prefix = 14; }
121 class A6 { bits<5> Prefix = 15; }
122 class A7 { bits<5> Prefix = 16; }
123 class T8XD { bits<5> Prefix = 17; }
124 class T8XS { bits<5> Prefix = 18; }
125 class TAXD { bits<5> Prefix = 19; }
126 class XOP8 { bits<5> Prefix = 20; }
127 class XOP9 { bits<5> Prefix = 21; }
128 class VEX { bit hasVEXPrefix = 1; }
129 class VEX_W { bit hasVEX_WPrefix = 1; }
130 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
131 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
132 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
133 class VEX_L { bit hasVEX_L = 1; }
134 class VEX_LIG { bit ignoresVEX_L = 1; }
135 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
136 class MemOp4 { bit hasMemOp4Prefix = 1; }
137 class XOP { bit hasXOP_Prefix = 1; }
138 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
141 Domain d = GenericDomain>
143 let Namespace = "X86";
145 bits<8> Opcode = opcod;
147 bits<6> FormBits = Form.Value;
150 dag OutOperandList = outs;
151 dag InOperandList = ins;
152 string AsmString = AsmStr;
154 // If this is a pseudo instruction, mark it isCodeGenOnly.
155 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
157 let Itinerary = itin;
160 // Attributes specific to X86 instructions...
162 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
163 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
165 bits<5> Prefix = 0; // Which prefix byte does this inst have?
166 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
167 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
168 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
169 bits<2> SegOvrBits = 0; // Segment override prefix.
170 Domain ExeDomain = d;
171 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
172 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
173 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
174 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
175 // encode the third operand?
176 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
177 // to be encoded in a immediate field?
178 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
179 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
180 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
181 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
182 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
184 // TSFlags layout should be kept in sync with X86InstrInfo.h.
185 let TSFlags{5-0} = FormBits;
186 let TSFlags{6} = hasOpSizePrefix;
187 let TSFlags{7} = hasAdSizePrefix;
188 let TSFlags{12-8} = Prefix;
189 let TSFlags{13} = hasREX_WPrefix;
190 let TSFlags{16-14} = ImmT.Value;
191 let TSFlags{19-17} = FPForm.Value;
192 let TSFlags{20} = hasLockPrefix;
193 let TSFlags{22-21} = SegOvrBits;
194 let TSFlags{24-23} = ExeDomain.Value;
195 let TSFlags{32-25} = Opcode;
196 let TSFlags{33} = hasVEXPrefix;
197 let TSFlags{34} = hasVEX_WPrefix;
198 let TSFlags{35} = hasVEX_4VPrefix;
199 let TSFlags{36} = hasVEX_4VOp3Prefix;
200 let TSFlags{37} = hasVEX_i8ImmReg;
201 let TSFlags{38} = hasVEX_L;
202 let TSFlags{39} = ignoresVEX_L;
203 let TSFlags{40} = has3DNow0F0FOpcode;
204 let TSFlags{41} = hasMemOp4Prefix;
205 let TSFlags{42} = hasXOP_Prefix;
208 class PseudoI<dag oops, dag iops, list<dag> pattern>
209 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
210 let Pattern = pattern;
213 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
214 list<dag> pattern, InstrItinClass itin = NoItinerary,
215 Domain d = GenericDomain>
216 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
217 let Pattern = pattern;
220 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
221 list<dag> pattern, InstrItinClass itin = NoItinerary,
222 Domain d = GenericDomain>
223 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
224 let Pattern = pattern;
227 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
228 list<dag> pattern, InstrItinClass itin = NoItinerary>
229 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
230 let Pattern = pattern;
233 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
234 list<dag> pattern, InstrItinClass itin = NoItinerary>
235 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
236 let Pattern = pattern;
239 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
240 list<dag> pattern, InstrItinClass itin = NoItinerary>
241 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
242 let Pattern = pattern;
246 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
247 list<dag> pattern, InstrItinClass itin = NoItinerary>
248 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
249 let Pattern = pattern;
253 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
254 list<dag> pattern, InstrItinClass itin = NoItinerary>
255 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
256 let Pattern = pattern;
260 // FPStack Instruction Templates:
261 // FPI - Floating Point Instruction template.
262 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
263 InstrItinClass itin = NoItinerary>
264 : I<o, F, outs, ins, asm, [], itin> {}
266 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
267 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
268 InstrItinClass itin = NoItinerary>
269 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
271 let Pattern = pattern;
274 // Templates for instructions that use a 16- or 32-bit segmented address as
275 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
277 // Iseg16 - 16-bit segment selector, 16-bit offset
278 // Iseg32 - 16-bit segment selector, 32-bit offset
280 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
281 list<dag> pattern, InstrItinClass itin = NoItinerary>
282 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
283 let Pattern = pattern;
287 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
288 list<dag> pattern, InstrItinClass itin = NoItinerary>
289 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
290 let Pattern = pattern;
296 // SI - SSE 1 & 2 scalar instructions
297 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
298 list<dag> pattern, InstrItinClass itin = NoItinerary>
299 : I<o, F, outs, ins, asm, pattern, itin> {
300 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
301 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
303 // AVX instructions have a 'v' prefix in the mnemonic
304 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
307 // SIi8 - SSE 1 & 2 scalar instructions
308 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
309 list<dag> pattern, InstrItinClass itin = NoItinerary>
310 : Ii8<o, F, outs, ins, asm, pattern, itin> {
311 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
312 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
314 // AVX instructions have a 'v' prefix in the mnemonic
315 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
318 // PI - SSE 1 & 2 packed instructions
319 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
320 InstrItinClass itin, Domain d>
321 : I<o, F, outs, ins, asm, pattern, itin, d> {
322 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
323 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
325 // AVX instructions have a 'v' prefix in the mnemonic
326 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
329 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
330 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
331 InstrItinClass itin, Domain d>
332 : I<o, F, outs, ins, asm, pattern, itin, d> {
333 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
336 // PIi8 - SSE 1 & 2 packed instructions with immediate
337 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
338 list<dag> pattern, InstrItinClass itin, Domain d>
339 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
340 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
341 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
343 // AVX instructions have a 'v' prefix in the mnemonic
344 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
347 // SSE1 Instruction Templates:
349 // SSI - SSE1 instructions with XS prefix.
350 // PSI - SSE1 instructions with TB prefix.
351 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
352 // VSSI - SSE1 instructions with XS prefix in AVX form.
353 // VPSI - SSE1 instructions with TB prefix in AVX form.
355 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
356 list<dag> pattern, InstrItinClass itin = NoItinerary>
357 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
358 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
359 list<dag> pattern, InstrItinClass itin = NoItinerary>
360 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
361 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
362 list<dag> pattern, InstrItinClass itin = NoItinerary>
363 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
365 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
366 list<dag> pattern, InstrItinClass itin = NoItinerary>
367 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
369 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
370 list<dag> pattern, InstrItinClass itin = NoItinerary>
371 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
373 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
374 list<dag> pattern, InstrItinClass itin = NoItinerary>
375 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
378 // SSE2 Instruction Templates:
380 // SDI - SSE2 instructions with XD prefix.
381 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
382 // S2SI - SSE2 instructions with XS prefix.
383 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
384 // PDI - SSE2 instructions with TB and OpSize prefixes.
385 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
386 // VSDI - SSE2 instructions with XD prefix in AVX form.
387 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
388 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
390 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
393 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
394 list<dag> pattern, InstrItinClass itin = NoItinerary>
395 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
396 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
397 list<dag> pattern, InstrItinClass itin = NoItinerary>
398 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
399 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
400 list<dag> pattern, InstrItinClass itin = NoItinerary>
401 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
402 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
403 list<dag> pattern, InstrItinClass itin = NoItinerary>
404 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
405 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
406 list<dag> pattern, InstrItinClass itin = NoItinerary>
407 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
409 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
410 list<dag> pattern, InstrItinClass itin = NoItinerary>
411 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
413 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
414 list<dag> pattern, InstrItinClass itin = NoItinerary>
415 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
417 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
418 list<dag> pattern, InstrItinClass itin = NoItinerary>
419 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
421 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
422 list<dag> pattern, InstrItinClass itin = NoItinerary>
423 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
424 OpSize, Requires<[HasAVX]>;
425 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
426 list<dag> pattern, InstrItinClass itin = NoItinerary>
427 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
428 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
429 list<dag> pattern, InstrItinClass itin = NoItinerary>
430 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
432 // SSE3 Instruction Templates:
434 // S3I - SSE3 instructions with TB and OpSize prefixes.
435 // S3SI - SSE3 instructions with XS prefix.
436 // S3DI - SSE3 instructions with XD prefix.
438 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
439 list<dag> pattern, InstrItinClass itin = NoItinerary>
440 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
442 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
443 list<dag> pattern, InstrItinClass itin = NoItinerary>
444 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
446 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
447 list<dag> pattern, InstrItinClass itin = NoItinerary>
448 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
452 // SSSE3 Instruction Templates:
454 // SS38I - SSSE3 instructions with T8 prefix.
455 // SS3AI - SSSE3 instructions with TA prefix.
456 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
457 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
459 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
460 // uses the MMX registers. The 64-bit versions are grouped with the MMX
461 // classes. They need to be enabled even if AVX is enabled.
463 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
464 list<dag> pattern, InstrItinClass itin = NoItinerary>
465 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
466 Requires<[UseSSSE3]>;
467 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
468 list<dag> pattern, InstrItinClass itin = NoItinerary>
469 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
470 Requires<[UseSSSE3]>;
471 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
472 list<dag> pattern, InstrItinClass itin = NoItinerary>
473 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
474 Requires<[HasSSSE3]>;
475 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
476 list<dag> pattern, InstrItinClass itin = NoItinerary>
477 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
478 Requires<[HasSSSE3]>;
480 // SSE4.1 Instruction Templates:
482 // SS48I - SSE 4.1 instructions with T8 prefix.
483 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
485 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
486 list<dag> pattern, InstrItinClass itin = NoItinerary>
487 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
488 Requires<[UseSSE41]>;
489 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
490 list<dag> pattern, InstrItinClass itin = NoItinerary>
491 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
492 Requires<[UseSSE41]>;
494 // SSE4.2 Instruction Templates:
496 // SS428I - SSE 4.2 instructions with T8 prefix.
497 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
498 list<dag> pattern, InstrItinClass itin = NoItinerary>
499 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
500 Requires<[UseSSE42]>;
502 // SS42FI - SSE 4.2 instructions with T8XD prefix.
503 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
504 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
505 list<dag> pattern, InstrItinClass itin = NoItinerary>
506 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
508 // SS42AI = SSE 4.2 instructions with TA prefix
509 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
510 list<dag> pattern, InstrItinClass itin = NoItinerary>
511 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
512 Requires<[UseSSE42]>;
514 // AVX Instruction Templates:
515 // Instructions introduced in AVX (no SSE equivalent forms)
517 // AVX8I - AVX instructions with T8 and OpSize prefix.
518 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
519 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
520 list<dag> pattern, InstrItinClass itin = NoItinerary>
521 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
523 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
524 list<dag> pattern, InstrItinClass itin = NoItinerary>
525 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
528 // AVX2 Instruction Templates:
529 // Instructions introduced in AVX2 (no SSE equivalent forms)
531 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
532 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
533 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
534 list<dag> pattern, InstrItinClass itin = NoItinerary>
535 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
537 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
538 list<dag> pattern, InstrItinClass itin = NoItinerary>
539 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
542 // AES Instruction Templates:
545 // These use the same encoding as the SSE4.2 T8 and TA encodings.
546 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
547 list<dag>pattern, InstrItinClass itin = NoItinerary>
548 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
551 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
552 list<dag> pattern, InstrItinClass itin = NoItinerary>
553 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
556 // PCLMUL Instruction Templates
557 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
558 list<dag>pattern, InstrItinClass itin = NoItinerary>
559 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
560 OpSize, Requires<[HasPCLMUL]>;
562 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
563 list<dag>pattern, InstrItinClass itin = NoItinerary>
564 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
565 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
567 // FMA3 Instruction Templates
568 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
569 list<dag>pattern, InstrItinClass itin = NoItinerary>
570 : I<o, F, outs, ins, asm, pattern, itin>, T8,
571 OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
573 // FMA4 Instruction Templates
574 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
575 list<dag>pattern, InstrItinClass itin = NoItinerary>
576 : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
577 OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
579 // XOP 2, 3 and 4 Operand Instruction Template
580 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
581 list<dag> pattern, InstrItinClass itin = NoItinerary>
582 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
583 XOP, XOP9, Requires<[HasXOP]>;
585 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
586 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
587 list<dag> pattern, InstrItinClass itin = NoItinerary>
588 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
589 XOP, XOP8, Requires<[HasXOP]>;
591 // XOP 5 operand instruction (VEX encoding!)
592 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
593 list<dag>pattern, InstrItinClass itin = NoItinerary>
594 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
595 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
597 // X86-64 Instruction templates...
600 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
601 list<dag> pattern, InstrItinClass itin = NoItinerary>
602 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
603 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = NoItinerary>
605 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
606 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
607 list<dag> pattern, InstrItinClass itin = NoItinerary>
608 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
610 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
611 list<dag> pattern, InstrItinClass itin = NoItinerary>
612 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
613 let Pattern = pattern;
617 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
618 list<dag> pattern, InstrItinClass itin = NoItinerary>
619 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
620 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
621 list<dag> pattern, InstrItinClass itin = NoItinerary>
622 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
623 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = NoItinerary>
625 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
626 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
627 list<dag> pattern, InstrItinClass itin = NoItinerary>
628 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
630 // MMX Instruction templates
633 // MMXI - MMX instructions with TB prefix.
634 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
635 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
636 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
637 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
638 // MMXID - MMX instructions with XD prefix.
639 // MMXIS - MMX instructions with XS prefix.
640 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
641 list<dag> pattern, InstrItinClass itin = NoItinerary>
642 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
643 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
644 list<dag> pattern, InstrItinClass itin = NoItinerary>
645 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
646 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
647 list<dag> pattern, InstrItinClass itin = NoItinerary>
648 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
649 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
650 list<dag> pattern, InstrItinClass itin = NoItinerary>
651 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
652 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
653 list<dag> pattern, InstrItinClass itin = NoItinerary>
654 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
655 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
656 list<dag> pattern, InstrItinClass itin = NoItinerary>
657 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
658 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
659 list<dag> pattern, InstrItinClass itin = NoItinerary>
660 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;