1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
43 // ImmType - This specifies the immediate type used by an instruction. This is
44 // part of the ad-hoc solution used to emit machine instruction encodings by our
45 // machine code emitter.
46 class ImmType<bits<3> val> {
49 def NoImm : ImmType<0>;
50 def Imm8 : ImmType<1>;
51 def Imm8PCRel : ImmType<2>;
52 def Imm16 : ImmType<3>;
53 def Imm32 : ImmType<4>;
54 def Imm32PCRel : ImmType<5>;
55 def Imm64 : ImmType<6>;
57 // FPFormat - This specifies what form this FP instruction has. This is used by
58 // the Floating-Point stackifier pass.
59 class FPFormat<bits<3> val> {
62 def NotFP : FPFormat<0>;
63 def ZeroArgFP : FPFormat<1>;
64 def OneArgFP : FPFormat<2>;
65 def OneArgFPRW : FPFormat<3>;
66 def TwoArgFP : FPFormat<4>;
67 def CompareFP : FPFormat<5>;
68 def CondMovFP : FPFormat<6>;
69 def SpecialFP : FPFormat<7>;
71 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
72 // Keep in sync with tables in X86InstrInfo.cpp.
73 class Domain<bits<2> val> {
76 def GenericDomain : Domain<0>;
77 def SSEPackedSingle : Domain<1>;
78 def SSEPackedDouble : Domain<2>;
79 def SSEPackedInt : Domain<3>;
81 // Prefix byte classes which are used to indicate to the ad-hoc machine code
82 // emitter that various prefix bytes are required.
83 class OpSize { bit hasOpSizePrefix = 1; }
84 class AdSize { bit hasAdSizePrefix = 1; }
85 class REX_W { bit hasREX_WPrefix = 1; }
86 class LOCK { bit hasLockPrefix = 1; }
87 class SegFS { bits<2> SegOvrBits = 1; }
88 class SegGS { bits<2> SegOvrBits = 2; }
89 class TB { bits<4> Prefix = 1; }
90 class REP { bits<4> Prefix = 2; }
91 class D8 { bits<4> Prefix = 3; }
92 class D9 { bits<4> Prefix = 4; }
93 class DA { bits<4> Prefix = 5; }
94 class DB { bits<4> Prefix = 6; }
95 class DC { bits<4> Prefix = 7; }
96 class DD { bits<4> Prefix = 8; }
97 class DE { bits<4> Prefix = 9; }
98 class DF { bits<4> Prefix = 10; }
99 class XD { bits<4> Prefix = 11; }
100 class XS { bits<4> Prefix = 12; }
101 class T8 { bits<4> Prefix = 13; }
102 class TA { bits<4> Prefix = 14; }
103 class TF { bits<4> Prefix = 15; }
105 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
106 string AsmStr, Domain d = GenericDomain>
108 let Namespace = "X86";
110 bits<8> Opcode = opcod;
112 bits<6> FormBits = Form.Value;
115 dag OutOperandList = outs;
116 dag InOperandList = ins;
117 string AsmString = AsmStr;
120 // Attributes specific to X86 instructions...
122 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
123 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
125 bits<4> Prefix = 0; // Which prefix byte does this inst have?
126 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
127 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
128 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
129 bits<2> SegOvrBits = 0; // Segment override prefix.
130 Domain ExeDomain = d;
132 // TSFlags layout should be kept in sync with X86InstrInfo.h.
133 let TSFlags{5-0} = FormBits;
134 let TSFlags{6} = hasOpSizePrefix;
135 let TSFlags{7} = hasAdSizePrefix;
136 let TSFlags{11-8} = Prefix;
137 let TSFlags{12} = hasREX_WPrefix;
138 let TSFlags{15-13} = ImmT.Value;
139 let TSFlags{18-16} = FPForm.Value;
140 let TSFlags{19} = hasLockPrefix;
141 let TSFlags{21-20} = SegOvrBits;
142 let TSFlags{23-22} = ExeDomain.Value;
143 let TSFlags{31-24} = Opcode;
146 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
147 list<dag> pattern, Domain d = GenericDomain>
148 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
149 let Pattern = pattern;
152 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
153 list<dag> pattern, Domain d = GenericDomain>
154 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
155 let Pattern = pattern;
158 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
160 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
161 let Pattern = pattern;
164 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
166 : X86Inst<o, f, Imm16, outs, ins, asm> {
167 let Pattern = pattern;
170 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
172 : X86Inst<o, f, Imm32, outs, ins, asm> {
173 let Pattern = pattern;
177 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
179 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
180 let Pattern = pattern;
184 // FPStack Instruction Templates:
185 // FPI - Floating Point Instruction template.
186 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
187 : I<o, F, outs, ins, asm, []> {}
189 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
190 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
191 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
193 let Pattern = pattern;
196 // Templates for instructions that use a 16- or 32-bit segmented address as
197 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
199 // Iseg16 - 16-bit segment selector, 16-bit offset
200 // Iseg32 - 16-bit segment selector, 32-bit offset
202 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
203 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
204 let Pattern = pattern;
208 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
209 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
210 let Pattern = pattern;
214 // SSE1 Instruction Templates:
216 // SSI - SSE1 instructions with XS prefix.
217 // PSI - SSE1 instructions with TB prefix.
218 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
220 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
221 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
222 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
224 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
225 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
226 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
228 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
230 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
233 // SSE2 Instruction Templates:
235 // SDI - SSE2 instructions with XD prefix.
236 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
237 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
238 // PDI - SSE2 instructions with TB and OpSize prefixes.
239 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
241 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
242 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
243 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
245 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
246 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
248 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
249 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
250 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
252 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
254 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
257 // SSE3 Instruction Templates:
259 // S3I - SSE3 instructions with TB and OpSize prefixes.
260 // S3SI - SSE3 instructions with XS prefix.
261 // S3DI - SSE3 instructions with XD prefix.
263 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
265 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
267 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
269 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
271 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
272 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
276 // SSSE3 Instruction Templates:
278 // SS38I - SSSE3 instructions with T8 prefix.
279 // SS3AI - SSSE3 instructions with TA prefix.
281 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
282 // uses the MMX registers. We put those instructions here because they better
283 // fit into the SSSE3 instruction category rather than the MMX category.
285 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
287 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
288 Requires<[HasSSSE3]>;
289 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
291 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
292 Requires<[HasSSSE3]>;
294 // SSE4.1 Instruction Templates:
296 // SS48I - SSE 4.1 instructions with T8 prefix.
297 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
299 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
301 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
302 Requires<[HasSSE41]>;
303 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
305 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
306 Requires<[HasSSE41]>;
308 // SSE4.2 Instruction Templates:
310 // SS428I - SSE 4.2 instructions with T8 prefix.
311 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
313 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
314 Requires<[HasSSE42]>;
316 // SS42FI - SSE 4.2 instructions with TF prefix.
317 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
319 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
321 // SS42AI = SSE 4.2 instructions with TA prefix
322 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
324 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
325 Requires<[HasSSE42]>;
327 // AES Instruction Templates:
330 // These use the same encoding as the SSE4.2 T8 and TA encodings.
331 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
333 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
336 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
338 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
341 // X86-64 Instruction templates...
344 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
345 : I<o, F, outs, ins, asm, pattern>, REX_W;
346 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
348 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
349 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
351 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
353 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
355 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
356 let Pattern = pattern;
360 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
362 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
363 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
365 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
366 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
368 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
370 // MMX Instruction templates
373 // MMXI - MMX instructions with TB prefix.
374 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
375 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
376 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
377 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
378 // MMXID - MMX instructions with XD prefix.
379 // MMXIS - MMX instructions with XS prefix.
380 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
382 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
383 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
385 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
386 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
388 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
389 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
391 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
392 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
394 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
395 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
397 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
398 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
400 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;