1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
45 // ImmType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class ImmType<bits<3> val> {
51 def NoImm : ImmType<0>;
52 def Imm8 : ImmType<1>;
53 def Imm8PCRel : ImmType<2>;
54 def Imm16 : ImmType<3>;
55 def Imm16PCRel : ImmType<4>;
56 def Imm32 : ImmType<5>;
57 def Imm32PCRel : ImmType<6>;
58 def Imm64 : ImmType<7>;
60 // FPFormat - This specifies what form this FP instruction has. This is used by
61 // the Floating-Point stackifier pass.
62 class FPFormat<bits<3> val> {
65 def NotFP : FPFormat<0>;
66 def ZeroArgFP : FPFormat<1>;
67 def OneArgFP : FPFormat<2>;
68 def OneArgFPRW : FPFormat<3>;
69 def TwoArgFP : FPFormat<4>;
70 def CompareFP : FPFormat<5>;
71 def CondMovFP : FPFormat<6>;
72 def SpecialFP : FPFormat<7>;
74 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
75 // Keep in sync with tables in X86InstrInfo.cpp.
76 class Domain<bits<2> val> {
79 def GenericDomain : Domain<0>;
80 def SSEPackedSingle : Domain<1>;
81 def SSEPackedDouble : Domain<2>;
82 def SSEPackedInt : Domain<3>;
84 // Prefix byte classes which are used to indicate to the ad-hoc machine code
85 // emitter that various prefix bytes are required.
86 class OpSize { bit hasOpSizePrefix = 1; }
87 class AdSize { bit hasAdSizePrefix = 1; }
88 class REX_W { bit hasREX_WPrefix = 1; }
89 class LOCK { bit hasLockPrefix = 1; }
90 class SegFS { bits<2> SegOvrBits = 1; }
91 class SegGS { bits<2> SegOvrBits = 2; }
92 class TB { bits<4> Prefix = 1; }
93 class REP { bits<4> Prefix = 2; }
94 class D8 { bits<4> Prefix = 3; }
95 class D9 { bits<4> Prefix = 4; }
96 class DA { bits<4> Prefix = 5; }
97 class DB { bits<4> Prefix = 6; }
98 class DC { bits<4> Prefix = 7; }
99 class DD { bits<4> Prefix = 8; }
100 class DE { bits<4> Prefix = 9; }
101 class DF { bits<4> Prefix = 10; }
102 class XD { bits<4> Prefix = 11; }
103 class XS { bits<4> Prefix = 12; }
104 class T8 { bits<4> Prefix = 13; }
105 class TA { bits<4> Prefix = 14; }
106 class TF { bits<4> Prefix = 15; }
107 class VEX { bit hasVEXPrefix = 1; }
108 class VEX_W { bit hasVEX_WPrefix = 1; }
109 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
110 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
111 class VEX_L { bit hasVEX_L = 1; }
112 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
114 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
115 string AsmStr, Domain d = GenericDomain>
117 let Namespace = "X86";
119 bits<8> Opcode = opcod;
121 bits<6> FormBits = Form.Value;
124 dag OutOperandList = outs;
125 dag InOperandList = ins;
126 string AsmString = AsmStr;
129 // Attributes specific to X86 instructions...
131 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
132 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
134 bits<4> Prefix = 0; // Which prefix byte does this inst have?
135 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
136 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
137 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
138 bits<2> SegOvrBits = 0; // Segment override prefix.
139 Domain ExeDomain = d;
140 bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix?
141 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
142 bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field?
143 bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register
144 // to be encoded in a immediate field?
145 bit hasVEX_L = 0; // Does this inst uses large (256-bit) registers?
146 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
148 // TSFlags layout should be kept in sync with X86InstrInfo.h.
149 let TSFlags{5-0} = FormBits;
150 let TSFlags{6} = hasOpSizePrefix;
151 let TSFlags{7} = hasAdSizePrefix;
152 let TSFlags{11-8} = Prefix;
153 let TSFlags{12} = hasREX_WPrefix;
154 let TSFlags{15-13} = ImmT.Value;
155 let TSFlags{18-16} = FPForm.Value;
156 let TSFlags{19} = hasLockPrefix;
157 let TSFlags{21-20} = SegOvrBits;
158 let TSFlags{23-22} = ExeDomain.Value;
159 let TSFlags{31-24} = Opcode;
160 let TSFlags{32} = hasVEXPrefix;
161 let TSFlags{33} = hasVEX_WPrefix;
162 let TSFlags{34} = hasVEX_4VPrefix;
163 let TSFlags{35} = hasVEX_i8ImmReg;
164 let TSFlags{36} = hasVEX_L;
165 let TSFlags{37} = has3DNow0F0FOpcode;
168 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
169 list<dag> pattern, Domain d = GenericDomain>
170 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
171 let Pattern = pattern;
174 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
175 list<dag> pattern, Domain d = GenericDomain>
176 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
177 let Pattern = pattern;
180 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
182 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
183 let Pattern = pattern;
186 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
188 : X86Inst<o, f, Imm16, outs, ins, asm> {
189 let Pattern = pattern;
192 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
194 : X86Inst<o, f, Imm32, outs, ins, asm> {
195 let Pattern = pattern;
199 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
201 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
202 let Pattern = pattern;
206 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
208 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
209 let Pattern = pattern;
213 // FPStack Instruction Templates:
214 // FPI - Floating Point Instruction template.
215 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
216 : I<o, F, outs, ins, asm, []> {}
218 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
219 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
220 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
222 let Pattern = pattern;
225 // Templates for instructions that use a 16- or 32-bit segmented address as
226 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
228 // Iseg16 - 16-bit segment selector, 16-bit offset
229 // Iseg32 - 16-bit segment selector, 32-bit offset
231 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
232 list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
233 let Pattern = pattern;
237 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
238 list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
239 let Pattern = pattern;
243 // SI - SSE 1 & 2 scalar instructions
244 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
245 : I<o, F, outs, ins, asm, pattern> {
246 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
247 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
249 // AVX instructions have a 'v' prefix in the mnemonic
250 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
253 // SIi8 - SSE 1 & 2 scalar instructions
254 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
256 : Ii8<o, F, outs, ins, asm, pattern> {
257 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
258 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
260 // AVX instructions have a 'v' prefix in the mnemonic
261 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
264 // PI - SSE 1 & 2 packed instructions
265 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
267 : I<o, F, outs, ins, asm, pattern, d> {
268 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
269 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
271 // AVX instructions have a 'v' prefix in the mnemonic
272 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
275 // PIi8 - SSE 1 & 2 packed instructions with immediate
276 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
277 list<dag> pattern, Domain d>
278 : Ii8<o, F, outs, ins, asm, pattern, d> {
279 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
280 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
282 // AVX instructions have a 'v' prefix in the mnemonic
283 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
286 // SSE1 Instruction Templates:
288 // SSI - SSE1 instructions with XS prefix.
289 // PSI - SSE1 instructions with TB prefix.
290 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
291 // VSSI - SSE1 instructions with XS prefix in AVX form.
292 // VPSI - SSE1 instructions with TB prefix in AVX form.
294 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
295 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
296 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
298 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
299 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
300 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
302 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
304 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
306 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
308 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
310 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
312 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
315 // SSE2 Instruction Templates:
317 // SDI - SSE2 instructions with XD prefix.
318 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
319 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
320 // PDI - SSE2 instructions with TB and OpSize prefixes.
321 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
322 // VSDI - SSE2 instructions with XD prefix in AVX form.
323 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
325 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
326 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
327 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
329 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
330 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
332 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
333 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
334 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
336 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
338 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
340 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
342 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
344 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
346 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
347 OpSize, Requires<[HasAVX]>;
349 // SSE3 Instruction Templates:
351 // S3I - SSE3 instructions with TB and OpSize prefixes.
352 // S3SI - SSE3 instructions with XS prefix.
353 // S3DI - SSE3 instructions with XD prefix.
355 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
357 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
359 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
361 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
363 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
364 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
368 // SSSE3 Instruction Templates:
370 // SS38I - SSSE3 instructions with T8 prefix.
371 // SS3AI - SSSE3 instructions with TA prefix.
373 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
374 // uses the MMX registers. We put those instructions here because they better
375 // fit into the SSSE3 instruction category rather than the MMX category.
377 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
379 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
380 Requires<[HasSSSE3]>;
381 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
383 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
384 Requires<[HasSSSE3]>;
386 // SSE4.1 Instruction Templates:
388 // SS48I - SSE 4.1 instructions with T8 prefix.
389 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
391 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
393 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
394 Requires<[HasSSE41]>;
395 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
397 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
398 Requires<[HasSSE41]>;
400 // SSE4.2 Instruction Templates:
402 // SS428I - SSE 4.2 instructions with T8 prefix.
403 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
405 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
406 Requires<[HasSSE42]>;
408 // SS42FI - SSE 4.2 instructions with TF prefix.
409 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
413 // SS42AI = SSE 4.2 instructions with TA prefix
414 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
416 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
417 Requires<[HasSSE42]>;
419 // AVX Instruction Templates:
420 // Instructions introduced in AVX (no SSE equivalent forms)
422 // AVX8I - AVX instructions with T8 and OpSize prefix.
423 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
424 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
426 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
428 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
430 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
433 // AES Instruction Templates:
436 // These use the same encoding as the SSE4.2 T8 and TA encodings.
437 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
439 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
442 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
444 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
447 // CLMUL Instruction Templates
448 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
450 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
451 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
453 // FMA3 Instruction Templates
454 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
456 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
457 OpSize, VEX_4V, Requires<[HasFMA3]>;
459 // X86-64 Instruction templates...
462 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
463 : I<o, F, outs, ins, asm, pattern>, REX_W;
464 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
466 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
467 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
469 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
471 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
473 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
474 let Pattern = pattern;
478 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
480 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
481 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
483 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
484 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
486 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
488 // MMX Instruction templates
491 // MMXI - MMX instructions with TB prefix.
492 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
493 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
494 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
495 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
496 // MMXID - MMX instructions with XD prefix.
497 // MMXIS - MMX instructions with XS prefix.
498 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
500 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
501 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
503 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
504 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
506 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
507 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
509 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
510 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
512 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
513 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
515 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
516 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
518 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;