1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def RawFrmImm8 : Format<11>;
28 def RawFrmImm16 : Format<12>;
29 def MRMXr : Format<14>; def MRMXm : Format<15>;
30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
32 def MRM6r : Format<22>; def MRM7r : Format<23>;
33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
35 def MRM6m : Format<30>; def MRM7m : Format<31>;
36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
39 def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>;
40 def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>;
41 def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>;
42 def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>;
43 def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>;
44 def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>;
45 def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>;
46 def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>;
47 def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>;
48 def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>;
49 def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>;
50 def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>;
51 def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>;
52 def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>;
53 def MRM_FE : Format<83>; def MRM_FF : Format<84>;
55 // ImmType - This specifies the immediate type used by an instruction. This is
56 // part of the ad-hoc solution used to emit machine instruction encodings by our
57 // machine code emitter.
58 class ImmType<bits<4> val> {
61 def NoImm : ImmType<0>;
62 def Imm8 : ImmType<1>;
63 def Imm8PCRel : ImmType<2>;
64 def Imm16 : ImmType<3>;
65 def Imm16PCRel : ImmType<4>;
66 def Imm32 : ImmType<5>;
67 def Imm32PCRel : ImmType<6>;
68 def Imm32S : ImmType<7>;
69 def Imm64 : ImmType<8>;
71 // FPFormat - This specifies what form this FP instruction has. This is used by
72 // the Floating-Point stackifier pass.
73 class FPFormat<bits<3> val> {
76 def NotFP : FPFormat<0>;
77 def ZeroArgFP : FPFormat<1>;
78 def OneArgFP : FPFormat<2>;
79 def OneArgFPRW : FPFormat<3>;
80 def TwoArgFP : FPFormat<4>;
81 def CompareFP : FPFormat<5>;
82 def CondMovFP : FPFormat<6>;
83 def SpecialFP : FPFormat<7>;
85 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
86 // Keep in sync with tables in X86InstrInfo.cpp.
87 class Domain<bits<2> val> {
90 def GenericDomain : Domain<0>;
91 def SSEPackedSingle : Domain<1>;
92 def SSEPackedDouble : Domain<2>;
93 def SSEPackedInt : Domain<3>;
95 // Class specifying the vector form of the decompressed
96 // displacement of 8-bit.
97 class CD8VForm<bits<3> val> {
100 def CD8VF : CD8VForm<0>; // v := VL
101 def CD8VH : CD8VForm<1>; // v := VL/2
102 def CD8VQ : CD8VForm<2>; // v := VL/4
103 def CD8VO : CD8VForm<3>; // v := VL/8
104 // The tuple (subvector) forms.
105 def CD8VT1 : CD8VForm<4>; // v := 1
106 def CD8VT2 : CD8VForm<5>; // v := 2
107 def CD8VT4 : CD8VForm<6>; // v := 4
108 def CD8VT8 : CD8VForm<7>; // v := 8
110 // Class specifying the prefix used an opcode extension.
111 class Prefix<bits<3> val> {
114 def NoPrfx : Prefix<0>;
120 // Class specifying the opcode map.
121 class Map<bits<3> val> {
132 // Class specifying the encoding
133 class Encoding<bits<2> val> {
136 def EncNormal : Encoding<0>;
137 def EncVEX : Encoding<1>;
138 def EncXOP : Encoding<2>;
139 def EncEVEX : Encoding<3>;
141 // Operand size for encodings that change based on mode.
142 class OperandSize<bits<2> val> {
145 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
146 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
147 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
149 // Address size for encodings that change based on mode.
150 class AddressSize<bits<2> val> {
153 def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
154 def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
155 def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
156 def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
158 // Prefix byte classes which are used to indicate to the ad-hoc machine code
159 // emitter that various prefix bytes are required.
160 class OpSize16 { OperandSize OpSize = OpSize16; }
161 class OpSize32 { OperandSize OpSize = OpSize32; }
162 class AdSize16 { AddressSize AdSize = AdSize16; }
163 class AdSize32 { AddressSize AdSize = AdSize32; }
164 class AdSize64 { AddressSize AdSize = AdSize64; }
165 class REX_W { bit hasREX_WPrefix = 1; }
166 class LOCK { bit hasLockPrefix = 1; }
167 class REP { bit hasREPPrefix = 1; }
168 class TB { Map OpMap = TB; }
169 class T8 { Map OpMap = T8; }
170 class TA { Map OpMap = TA; }
171 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
172 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
173 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
174 class OBXS { Prefix OpPrefix = XS; }
175 class PS : TB { Prefix OpPrefix = PS; }
176 class PD : TB { Prefix OpPrefix = PD; }
177 class XD : TB { Prefix OpPrefix = XD; }
178 class XS : TB { Prefix OpPrefix = XS; }
179 class T8PS : T8 { Prefix OpPrefix = PS; }
180 class T8PD : T8 { Prefix OpPrefix = PD; }
181 class T8XD : T8 { Prefix OpPrefix = XD; }
182 class T8XS : T8 { Prefix OpPrefix = XS; }
183 class TAPS : TA { Prefix OpPrefix = PS; }
184 class TAPD : TA { Prefix OpPrefix = PD; }
185 class TAXD : TA { Prefix OpPrefix = XD; }
186 class VEX { Encoding OpEnc = EncVEX; }
187 class VEX_W { bit hasVEX_WPrefix = 1; }
188 class VEX_4V : VEX { bit hasVEX_4V = 1; }
189 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; }
190 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
191 class VEX_L { bit hasVEX_L = 1; }
192 class VEX_LIG { bit ignoresVEX_L = 1; }
193 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
194 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
195 class EVEX_K { bit hasEVEX_K = 1; }
196 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
197 class EVEX_B { bit hasEVEX_B = 1; }
198 class EVEX_RC { bit hasEVEX_RC = 1; }
199 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
200 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }
201 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }
203 // Specify AVX512 8-bit compressed displacement encoding based on the vector
204 // element size in bits (8, 16, 32, 64) and the CDisp8 form.
205 class EVEX_CD8<int esize, CD8VForm form> {
206 int CD8_EltSize = !srl(esize, 3);
207 bits<3> CD8_Form = form.Value;
210 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
211 class MemOp4 { bit hasMemOp4Prefix = 1; }
212 class XOP { Encoding OpEnc = EncXOP; }
213 class XOP_4V : XOP { bit hasVEX_4V = 1; }
214 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; }
216 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
219 Domain d = GenericDomain>
221 let Namespace = "X86";
223 bits<8> Opcode = opcod;
225 bits<7> FormBits = Form.Value;
228 dag OutOperandList = outs;
229 dag InOperandList = ins;
230 string AsmString = AsmStr;
232 // If this is a pseudo instruction, mark it isCodeGenOnly.
233 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
235 let Itinerary = itin;
238 // Attributes specific to X86 instructions...
240 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
241 // isCodeGenonly. Needed to hide an ambiguous
242 // AsmString from the parser, but still disassemble.
244 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
245 // based on operand size of the mode?
246 bits<2> OpSizeBits = OpSize.Value;
247 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
248 // based on address size of the mode?
249 bits<2> AdSizeBits = AdSize.Value;
251 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
252 bits<3> OpPrefixBits = OpPrefix.Value;
253 Map OpMap = OB; // Which opcode map does this inst have?
254 bits<3> OpMapBits = OpMap.Value;
255 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
256 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
257 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
258 Domain ExeDomain = d;
259 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
260 Encoding OpEnc = EncNormal; // Encoding used by this instruction
261 bits<2> OpEncBits = OpEnc.Value;
262 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
263 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
264 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to
265 // encode the third operand?
266 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
267 // to be encoded in a immediate field?
268 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
269 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
270 bit hasEVEX_K = 0; // Does this inst require masking?
271 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
272 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
273 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
274 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
275 // Declare it int rather than bits<4> so that all bits are defined when
276 // assigning to bits<7>.
277 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
278 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
279 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
280 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
283 let EVEX_LL{0} = hasVEX_L;
284 let EVEX_LL{1} = hasEVEX_L2;
285 // Vector size in bytes.
286 bits<7> VectSize = !shl(16, EVEX_LL);
288 // The scaling factor for AVX512's compressed displacement is either
289 // - the size of a power-of-two number of elements or
290 // - the size of a single element for broadcasts or
291 // - the total vector size divided by a power-of-two number.
292 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
293 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
295 !shl(CD8_EltSize, CD8_Form{1-0}),
298 !srl(VectSize, CD8_Form{1-0}))), 0);
300 // TSFlags layout should be kept in sync with X86BaseInfo.h.
301 let TSFlags{6-0} = FormBits;
302 let TSFlags{8-7} = OpSizeBits;
303 let TSFlags{10-9} = AdSizeBits;
304 let TSFlags{13-11} = OpPrefixBits;
305 let TSFlags{16-14} = OpMapBits;
306 let TSFlags{17} = hasREX_WPrefix;
307 let TSFlags{21-18} = ImmT.Value;
308 let TSFlags{24-22} = FPForm.Value;
309 let TSFlags{25} = hasLockPrefix;
310 let TSFlags{26} = hasREPPrefix;
311 let TSFlags{28-27} = ExeDomain.Value;
312 let TSFlags{30-29} = OpEncBits;
313 let TSFlags{38-31} = Opcode;
314 let TSFlags{39} = hasVEX_WPrefix;
315 let TSFlags{40} = hasVEX_4V;
316 let TSFlags{41} = hasVEX_4VOp3;
317 let TSFlags{42} = hasVEX_i8ImmReg;
318 let TSFlags{43} = hasVEX_L;
319 let TSFlags{44} = ignoresVEX_L;
320 let TSFlags{45} = hasEVEX_K;
321 let TSFlags{46} = hasEVEX_Z;
322 let TSFlags{47} = hasEVEX_L2;
323 let TSFlags{48} = hasEVEX_B;
324 // If we run out of TSFlags bits, it's possible to encode this in 3 bits.
325 let TSFlags{55-49} = CD8_Scale;
326 let TSFlags{56} = has3DNow0F0FOpcode;
327 let TSFlags{57} = hasMemOp4Prefix;
328 let TSFlags{58} = hasEVEX_RC;
331 class PseudoI<dag oops, dag iops, list<dag> pattern>
332 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
333 let Pattern = pattern;
336 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
337 list<dag> pattern, InstrItinClass itin = NoItinerary,
338 Domain d = GenericDomain>
339 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
340 let Pattern = pattern;
343 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
344 list<dag> pattern, InstrItinClass itin = NoItinerary,
345 Domain d = GenericDomain>
346 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
347 let Pattern = pattern;
350 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
351 list<dag> pattern, InstrItinClass itin = NoItinerary>
352 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
353 let Pattern = pattern;
356 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
357 list<dag> pattern, InstrItinClass itin = NoItinerary>
358 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
359 let Pattern = pattern;
362 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
363 list<dag> pattern, InstrItinClass itin = NoItinerary>
364 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
365 let Pattern = pattern;
368 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
369 list<dag> pattern, InstrItinClass itin = NoItinerary>
370 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
371 let Pattern = pattern;
375 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
376 list<dag> pattern, InstrItinClass itin = NoItinerary>
377 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
378 let Pattern = pattern;
382 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
383 list<dag> pattern, InstrItinClass itin = NoItinerary>
384 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
385 let Pattern = pattern;
389 // FPStack Instruction Templates:
390 // FPI - Floating Point Instruction template.
391 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
392 InstrItinClass itin = NoItinerary>
393 : I<o, F, outs, ins, asm, [], itin> {}
395 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
396 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
397 InstrItinClass itin = NoItinerary>
398 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
400 let Pattern = pattern;
403 // Templates for instructions that use a 16- or 32-bit segmented address as
404 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
406 // Iseg16 - 16-bit segment selector, 16-bit offset
407 // Iseg32 - 16-bit segment selector, 32-bit offset
409 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
410 list<dag> pattern, InstrItinClass itin = NoItinerary>
411 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
412 let Pattern = pattern;
416 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
417 list<dag> pattern, InstrItinClass itin = NoItinerary>
418 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
419 let Pattern = pattern;
423 // SI - SSE 1 & 2 scalar instructions
424 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
425 list<dag> pattern, InstrItinClass itin = NoItinerary,
426 Domain d = GenericDomain>
427 : I<o, F, outs, ins, asm, pattern, itin, d> {
428 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
429 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
430 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
431 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
432 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
435 // AVX instructions have a 'v' prefix in the mnemonic
436 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
437 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
441 // SIi8 - SSE 1 & 2 scalar instructions
442 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
443 list<dag> pattern, InstrItinClass itin = NoItinerary>
444 : Ii8<o, F, outs, ins, asm, pattern, itin> {
445 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
446 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
447 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
450 // AVX instructions have a 'v' prefix in the mnemonic
451 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
452 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
456 // PI - SSE 1 & 2 packed instructions
457 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
458 InstrItinClass itin, Domain d>
459 : I<o, F, outs, ins, asm, pattern, itin, d> {
460 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
461 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
462 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
465 // AVX instructions have a 'v' prefix in the mnemonic
466 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
467 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
471 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
472 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
473 InstrItinClass itin, Domain d>
474 : I<o, F, outs, ins, asm, pattern, itin, d> {
475 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
479 // PIi8 - SSE 1 & 2 packed instructions with immediate
480 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin, Domain d>
482 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
483 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
484 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
485 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
488 // AVX instructions have a 'v' prefix in the mnemonic
489 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
490 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
494 // SSE1 Instruction Templates:
496 // SSI - SSE1 instructions with XS prefix.
497 // PSI - SSE1 instructions with PS prefix.
498 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
499 // VSSI - SSE1 instructions with XS prefix in AVX form.
500 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
502 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
505 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
506 list<dag> pattern, InstrItinClass itin = NoItinerary>
507 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
508 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
509 list<dag> pattern, InstrItinClass itin = NoItinerary>
510 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
512 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
513 list<dag> pattern, InstrItinClass itin = NoItinerary>
514 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
516 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
517 list<dag> pattern, InstrItinClass itin = NoItinerary>
518 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
520 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
521 list<dag> pattern, InstrItinClass itin = NoItinerary>
522 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
525 // SSE2 Instruction Templates:
527 // SDI - SSE2 instructions with XD prefix.
528 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
529 // S2SI - SSE2 instructions with XS prefix.
530 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
531 // PDI - SSE2 instructions with PD prefix, packed double domain.
532 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
533 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
534 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
535 // packed double domain.
536 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
537 // S2I - SSE2 scalar instructions with PD prefix.
538 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
540 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
543 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
544 list<dag> pattern, InstrItinClass itin = NoItinerary>
545 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
546 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
547 list<dag> pattern, InstrItinClass itin = NoItinerary>
548 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
549 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
550 list<dag> pattern, InstrItinClass itin = NoItinerary>
551 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
552 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
553 list<dag> pattern, InstrItinClass itin = NoItinerary>
554 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
555 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
556 list<dag> pattern, InstrItinClass itin = NoItinerary>
557 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
559 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
560 list<dag> pattern, InstrItinClass itin = NoItinerary>
561 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
563 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
564 list<dag> pattern, InstrItinClass itin = NoItinerary>
565 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
567 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
568 list<dag> pattern, InstrItinClass itin = NoItinerary>
569 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
571 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
572 list<dag> pattern, InstrItinClass itin = NoItinerary>
573 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
574 PD, Requires<[HasAVX]>;
575 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
576 list<dag> pattern, InstrItinClass itin = NoItinerary>
577 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
579 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
580 list<dag> pattern, InstrItinClass itin = NoItinerary>
581 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
582 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
583 list<dag> pattern, InstrItinClass itin = NoItinerary>
584 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
585 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
586 list<dag> pattern, InstrItinClass itin = NoItinerary>
587 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
589 // SSE3 Instruction Templates:
591 // S3I - SSE3 instructions with PD prefixes.
592 // S3SI - SSE3 instructions with XS prefix.
593 // S3DI - SSE3 instructions with XD prefix.
595 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
596 list<dag> pattern, InstrItinClass itin = NoItinerary>
597 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
599 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
600 list<dag> pattern, InstrItinClass itin = NoItinerary>
601 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
603 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = NoItinerary>
605 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
609 // SSSE3 Instruction Templates:
611 // SS38I - SSSE3 instructions with T8 prefix.
612 // SS3AI - SSSE3 instructions with TA prefix.
613 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
614 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
616 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
617 // uses the MMX registers. The 64-bit versions are grouped with the MMX
618 // classes. They need to be enabled even if AVX is enabled.
620 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
621 list<dag> pattern, InstrItinClass itin = NoItinerary>
622 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
623 Requires<[UseSSSE3]>;
624 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
625 list<dag> pattern, InstrItinClass itin = NoItinerary>
626 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
627 Requires<[UseSSSE3]>;
628 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
629 list<dag> pattern, InstrItinClass itin = NoItinerary>
630 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
631 Requires<[HasSSSE3]>;
632 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
633 list<dag> pattern, InstrItinClass itin = NoItinerary>
634 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
635 Requires<[HasSSSE3]>;
637 // SSE4.1 Instruction Templates:
639 // SS48I - SSE 4.1 instructions with T8 prefix.
640 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
642 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
643 list<dag> pattern, InstrItinClass itin = NoItinerary>
644 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
645 Requires<[UseSSE41]>;
646 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
647 list<dag> pattern, InstrItinClass itin = NoItinerary>
648 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
649 Requires<[UseSSE41]>;
651 // SSE4.2 Instruction Templates:
653 // SS428I - SSE 4.2 instructions with T8 prefix.
654 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
655 list<dag> pattern, InstrItinClass itin = NoItinerary>
656 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
657 Requires<[UseSSE42]>;
659 // SS42FI - SSE 4.2 instructions with T8XD prefix.
660 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
661 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
662 list<dag> pattern, InstrItinClass itin = NoItinerary>
663 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
665 // SS42AI = SSE 4.2 instructions with TA prefix
666 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
667 list<dag> pattern, InstrItinClass itin = NoItinerary>
668 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
669 Requires<[UseSSE42]>;
671 // AVX Instruction Templates:
672 // Instructions introduced in AVX (no SSE equivalent forms)
674 // AVX8I - AVX instructions with T8PD prefix.
675 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
676 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
677 list<dag> pattern, InstrItinClass itin = NoItinerary>
678 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
680 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag> pattern, InstrItinClass itin = NoItinerary>
682 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
685 // AVX2 Instruction Templates:
686 // Instructions introduced in AVX2 (no SSE equivalent forms)
688 // AVX28I - AVX2 instructions with T8PD prefix.
689 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
690 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
691 list<dag> pattern, InstrItinClass itin = NoItinerary>
692 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
694 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
695 list<dag> pattern, InstrItinClass itin = NoItinerary>
696 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
700 // AVX-512 Instruction Templates:
701 // Instructions introduced in AVX-512 (no SSE equivalent forms)
703 // AVX5128I - AVX-512 instructions with T8PD prefix.
704 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
705 // AVX512PDI - AVX-512 instructions with PD, double packed.
706 // AVX512PSI - AVX-512 instructions with PS, single packed.
707 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
708 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
709 // AVX512BI - AVX-512 instructions with PD, int packed domain.
710 // AVX512SI - AVX-512 scalar instructions with PD prefix.
712 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
713 list<dag> pattern, InstrItinClass itin = NoItinerary>
714 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
715 Requires<[HasAVX512]>;
716 class AVX5128IBase : T8PD {
717 Domain ExeDomain = SSEPackedInt;
719 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
720 list<dag> pattern, InstrItinClass itin = NoItinerary>
721 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
722 Requires<[HasAVX512]>;
723 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
724 list<dag> pattern, InstrItinClass itin = NoItinerary>
725 : I<o, F, outs, ins, asm, pattern, itin>, XS,
726 Requires<[HasAVX512]>;
727 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
728 list<dag> pattern, InstrItinClass itin = NoItinerary>
729 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
730 Requires<[HasAVX512]>;
731 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
732 list<dag> pattern, InstrItinClass itin = NoItinerary>
733 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
734 Requires<[HasAVX512]>;
735 class AVX512BIBase : PD {
736 Domain ExeDomain = SSEPackedInt;
738 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
739 list<dag> pattern, InstrItinClass itin = NoItinerary>
740 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
741 Requires<[HasAVX512]>;
742 class AVX512BIi8Base : PD {
743 Domain ExeDomain = SSEPackedInt;
746 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
747 list<dag> pattern, InstrItinClass itin = NoItinerary>
748 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
749 Requires<[HasAVX512]>;
750 class AVX512AIi8Base : TAPD {
751 Domain ExeDomain = SSEPackedInt;
754 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
755 list<dag> pattern, InstrItinClass itin = NoItinerary>
756 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
757 Requires<[HasAVX512]>;
758 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
759 list<dag> pattern, InstrItinClass itin = NoItinerary>
760 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
761 Requires<[HasAVX512]>;
762 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
763 list<dag> pattern, InstrItinClass itin = NoItinerary>
764 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
765 Requires<[HasAVX512]>;
766 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
767 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
768 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
769 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
770 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
771 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
772 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
773 list<dag>pattern, InstrItinClass itin = NoItinerary>
774 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
775 EVEX_4V, Requires<[HasAVX512]>;
776 class AVX512FMA3Base : T8PD, EVEX_4V;
778 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
779 list<dag>pattern, InstrItinClass itin = NoItinerary>
780 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>;
782 // AES Instruction Templates:
785 // These use the same encoding as the SSE4.2 T8 and TA encodings.
786 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
787 list<dag>pattern, InstrItinClass itin = IIC_AES>
788 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
791 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
792 list<dag> pattern, InstrItinClass itin = NoItinerary>
793 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
796 // PCLMUL Instruction Templates
797 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
798 list<dag>pattern, InstrItinClass itin = NoItinerary>
799 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
800 Requires<[HasPCLMUL]>;
802 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
803 list<dag>pattern, InstrItinClass itin = NoItinerary>
804 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
805 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
807 // FMA3 Instruction Templates
808 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
809 list<dag>pattern, InstrItinClass itin = NoItinerary>
810 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
811 VEX_4V, FMASC, Requires<[HasFMA]>;
813 // FMA4 Instruction Templates
814 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
815 list<dag>pattern, InstrItinClass itin = NoItinerary>
816 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
817 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
819 // XOP 2, 3 and 4 Operand Instruction Template
820 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
821 list<dag> pattern, InstrItinClass itin = NoItinerary>
822 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
823 XOP9, Requires<[HasXOP]>;
825 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
826 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
827 list<dag> pattern, InstrItinClass itin = NoItinerary>
828 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
829 XOP8, Requires<[HasXOP]>;
831 // XOP 5 operand instruction (VEX encoding!)
832 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
833 list<dag>pattern, InstrItinClass itin = NoItinerary>
834 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
835 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
837 // X86-64 Instruction templates...
840 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
841 list<dag> pattern, InstrItinClass itin = NoItinerary>
842 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
843 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
844 list<dag> pattern, InstrItinClass itin = NoItinerary>
845 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
846 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
847 list<dag> pattern, InstrItinClass itin = NoItinerary>
848 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
849 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
850 list<dag> pattern, InstrItinClass itin = NoItinerary>
851 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
852 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
853 list<dag> pattern, InstrItinClass itin = NoItinerary>
854 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
856 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
857 list<dag> pattern, InstrItinClass itin = NoItinerary>
858 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
859 let Pattern = pattern;
863 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
864 list<dag> pattern, InstrItinClass itin = NoItinerary>
865 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
866 let Pattern = pattern;
870 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
871 list<dag> pattern, InstrItinClass itin = NoItinerary>
872 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
873 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
874 list<dag> pattern, InstrItinClass itin = NoItinerary>
875 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
877 // MMX Instruction templates
880 // MMXI - MMX instructions with TB prefix.
881 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
882 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
883 // MMX2I - MMX / SSE2 instructions with PD prefix.
884 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
885 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
886 // MMXID - MMX instructions with XD prefix.
887 // MMXIS - MMX instructions with XS prefix.
888 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
889 list<dag> pattern, InstrItinClass itin = NoItinerary>
890 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
891 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
892 list<dag> pattern, InstrItinClass itin = NoItinerary>
893 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
894 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
895 list<dag> pattern, InstrItinClass itin = NoItinerary>
896 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
897 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
898 list<dag> pattern, InstrItinClass itin = NoItinerary>
899 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
900 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
901 list<dag> pattern, InstrItinClass itin = NoItinerary>
902 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
903 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
904 list<dag> pattern, InstrItinClass itin = NoItinerary>
905 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
906 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
907 list<dag> pattern, InstrItinClass itin = NoItinerary>
908 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
909 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
910 list<dag> pattern, InstrItinClass itin = NoItinerary>
911 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;