1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def RawFrmImm8 : Format<11>;
28 def RawFrmImm16 : Format<12>;
29 def MRMXr : Format<14>; def MRMXm : Format<15>;
30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
32 def MRM6r : Format<22>; def MRM7r : Format<23>;
33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
35 def MRM6m : Format<30>; def MRM7m : Format<31>;
36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
39 def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>;
40 def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>;
41 def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>;
42 def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>;
43 def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>;
44 def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>;
45 def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>;
46 def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>;
47 def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>;
48 def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>;
49 def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>;
50 def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>;
51 def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>;
52 def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>;
53 def MRM_FE : Format<83>; def MRM_FF : Format<84>;
55 // ImmType - This specifies the immediate type used by an instruction. This is
56 // part of the ad-hoc solution used to emit machine instruction encodings by our
57 // machine code emitter.
58 class ImmType<bits<4> val> {
61 def NoImm : ImmType<0>;
62 def Imm8 : ImmType<1>;
63 def Imm8PCRel : ImmType<2>;
64 def Imm16 : ImmType<3>;
65 def Imm16PCRel : ImmType<4>;
66 def Imm32 : ImmType<5>;
67 def Imm32PCRel : ImmType<6>;
68 def Imm32S : ImmType<7>;
69 def Imm64 : ImmType<8>;
71 // FPFormat - This specifies what form this FP instruction has. This is used by
72 // the Floating-Point stackifier pass.
73 class FPFormat<bits<3> val> {
76 def NotFP : FPFormat<0>;
77 def ZeroArgFP : FPFormat<1>;
78 def OneArgFP : FPFormat<2>;
79 def OneArgFPRW : FPFormat<3>;
80 def TwoArgFP : FPFormat<4>;
81 def CompareFP : FPFormat<5>;
82 def CondMovFP : FPFormat<6>;
83 def SpecialFP : FPFormat<7>;
85 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
86 // Keep in sync with tables in X86InstrInfo.cpp.
87 class Domain<bits<2> val> {
90 def GenericDomain : Domain<0>;
91 def SSEPackedSingle : Domain<1>;
92 def SSEPackedDouble : Domain<2>;
93 def SSEPackedInt : Domain<3>;
95 // Class specifying the vector form of the decompressed
96 // displacement of 8-bit.
97 class CD8VForm<bits<3> val> {
100 def CD8VF : CD8VForm<0>; // v := VL
101 def CD8VH : CD8VForm<1>; // v := VL/2
102 def CD8VQ : CD8VForm<2>; // v := VL/4
103 def CD8VO : CD8VForm<3>; // v := VL/8
104 // The tuple (subvector) forms.
105 def CD8VT1 : CD8VForm<4>; // v := 1
106 def CD8VT2 : CD8VForm<5>; // v := 2
107 def CD8VT4 : CD8VForm<6>; // v := 4
108 def CD8VT8 : CD8VForm<7>; // v := 8
110 // Class specifying the prefix used an opcode extension.
111 class Prefix<bits<3> val> {
114 def NoPrfx : Prefix<0>;
120 // Class specifying the opcode map.
121 class Map<bits<3> val> {
132 // Class specifying the encoding
133 class Encoding<bits<2> val> {
136 def EncNormal : Encoding<0>;
137 def EncVEX : Encoding<1>;
138 def EncXOP : Encoding<2>;
139 def EncEVEX : Encoding<3>;
141 // Operand size for encodings that change based on mode.
142 class OperandSize<bits<2> val> {
145 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
146 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
147 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
149 // Prefix byte classes which are used to indicate to the ad-hoc machine code
150 // emitter that various prefix bytes are required.
151 class OpSize16 { OperandSize OpSize = OpSize16; }
152 class OpSize32 { OperandSize OpSize = OpSize32; }
153 class AdSize { bit hasAdSizePrefix = 1; }
154 class REX_W { bit hasREX_WPrefix = 1; }
155 class LOCK { bit hasLockPrefix = 1; }
156 class REP { bit hasREPPrefix = 1; }
157 class TB { Map OpMap = TB; }
158 class T8 { Map OpMap = T8; }
159 class TA { Map OpMap = TA; }
160 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
161 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
162 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
163 class OBXS { Prefix OpPrefix = XS; }
164 class PS : TB { Prefix OpPrefix = PS; }
165 class PD : TB { Prefix OpPrefix = PD; }
166 class XD : TB { Prefix OpPrefix = XD; }
167 class XS : TB { Prefix OpPrefix = XS; }
168 class T8PS : T8 { Prefix OpPrefix = PS; }
169 class T8PD : T8 { Prefix OpPrefix = PD; }
170 class T8XD : T8 { Prefix OpPrefix = XD; }
171 class T8XS : T8 { Prefix OpPrefix = XS; }
172 class TAPS : TA { Prefix OpPrefix = PS; }
173 class TAPD : TA { Prefix OpPrefix = PD; }
174 class TAXD : TA { Prefix OpPrefix = XD; }
175 class VEX { Encoding OpEnc = EncVEX; }
176 class VEX_W { bit hasVEX_WPrefix = 1; }
177 class VEX_4V : VEX { bit hasVEX_4V = 1; }
178 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; }
179 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
180 class VEX_L { bit hasVEX_L = 1; }
181 class VEX_LIG { bit ignoresVEX_L = 1; }
182 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
183 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
184 class EVEX_K { bit hasEVEX_K = 1; }
185 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
186 class EVEX_B { bit hasEVEX_B = 1; }
187 class EVEX_RC { bit hasEVEX_RC = 1; }
188 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
189 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }
190 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }
192 // Specify AVX512 8-bit compressed displacement encoding based on the vector
193 // element size in bits (8, 16, 32, 64) and the CDisp8 form.
194 class EVEX_CD8<int esize, CD8VForm form> {
195 int CD8_EltSize = !srl(esize, 3);
196 bits<3> CD8_Form = form.Value;
199 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
200 class MemOp4 { bit hasMemOp4Prefix = 1; }
201 class XOP { Encoding OpEnc = EncXOP; }
202 class XOP_4V : XOP { bit hasVEX_4V = 1; }
203 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; }
205 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
208 Domain d = GenericDomain>
210 let Namespace = "X86";
212 bits<8> Opcode = opcod;
214 bits<7> FormBits = Form.Value;
217 dag OutOperandList = outs;
218 dag InOperandList = ins;
219 string AsmString = AsmStr;
221 // If this is a pseudo instruction, mark it isCodeGenOnly.
222 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
224 let Itinerary = itin;
227 // Attributes specific to X86 instructions...
229 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
230 // isCodeGenonly. Needed to hide an ambiguous
231 // AsmString from the parser, but still disassemble.
233 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
234 // based on operand size of the mode
235 bits<2> OpSizeBits = OpSize.Value;
236 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
238 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
239 bits<3> OpPrefixBits = OpPrefix.Value;
240 Map OpMap = OB; // Which opcode map does this inst have?
241 bits<3> OpMapBits = OpMap.Value;
242 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
243 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
244 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
245 Domain ExeDomain = d;
246 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
247 Encoding OpEnc = EncNormal; // Encoding used by this instruction
248 bits<2> OpEncBits = OpEnc.Value;
249 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
250 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
251 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to
252 // encode the third operand?
253 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
254 // to be encoded in a immediate field?
255 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
256 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
257 bit hasEVEX_K = 0; // Does this inst require masking?
258 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
259 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
260 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
261 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
262 // Declare it int rather than bits<4> so that all bits are defined when
263 // assigning to bits<7>.
264 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
265 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
266 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
267 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
270 let EVEX_LL{0} = hasVEX_L;
271 let EVEX_LL{1} = hasEVEX_L2;
272 // Vector size in bytes.
273 bits<7> VectSize = !shl(16, EVEX_LL);
275 // The scaling factor for AVX512's compressed displacement is either
276 // - the size of a power-of-two number of elements or
277 // - the size of a single element for broadcasts or
278 // - the total vector size divided by a power-of-two number.
279 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
280 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
282 !shl(CD8_EltSize, CD8_Form{1-0}),
285 !srl(VectSize, CD8_Form{1-0}))), 0);
287 // TSFlags layout should be kept in sync with X86InstrInfo.h.
288 let TSFlags{6-0} = FormBits;
289 let TSFlags{8-7} = OpSizeBits;
290 let TSFlags{9} = hasAdSizePrefix;
291 let TSFlags{12-10} = OpPrefixBits;
292 let TSFlags{15-13} = OpMapBits;
293 let TSFlags{16} = hasREX_WPrefix;
294 let TSFlags{20-17} = ImmT.Value;
295 let TSFlags{23-21} = FPForm.Value;
296 let TSFlags{24} = hasLockPrefix;
297 let TSFlags{25} = hasREPPrefix;
298 let TSFlags{27-26} = ExeDomain.Value;
299 let TSFlags{29-28} = OpEncBits;
300 let TSFlags{37-30} = Opcode;
301 let TSFlags{38} = hasVEX_WPrefix;
302 let TSFlags{39} = hasVEX_4V;
303 let TSFlags{40} = hasVEX_4VOp3;
304 let TSFlags{41} = hasVEX_i8ImmReg;
305 let TSFlags{42} = hasVEX_L;
306 let TSFlags{43} = ignoresVEX_L;
307 let TSFlags{44} = hasEVEX_K;
308 let TSFlags{45} = hasEVEX_Z;
309 let TSFlags{46} = hasEVEX_L2;
310 let TSFlags{47} = hasEVEX_B;
311 // If we run out of TSFlags bits, it's possible to encode this in 3 bits.
312 let TSFlags{54-48} = CD8_Scale;
313 let TSFlags{55} = has3DNow0F0FOpcode;
314 let TSFlags{56} = hasMemOp4Prefix;
315 let TSFlags{57} = hasEVEX_RC;
318 class PseudoI<dag oops, dag iops, list<dag> pattern>
319 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
320 let Pattern = pattern;
323 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
324 list<dag> pattern, InstrItinClass itin = NoItinerary,
325 Domain d = GenericDomain>
326 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
327 let Pattern = pattern;
330 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
331 list<dag> pattern, InstrItinClass itin = NoItinerary,
332 Domain d = GenericDomain>
333 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
334 let Pattern = pattern;
337 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
338 list<dag> pattern, InstrItinClass itin = NoItinerary>
339 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
340 let Pattern = pattern;
343 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
344 list<dag> pattern, InstrItinClass itin = NoItinerary>
345 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
346 let Pattern = pattern;
349 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
350 list<dag> pattern, InstrItinClass itin = NoItinerary>
351 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
352 let Pattern = pattern;
355 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
356 list<dag> pattern, InstrItinClass itin = NoItinerary>
357 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
358 let Pattern = pattern;
362 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
363 list<dag> pattern, InstrItinClass itin = NoItinerary>
364 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
365 let Pattern = pattern;
369 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
370 list<dag> pattern, InstrItinClass itin = NoItinerary>
371 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
372 let Pattern = pattern;
376 // FPStack Instruction Templates:
377 // FPI - Floating Point Instruction template.
378 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
379 InstrItinClass itin = NoItinerary>
380 : I<o, F, outs, ins, asm, [], itin> {}
382 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
383 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
384 InstrItinClass itin = NoItinerary>
385 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
387 let Pattern = pattern;
390 // Templates for instructions that use a 16- or 32-bit segmented address as
391 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
393 // Iseg16 - 16-bit segment selector, 16-bit offset
394 // Iseg32 - 16-bit segment selector, 32-bit offset
396 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
397 list<dag> pattern, InstrItinClass itin = NoItinerary>
398 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
399 let Pattern = pattern;
403 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
404 list<dag> pattern, InstrItinClass itin = NoItinerary>
405 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
406 let Pattern = pattern;
410 // SI - SSE 1 & 2 scalar instructions
411 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
412 list<dag> pattern, InstrItinClass itin = NoItinerary>
413 : I<o, F, outs, ins, asm, pattern, itin> {
414 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
415 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
416 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
417 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
418 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
421 // AVX instructions have a 'v' prefix in the mnemonic
422 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
423 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
427 // SIi8 - SSE 1 & 2 scalar instructions
428 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
429 list<dag> pattern, InstrItinClass itin = NoItinerary>
430 : Ii8<o, F, outs, ins, asm, pattern, itin> {
431 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
432 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
433 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
436 // AVX instructions have a 'v' prefix in the mnemonic
437 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
438 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
442 // PI - SSE 1 & 2 packed instructions
443 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
444 InstrItinClass itin, Domain d>
445 : I<o, F, outs, ins, asm, pattern, itin, d> {
446 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
447 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
448 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
451 // AVX instructions have a 'v' prefix in the mnemonic
452 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
453 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
457 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
458 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
459 InstrItinClass itin, Domain d>
460 : I<o, F, outs, ins, asm, pattern, itin, d> {
461 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
465 // PIi8 - SSE 1 & 2 packed instructions with immediate
466 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
467 list<dag> pattern, InstrItinClass itin, Domain d>
468 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
469 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
470 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
471 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
474 // AVX instructions have a 'v' prefix in the mnemonic
475 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
476 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
480 // SSE1 Instruction Templates:
482 // SSI - SSE1 instructions with XS prefix.
483 // PSI - SSE1 instructions with PS prefix.
484 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
485 // VSSI - SSE1 instructions with XS prefix in AVX form.
486 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
488 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
489 list<dag> pattern, InstrItinClass itin = NoItinerary>
490 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
491 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
492 list<dag> pattern, InstrItinClass itin = NoItinerary>
493 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
494 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
495 list<dag> pattern, InstrItinClass itin = NoItinerary>
496 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
498 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
499 list<dag> pattern, InstrItinClass itin = NoItinerary>
500 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
502 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
506 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = NoItinerary>
508 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
511 // SSE2 Instruction Templates:
513 // SDI - SSE2 instructions with XD prefix.
514 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
515 // S2SI - SSE2 instructions with XS prefix.
516 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
517 // PDI - SSE2 instructions with PD prefix, packed double domain.
518 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
519 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
520 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
521 // packed double domain.
522 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
523 // S2I - SSE2 scalar instructions with PD prefix.
524 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
526 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
529 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
530 list<dag> pattern, InstrItinClass itin = NoItinerary>
531 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
532 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
533 list<dag> pattern, InstrItinClass itin = NoItinerary>
534 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
535 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
536 list<dag> pattern, InstrItinClass itin = NoItinerary>
537 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
538 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
539 list<dag> pattern, InstrItinClass itin = NoItinerary>
540 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
541 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
542 list<dag> pattern, InstrItinClass itin = NoItinerary>
543 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
545 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
546 list<dag> pattern, InstrItinClass itin = NoItinerary>
547 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
549 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
550 list<dag> pattern, InstrItinClass itin = NoItinerary>
551 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
553 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
554 list<dag> pattern, InstrItinClass itin = NoItinerary>
555 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
557 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
558 list<dag> pattern, InstrItinClass itin = NoItinerary>
559 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
560 PD, Requires<[HasAVX]>;
561 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
562 list<dag> pattern, InstrItinClass itin = NoItinerary>
563 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
565 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
566 list<dag> pattern, InstrItinClass itin = NoItinerary>
567 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
568 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
569 list<dag> pattern, InstrItinClass itin = NoItinerary>
570 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
571 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
572 list<dag> pattern, InstrItinClass itin = NoItinerary>
573 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
575 // SSE3 Instruction Templates:
577 // S3I - SSE3 instructions with PD prefixes.
578 // S3SI - SSE3 instructions with XS prefix.
579 // S3DI - SSE3 instructions with XD prefix.
581 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
582 list<dag> pattern, InstrItinClass itin = NoItinerary>
583 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
585 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
586 list<dag> pattern, InstrItinClass itin = NoItinerary>
587 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
589 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
590 list<dag> pattern, InstrItinClass itin = NoItinerary>
591 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
595 // SSSE3 Instruction Templates:
597 // SS38I - SSSE3 instructions with T8 prefix.
598 // SS3AI - SSSE3 instructions with TA prefix.
599 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
600 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
602 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
603 // uses the MMX registers. The 64-bit versions are grouped with the MMX
604 // classes. They need to be enabled even if AVX is enabled.
606 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
607 list<dag> pattern, InstrItinClass itin = NoItinerary>
608 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
609 Requires<[UseSSSE3]>;
610 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
611 list<dag> pattern, InstrItinClass itin = NoItinerary>
612 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
613 Requires<[UseSSSE3]>;
614 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
615 list<dag> pattern, InstrItinClass itin = NoItinerary>
616 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
617 Requires<[HasSSSE3]>;
618 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
619 list<dag> pattern, InstrItinClass itin = NoItinerary>
620 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
621 Requires<[HasSSSE3]>;
623 // SSE4.1 Instruction Templates:
625 // SS48I - SSE 4.1 instructions with T8 prefix.
626 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
628 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
629 list<dag> pattern, InstrItinClass itin = NoItinerary>
630 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
631 Requires<[UseSSE41]>;
632 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
633 list<dag> pattern, InstrItinClass itin = NoItinerary>
634 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
635 Requires<[UseSSE41]>;
637 // SSE4.2 Instruction Templates:
639 // SS428I - SSE 4.2 instructions with T8 prefix.
640 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
641 list<dag> pattern, InstrItinClass itin = NoItinerary>
642 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
643 Requires<[UseSSE42]>;
645 // SS42FI - SSE 4.2 instructions with T8XD prefix.
646 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
647 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
648 list<dag> pattern, InstrItinClass itin = NoItinerary>
649 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
651 // SS42AI = SSE 4.2 instructions with TA prefix
652 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
653 list<dag> pattern, InstrItinClass itin = NoItinerary>
654 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
655 Requires<[UseSSE42]>;
657 // AVX Instruction Templates:
658 // Instructions introduced in AVX (no SSE equivalent forms)
660 // AVX8I - AVX instructions with T8PD prefix.
661 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
662 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
663 list<dag> pattern, InstrItinClass itin = NoItinerary>
664 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
666 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
667 list<dag> pattern, InstrItinClass itin = NoItinerary>
668 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
671 // AVX2 Instruction Templates:
672 // Instructions introduced in AVX2 (no SSE equivalent forms)
674 // AVX28I - AVX2 instructions with T8PD prefix.
675 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
676 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
677 list<dag> pattern, InstrItinClass itin = NoItinerary>
678 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
680 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag> pattern, InstrItinClass itin = NoItinerary>
682 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
686 // AVX-512 Instruction Templates:
687 // Instructions introduced in AVX-512 (no SSE equivalent forms)
689 // AVX5128I - AVX-512 instructions with T8PD prefix.
690 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
691 // AVX512PDI - AVX-512 instructions with PD, double packed.
692 // AVX512PSI - AVX-512 instructions with PS, single packed.
693 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
694 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
695 // AVX512BI - AVX-512 instructions with PD, int packed domain.
696 // AVX512SI - AVX-512 scalar instructions with PD prefix.
698 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
699 list<dag> pattern, InstrItinClass itin = NoItinerary>
700 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
701 Requires<[HasAVX512]>;
702 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
703 list<dag> pattern, InstrItinClass itin = NoItinerary>
704 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
705 Requires<[HasAVX512]>;
706 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
707 list<dag> pattern, InstrItinClass itin = NoItinerary>
708 : I<o, F, outs, ins, asm, pattern, itin>, XS,
709 Requires<[HasAVX512]>;
710 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
711 list<dag> pattern, InstrItinClass itin = NoItinerary>
712 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
713 Requires<[HasAVX512]>;
714 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
715 list<dag> pattern, InstrItinClass itin = NoItinerary>
716 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
717 Requires<[HasAVX512]>;
718 class AVX512BIBase : PD {
719 Domain ExeDomain = SSEPackedInt;
721 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
722 list<dag> pattern, InstrItinClass itin = NoItinerary>
723 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
724 Requires<[HasAVX512]>;
725 class AVX512BIi8Base : PD {
726 Domain ExeDomain = SSEPackedInt;
729 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
730 list<dag> pattern, InstrItinClass itin = NoItinerary>
731 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
732 Requires<[HasAVX512]>;
733 class AVX512AIi8Base : TAPD {
734 Domain ExeDomain = SSEPackedInt;
737 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
738 list<dag> pattern, InstrItinClass itin = NoItinerary>
739 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
740 Requires<[HasAVX512]>;
741 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
742 list<dag> pattern, InstrItinClass itin = NoItinerary>
743 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
744 Requires<[HasAVX512]>;
745 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
746 list<dag> pattern, InstrItinClass itin = NoItinerary>
747 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
748 Requires<[HasAVX512]>;
749 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
750 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
751 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
752 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
753 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
754 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
755 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
756 list<dag>pattern, InstrItinClass itin = NoItinerary>
757 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
758 EVEX_4V, Requires<[HasAVX512]>;
759 class AVX512FMA3Base : T8PD, EVEX_4V;
761 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
762 list<dag>pattern, InstrItinClass itin = NoItinerary>
763 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>;
765 // AES Instruction Templates:
768 // These use the same encoding as the SSE4.2 T8 and TA encodings.
769 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
770 list<dag>pattern, InstrItinClass itin = IIC_AES>
771 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
774 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
775 list<dag> pattern, InstrItinClass itin = NoItinerary>
776 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
779 // PCLMUL Instruction Templates
780 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
781 list<dag>pattern, InstrItinClass itin = NoItinerary>
782 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
783 Requires<[HasPCLMUL]>;
785 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
786 list<dag>pattern, InstrItinClass itin = NoItinerary>
787 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
788 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
790 // FMA3 Instruction Templates
791 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
792 list<dag>pattern, InstrItinClass itin = NoItinerary>
793 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
794 VEX_4V, FMASC, Requires<[HasFMA]>;
796 // FMA4 Instruction Templates
797 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
798 list<dag>pattern, InstrItinClass itin = NoItinerary>
799 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
800 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
802 // XOP 2, 3 and 4 Operand Instruction Template
803 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
804 list<dag> pattern, InstrItinClass itin = NoItinerary>
805 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
806 XOP9, Requires<[HasXOP]>;
808 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
809 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
810 list<dag> pattern, InstrItinClass itin = NoItinerary>
811 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
812 XOP8, Requires<[HasXOP]>;
814 // XOP 5 operand instruction (VEX encoding!)
815 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
816 list<dag>pattern, InstrItinClass itin = NoItinerary>
817 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
818 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
820 // X86-64 Instruction templates...
823 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
824 list<dag> pattern, InstrItinClass itin = NoItinerary>
825 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
826 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
827 list<dag> pattern, InstrItinClass itin = NoItinerary>
828 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
829 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
830 list<dag> pattern, InstrItinClass itin = NoItinerary>
831 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
832 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
833 list<dag> pattern, InstrItinClass itin = NoItinerary>
834 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
835 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
836 list<dag> pattern, InstrItinClass itin = NoItinerary>
837 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
839 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
840 list<dag> pattern, InstrItinClass itin = NoItinerary>
841 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
842 let Pattern = pattern;
846 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
847 list<dag> pattern, InstrItinClass itin = NoItinerary>
848 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
849 let Pattern = pattern;
853 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
854 list<dag> pattern, InstrItinClass itin = NoItinerary>
855 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
856 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
857 list<dag> pattern, InstrItinClass itin = NoItinerary>
858 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
860 // MMX Instruction templates
863 // MMXI - MMX instructions with TB prefix.
864 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
865 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
866 // MMX2I - MMX / SSE2 instructions with PD prefix.
867 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
868 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
869 // MMXID - MMX instructions with XD prefix.
870 // MMXIS - MMX instructions with XS prefix.
871 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
872 list<dag> pattern, InstrItinClass itin = NoItinerary>
873 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
874 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
875 list<dag> pattern, InstrItinClass itin = NoItinerary>
876 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
877 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
878 list<dag> pattern, InstrItinClass itin = NoItinerary>
879 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
880 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
881 list<dag> pattern, InstrItinClass itin = NoItinerary>
882 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
883 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
884 list<dag> pattern, InstrItinClass itin = NoItinerary>
885 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
886 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
887 list<dag> pattern, InstrItinClass itin = NoItinerary>
888 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
889 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
890 list<dag> pattern, InstrItinClass itin = NoItinerary>
891 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
892 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
893 list<dag> pattern, InstrItinClass itin = NoItinerary>
894 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;