1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
33 def MRM_C1 : Format<33>;
34 def MRM_C2 : Format<34>;
35 def MRM_C3 : Format<35>;
36 def MRM_C4 : Format<36>;
37 def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>;
39 def MRM_CA : Format<39>;
40 def MRM_CB : Format<40>;
41 def MRM_E8 : Format<41>;
42 def MRM_F0 : Format<42>;
43 def RawFrmImm8 : Format<43>;
44 def RawFrmImm16 : Format<44>;
45 def MRM_F8 : Format<45>;
46 def MRM_F9 : Format<46>;
47 def MRM_D0 : Format<47>;
48 def MRM_D1 : Format<48>;
49 def MRM_D4 : Format<49>;
50 def MRM_D5 : Format<50>;
51 def MRM_D6 : Format<51>;
52 def MRM_D8 : Format<52>;
53 def MRM_D9 : Format<53>;
54 def MRM_DA : Format<54>;
55 def MRM_DB : Format<55>;
56 def MRM_DC : Format<56>;
57 def MRM_DD : Format<57>;
58 def MRM_DE : Format<58>;
59 def MRM_DF : Format<59>;
61 // ImmType - This specifies the immediate type used by an instruction. This is
62 // part of the ad-hoc solution used to emit machine instruction encodings by our
63 // machine code emitter.
64 class ImmType<bits<4> val> {
67 def NoImm : ImmType<0>;
68 def Imm8 : ImmType<1>;
69 def Imm8PCRel : ImmType<2>;
70 def Imm16 : ImmType<3>;
71 def Imm16PCRel : ImmType<4>;
72 def Imm32 : ImmType<5>;
73 def Imm32PCRel : ImmType<6>;
74 def Imm32S : ImmType<7>;
75 def Imm64 : ImmType<8>;
77 // FPFormat - This specifies what form this FP instruction has. This is used by
78 // the Floating-Point stackifier pass.
79 class FPFormat<bits<3> val> {
82 def NotFP : FPFormat<0>;
83 def ZeroArgFP : FPFormat<1>;
84 def OneArgFP : FPFormat<2>;
85 def OneArgFPRW : FPFormat<3>;
86 def TwoArgFP : FPFormat<4>;
87 def CompareFP : FPFormat<5>;
88 def CondMovFP : FPFormat<6>;
89 def SpecialFP : FPFormat<7>;
91 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
92 // Keep in sync with tables in X86InstrInfo.cpp.
93 class Domain<bits<2> val> {
96 def GenericDomain : Domain<0>;
97 def SSEPackedSingle : Domain<1>;
98 def SSEPackedDouble : Domain<2>;
99 def SSEPackedInt : Domain<3>;
101 // Class specifying the vector form of the decompressed
102 // displacement of 8-bit.
103 class CD8VForm<bits<3> val> {
106 def CD8VF : CD8VForm<0>; // v := VL
107 def CD8VH : CD8VForm<1>; // v := VL/2
108 def CD8VQ : CD8VForm<2>; // v := VL/4
109 def CD8VO : CD8VForm<3>; // v := VL/8
110 def CD8VT1 : CD8VForm<4>; // v := 1
111 def CD8VT2 : CD8VForm<5>; // v := 2
112 def CD8VT4 : CD8VForm<6>; // v := 4
113 def CD8VT8 : CD8VForm<7>; // v := 8
115 // Class specifying the prefix used an opcode extension.
116 class Prefix<bits<2> val> {
119 def NoPrfx : Prefix<0>;
124 // Class specifying the opcode map.
125 class Map<bits<5> val> {
146 // Prefix byte classes which are used to indicate to the ad-hoc machine code
147 // emitter that various prefix bytes are required.
148 class OpSize { bit hasOpSizePrefix = 1; }
149 class OpSize16 { bit hasOpSize16Prefix = 1; }
150 class AdSize { bit hasAdSizePrefix = 1; }
151 class REX_W { bit hasREX_WPrefix = 1; }
152 class LOCK { bit hasLockPrefix = 1; }
153 class REP { bit hasREPPrefix = 1; }
154 class TB { Map OpMap = TB; }
155 class D8 { Map OpMap = D8; }
156 class D9 { Map OpMap = D9; }
157 class DA { Map OpMap = DA; }
158 class DB { Map OpMap = DB; }
159 class DC { Map OpMap = DC; }
160 class DD { Map OpMap = DD; }
161 class DE { Map OpMap = DE; }
162 class DF { Map OpMap = DF; }
163 class T8 { Map OpMap = T8; }
164 class TA { Map OpMap = TA; }
165 class A6 { Map OpMap = A6; }
166 class A7 { Map OpMap = A7; }
167 class XOP8 { Map OpMap = XOP8; }
168 class XOP9 { Map OpMap = XOP9; }
169 class XOPA { Map OpMap = XOPA; }
170 class PD : TB { Prefix OpPrefix = PD; }
171 class XD : TB { Prefix OpPrefix = XD; }
172 class XS : TB { Prefix OpPrefix = XS; }
173 class T8PD : T8 { Prefix OpPrefix = PD; }
174 class T8XD : T8 { Prefix OpPrefix = XD; }
175 class T8XS : T8 { Prefix OpPrefix = XS; }
176 class TAPD : TA { Prefix OpPrefix = PD; }
177 class TAXD : TA { Prefix OpPrefix = XD; }
178 class VEX { bit hasVEXPrefix = 1; }
179 class VEX_W { bit hasVEX_WPrefix = 1; }
180 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
181 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
182 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
183 class VEX_L { bit hasVEX_L = 1; }
184 class VEX_LIG { bit ignoresVEX_L = 1; }
185 class EVEX : VEX { bit hasEVEXPrefix = 1; }
186 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
187 class EVEX_K { bit hasEVEX_K = 1; }
188 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
189 class EVEX_B { bit hasEVEX_B = 1; }
190 class EVEX_RC { bit hasEVEX_RC = 1; }
191 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
192 class EVEX_CD8<int esize, CD8VForm form> {
193 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
194 !if(!eq(esize, 16), 0b01,
195 !if(!eq(esize, 32), 0b10,
196 !if(!eq(esize, 64), 0b11, ?))));
197 bits<3> EVEX_CD8V = form.Value;
199 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
200 class MemOp4 { bit hasMemOp4Prefix = 1; }
201 class XOP { bit hasXOP_Prefix = 1; }
202 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
205 Domain d = GenericDomain>
207 let Namespace = "X86";
209 bits<8> Opcode = opcod;
211 bits<6> FormBits = Form.Value;
214 dag OutOperandList = outs;
215 dag InOperandList = ins;
216 string AsmString = AsmStr;
218 // If this is a pseudo instruction, mark it isCodeGenOnly.
219 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
221 let Itinerary = itin;
224 // Attributes specific to X86 instructions...
226 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
227 // isCodeGenonly. Needed to hide an ambiguous
228 // AsmString from the parser, but still disassemble.
230 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
231 bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
232 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
234 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
235 Map OpMap = OB; // Which opcode map does this inst have?
236 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
237 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
238 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
239 Domain ExeDomain = d;
240 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
241 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
242 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
243 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
244 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
245 // encode the third operand?
246 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
247 // to be encoded in a immediate field?
248 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
249 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
250 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
251 bit hasEVEX_K = 0; // Does this inst require masking?
252 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
253 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
254 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
255 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
256 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
257 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
258 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
259 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
260 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
262 // TSFlags layout should be kept in sync with X86InstrInfo.h.
263 let TSFlags{5-0} = FormBits;
264 let TSFlags{6} = hasOpSizePrefix;
265 let TSFlags{7} = hasOpSize16Prefix;
266 let TSFlags{8} = hasAdSizePrefix;
267 let TSFlags{10-9} = OpPrefix.Value;
268 let TSFlags{15-11} = OpMap.Value;
269 let TSFlags{16} = hasREX_WPrefix;
270 let TSFlags{20-17} = ImmT.Value;
271 let TSFlags{23-21} = FPForm.Value;
272 let TSFlags{24} = hasLockPrefix;
273 let TSFlags{25} = hasREPPrefix;
274 let TSFlags{27-26} = ExeDomain.Value;
275 let TSFlags{35-28} = Opcode;
276 let TSFlags{36} = hasVEXPrefix;
277 let TSFlags{37} = hasVEX_WPrefix;
278 let TSFlags{38} = hasVEX_4VPrefix;
279 let TSFlags{39} = hasVEX_4VOp3Prefix;
280 let TSFlags{40} = hasVEX_i8ImmReg;
281 let TSFlags{41} = hasVEX_L;
282 let TSFlags{42} = ignoresVEX_L;
283 let TSFlags{43} = hasEVEXPrefix;
284 let TSFlags{44} = hasEVEX_K;
285 let TSFlags{45} = hasEVEX_Z;
286 let TSFlags{46} = hasEVEX_L2;
287 let TSFlags{47} = hasEVEX_B;
288 let TSFlags{49-48} = EVEX_CD8E;
289 let TSFlags{52-50} = EVEX_CD8V;
290 let TSFlags{53} = has3DNow0F0FOpcode;
291 let TSFlags{54} = hasMemOp4Prefix;
292 let TSFlags{55} = hasXOP_Prefix;
293 let TSFlags{56} = hasEVEX_RC;
296 class PseudoI<dag oops, dag iops, list<dag> pattern>
297 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
298 let Pattern = pattern;
301 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
302 list<dag> pattern, InstrItinClass itin = NoItinerary,
303 Domain d = GenericDomain>
304 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
305 let Pattern = pattern;
308 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
309 list<dag> pattern, InstrItinClass itin = NoItinerary,
310 Domain d = GenericDomain>
311 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
312 let Pattern = pattern;
315 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
316 list<dag> pattern, InstrItinClass itin = NoItinerary>
317 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
318 let Pattern = pattern;
321 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
322 list<dag> pattern, InstrItinClass itin = NoItinerary>
323 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
324 let Pattern = pattern;
327 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
328 list<dag> pattern, InstrItinClass itin = NoItinerary>
329 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
330 let Pattern = pattern;
333 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
334 list<dag> pattern, InstrItinClass itin = NoItinerary>
335 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
336 let Pattern = pattern;
340 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
341 list<dag> pattern, InstrItinClass itin = NoItinerary>
342 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
343 let Pattern = pattern;
347 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
348 list<dag> pattern, InstrItinClass itin = NoItinerary>
349 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
350 let Pattern = pattern;
354 // FPStack Instruction Templates:
355 // FPI - Floating Point Instruction template.
356 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
357 InstrItinClass itin = NoItinerary>
358 : I<o, F, outs, ins, asm, [], itin> {}
360 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
361 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
362 InstrItinClass itin = NoItinerary>
363 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
365 let Pattern = pattern;
368 // Templates for instructions that use a 16- or 32-bit segmented address as
369 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
371 // Iseg16 - 16-bit segment selector, 16-bit offset
372 // Iseg32 - 16-bit segment selector, 32-bit offset
374 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
375 list<dag> pattern, InstrItinClass itin = NoItinerary>
376 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
377 let Pattern = pattern;
381 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
382 list<dag> pattern, InstrItinClass itin = NoItinerary>
383 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
384 let Pattern = pattern;
392 // SI - SSE 1 & 2 scalar instructions
393 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
394 list<dag> pattern, InstrItinClass itin = NoItinerary>
395 : I<o, F, outs, ins, asm, pattern, itin> {
396 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
397 !if(hasVEXPrefix /* VEX */, [UseAVX],
398 !if(!eq(OpPrefix.Value, __xs.OpPrefix.Value), [UseSSE1],
399 !if(!eq(OpPrefix.Value, __xd.OpPrefix.Value), [UseSSE2],
400 !if(!eq(OpPrefix.Value, __pd.OpPrefix.Value), [UseSSE2],
403 // AVX instructions have a 'v' prefix in the mnemonic
404 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
407 // SIi8 - SSE 1 & 2 scalar instructions
408 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
409 list<dag> pattern, InstrItinClass itin = NoItinerary>
410 : Ii8<o, F, outs, ins, asm, pattern, itin> {
411 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
412 !if(hasVEXPrefix /* VEX */, [UseAVX],
413 !if(!eq(OpPrefix.Value, __xs.OpPrefix.Value), [UseSSE1],
416 // AVX instructions have a 'v' prefix in the mnemonic
417 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
420 // PI - SSE 1 & 2 packed instructions
421 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
422 InstrItinClass itin, Domain d>
423 : I<o, F, outs, ins, asm, pattern, itin, d> {
424 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
425 !if(hasVEXPrefix /* VEX */, [HasAVX],
426 !if(!eq(OpPrefix.Value, __pd.OpPrefix.Value), [UseSSE2],
429 // AVX instructions have a 'v' prefix in the mnemonic
430 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
433 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
434 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
435 InstrItinClass itin, Domain d>
436 : I<o, F, outs, ins, asm, pattern, itin, d> {
437 let Predicates = !if(!eq(OpPrefix.Value, __pd.OpPrefix.Value), [HasSSE2],
441 // PIi8 - SSE 1 & 2 packed instructions with immediate
442 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
443 list<dag> pattern, InstrItinClass itin, Domain d>
444 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
445 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
446 !if(hasVEXPrefix /* VEX */, [HasAVX],
447 !if(!eq(OpPrefix.Value, __pd.OpPrefix.Value), [UseSSE2],
450 // AVX instructions have a 'v' prefix in the mnemonic
451 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
454 // SSE1 Instruction Templates:
456 // SSI - SSE1 instructions with XS prefix.
457 // PSI - SSE1 instructions with TB prefix.
458 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
459 // VSSI - SSE1 instructions with XS prefix in AVX form.
460 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
462 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
463 list<dag> pattern, InstrItinClass itin = NoItinerary>
464 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
465 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = NoItinerary>
467 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
468 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
469 list<dag> pattern, InstrItinClass itin = NoItinerary>
470 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
472 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
473 list<dag> pattern, InstrItinClass itin = NoItinerary>
474 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
476 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
477 list<dag> pattern, InstrItinClass itin = NoItinerary>
478 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
480 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin = NoItinerary>
482 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
485 // SSE2 Instruction Templates:
487 // SDI - SSE2 instructions with XD prefix.
488 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
489 // S2SI - SSE2 instructions with XS prefix.
490 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
491 // PDI - SSE2 instructions with PD prefix, packed double domain.
492 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
493 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
494 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
495 // packed double domain.
496 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
497 // S2I - SSE2 scalar instructions with PD prefix.
498 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
500 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
503 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
504 list<dag> pattern, InstrItinClass itin = NoItinerary>
505 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
506 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = NoItinerary>
508 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
509 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
510 list<dag> pattern, InstrItinClass itin = NoItinerary>
511 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
512 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
513 list<dag> pattern, InstrItinClass itin = NoItinerary>
514 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
515 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
516 list<dag> pattern, InstrItinClass itin = NoItinerary>
517 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
519 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
520 list<dag> pattern, InstrItinClass itin = NoItinerary>
521 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
523 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
524 list<dag> pattern, InstrItinClass itin = NoItinerary>
525 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
527 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
528 list<dag> pattern, InstrItinClass itin = NoItinerary>
529 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
531 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
534 PD, Requires<[HasAVX]>;
535 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
536 list<dag> pattern, InstrItinClass itin = NoItinerary>
537 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
539 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
540 list<dag> pattern, InstrItinClass itin = NoItinerary>
541 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
542 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
543 list<dag> pattern, InstrItinClass itin = NoItinerary>
544 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
545 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
546 list<dag> pattern, InstrItinClass itin = NoItinerary>
547 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
549 // SSE3 Instruction Templates:
551 // S3I - SSE3 instructions with PD prefixes.
552 // S3SI - SSE3 instructions with XS prefix.
553 // S3DI - SSE3 instructions with XD prefix.
555 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
556 list<dag> pattern, InstrItinClass itin = NoItinerary>
557 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
559 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
560 list<dag> pattern, InstrItinClass itin = NoItinerary>
561 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
563 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
564 list<dag> pattern, InstrItinClass itin = NoItinerary>
565 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
569 // SSSE3 Instruction Templates:
571 // SS38I - SSSE3 instructions with T8 prefix.
572 // SS3AI - SSSE3 instructions with TA prefix.
573 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
574 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
576 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
577 // uses the MMX registers. The 64-bit versions are grouped with the MMX
578 // classes. They need to be enabled even if AVX is enabled.
580 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
581 list<dag> pattern, InstrItinClass itin = NoItinerary>
582 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
583 Requires<[UseSSSE3]>;
584 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
585 list<dag> pattern, InstrItinClass itin = NoItinerary>
586 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
587 Requires<[UseSSSE3]>;
588 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
589 list<dag> pattern, InstrItinClass itin = NoItinerary>
590 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
591 Requires<[HasSSSE3]>;
592 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
593 list<dag> pattern, InstrItinClass itin = NoItinerary>
594 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
595 Requires<[HasSSSE3]>;
597 // SSE4.1 Instruction Templates:
599 // SS48I - SSE 4.1 instructions with T8 prefix.
600 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
602 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
603 list<dag> pattern, InstrItinClass itin = NoItinerary>
604 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
605 Requires<[UseSSE41]>;
606 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
607 list<dag> pattern, InstrItinClass itin = NoItinerary>
608 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
609 Requires<[UseSSE41]>;
611 // SSE4.2 Instruction Templates:
613 // SS428I - SSE 4.2 instructions with T8 prefix.
614 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
615 list<dag> pattern, InstrItinClass itin = NoItinerary>
616 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
617 Requires<[UseSSE42]>;
619 // SS42FI - SSE 4.2 instructions with T8XD prefix.
620 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
621 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
622 list<dag> pattern, InstrItinClass itin = NoItinerary>
623 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
625 // SS42AI = SSE 4.2 instructions with TA prefix
626 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
627 list<dag> pattern, InstrItinClass itin = NoItinerary>
628 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
629 Requires<[UseSSE42]>;
631 // AVX Instruction Templates:
632 // Instructions introduced in AVX (no SSE equivalent forms)
634 // AVX8I - AVX instructions with T8PD prefix.
635 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
636 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
637 list<dag> pattern, InstrItinClass itin = NoItinerary>
638 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
640 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
641 list<dag> pattern, InstrItinClass itin = NoItinerary>
642 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
645 // AVX2 Instruction Templates:
646 // Instructions introduced in AVX2 (no SSE equivalent forms)
648 // AVX28I - AVX2 instructions with T8PD prefix.
649 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
650 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
651 list<dag> pattern, InstrItinClass itin = NoItinerary>
652 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
654 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
655 list<dag> pattern, InstrItinClass itin = NoItinerary>
656 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
660 // AVX-512 Instruction Templates:
661 // Instructions introduced in AVX-512 (no SSE equivalent forms)
663 // AVX5128I - AVX-512 instructions with T8PD prefix.
664 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
665 // AVX512PDI - AVX-512 instructions with PD, double packed.
666 // AVX512PSI - AVX-512 instructions with TB, single packed.
667 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
668 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
669 // AVX512BI - AVX-512 instructions with PD, int packed domain.
670 // AVX512SI - AVX-512 scalar instructions with PD prefix.
672 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
673 list<dag> pattern, InstrItinClass itin = NoItinerary>
674 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
675 Requires<[HasAVX512]>;
676 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
677 list<dag> pattern, InstrItinClass itin = NoItinerary>
678 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
679 Requires<[HasAVX512]>;
680 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag> pattern, InstrItinClass itin = NoItinerary>
682 : I<o, F, outs, ins, asm, pattern, itin>, XS,
683 Requires<[HasAVX512]>;
684 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
685 list<dag> pattern, InstrItinClass itin = NoItinerary>
686 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
687 Requires<[HasAVX512]>;
688 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
689 list<dag> pattern, InstrItinClass itin = NoItinerary>
690 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
691 Requires<[HasAVX512]>;
692 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
693 list<dag> pattern, InstrItinClass itin = NoItinerary>
694 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
695 Requires<[HasAVX512]>;
696 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
697 list<dag> pattern, InstrItinClass itin = NoItinerary>
698 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
699 Requires<[HasAVX512]>;
700 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
701 list<dag> pattern, InstrItinClass itin = NoItinerary>
702 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
703 Requires<[HasAVX512]>;
704 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
705 list<dag> pattern, InstrItinClass itin = NoItinerary>
706 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
707 Requires<[HasAVX512]>;
708 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
709 list<dag> pattern, InstrItinClass itin = NoItinerary>
710 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
711 Requires<[HasAVX512]>;
712 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
713 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
714 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
715 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
716 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
717 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
718 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
719 list<dag>pattern, InstrItinClass itin = NoItinerary>
720 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
721 EVEX_4V, Requires<[HasAVX512]>;
723 // AES Instruction Templates:
726 // These use the same encoding as the SSE4.2 T8 and TA encodings.
727 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
728 list<dag>pattern, InstrItinClass itin = IIC_AES>
729 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
732 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
733 list<dag> pattern, InstrItinClass itin = NoItinerary>
734 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
737 // PCLMUL Instruction Templates
738 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
739 list<dag>pattern, InstrItinClass itin = NoItinerary>
740 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
741 Requires<[HasPCLMUL]>;
743 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
744 list<dag>pattern, InstrItinClass itin = NoItinerary>
745 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
746 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
748 // FMA3 Instruction Templates
749 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
750 list<dag>pattern, InstrItinClass itin = NoItinerary>
751 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
752 VEX_4V, FMASC, Requires<[HasFMA]>;
754 // FMA4 Instruction Templates
755 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
756 list<dag>pattern, InstrItinClass itin = NoItinerary>
757 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
758 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
760 // XOP 2, 3 and 4 Operand Instruction Template
761 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
762 list<dag> pattern, InstrItinClass itin = NoItinerary>
763 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
764 XOP, XOP9, Requires<[HasXOP]>;
766 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
767 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
768 list<dag> pattern, InstrItinClass itin = NoItinerary>
769 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
770 XOP, XOP8, Requires<[HasXOP]>;
772 // XOP 5 operand instruction (VEX encoding!)
773 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
774 list<dag>pattern, InstrItinClass itin = NoItinerary>
775 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
776 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
778 // X86-64 Instruction templates...
781 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
782 list<dag> pattern, InstrItinClass itin = NoItinerary>
783 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
784 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
785 list<dag> pattern, InstrItinClass itin = NoItinerary>
786 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
787 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
788 list<dag> pattern, InstrItinClass itin = NoItinerary>
789 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
790 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
791 list<dag> pattern, InstrItinClass itin = NoItinerary>
792 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
793 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
794 list<dag> pattern, InstrItinClass itin = NoItinerary>
795 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
797 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
798 list<dag> pattern, InstrItinClass itin = NoItinerary>
799 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
800 let Pattern = pattern;
804 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
805 list<dag> pattern, InstrItinClass itin = NoItinerary>
806 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
807 let Pattern = pattern;
811 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
812 list<dag> pattern, InstrItinClass itin = NoItinerary>
813 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
814 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
815 list<dag> pattern, InstrItinClass itin = NoItinerary>
816 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
817 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
818 list<dag> pattern, InstrItinClass itin = NoItinerary>
819 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
820 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
821 list<dag> pattern, InstrItinClass itin = NoItinerary>
822 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
823 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
824 list<dag> pattern, InstrItinClass itin = NoItinerary>
825 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
826 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
827 list<dag> pattern, InstrItinClass itin = NoItinerary>
828 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
830 // MMX Instruction templates
833 // MMXI - MMX instructions with TB prefix.
834 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
835 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
836 // MMX2I - MMX / SSE2 instructions with PD prefix.
837 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
838 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
839 // MMXID - MMX instructions with XD prefix.
840 // MMXIS - MMX instructions with XS prefix.
841 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
842 list<dag> pattern, InstrItinClass itin = NoItinerary>
843 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
844 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
845 list<dag> pattern, InstrItinClass itin = NoItinerary>
846 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,Not64BitMode]>;
847 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
848 list<dag> pattern, InstrItinClass itin = NoItinerary>
849 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
850 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
851 list<dag> pattern, InstrItinClass itin = NoItinerary>
852 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
853 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
854 list<dag> pattern, InstrItinClass itin = NoItinerary>
855 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
856 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
857 list<dag> pattern, InstrItinClass itin = NoItinerary>
858 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
859 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
860 list<dag> pattern, InstrItinClass itin = NoItinerary>
861 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
862 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
863 list<dag> pattern, InstrItinClass itin = NoItinerary>
864 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;