1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
47 // ImmType - This specifies the immediate type used by an instruction. This is
48 // part of the ad-hoc solution used to emit machine instruction encodings by our
49 // machine code emitter.
50 class ImmType<bits<3> val> {
53 def NoImm : ImmType<0>;
54 def Imm8 : ImmType<1>;
55 def Imm8PCRel : ImmType<2>;
56 def Imm16 : ImmType<3>;
57 def Imm16PCRel : ImmType<4>;
58 def Imm32 : ImmType<5>;
59 def Imm32PCRel : ImmType<6>;
60 def Imm64 : ImmType<7>;
62 // FPFormat - This specifies what form this FP instruction has. This is used by
63 // the Floating-Point stackifier pass.
64 class FPFormat<bits<3> val> {
67 def NotFP : FPFormat<0>;
68 def ZeroArgFP : FPFormat<1>;
69 def OneArgFP : FPFormat<2>;
70 def OneArgFPRW : FPFormat<3>;
71 def TwoArgFP : FPFormat<4>;
72 def CompareFP : FPFormat<5>;
73 def CondMovFP : FPFormat<6>;
74 def SpecialFP : FPFormat<7>;
76 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
77 // Keep in sync with tables in X86InstrInfo.cpp.
78 class Domain<bits<2> val> {
81 def GenericDomain : Domain<0>;
82 def SSEPackedSingle : Domain<1>;
83 def SSEPackedDouble : Domain<2>;
84 def SSEPackedInt : Domain<3>;
86 // Prefix byte classes which are used to indicate to the ad-hoc machine code
87 // emitter that various prefix bytes are required.
88 class OpSize { bit hasOpSizePrefix = 1; }
89 class AdSize { bit hasAdSizePrefix = 1; }
90 class REX_W { bit hasREX_WPrefix = 1; }
91 class LOCK { bit hasLockPrefix = 1; }
92 class SegFS { bits<2> SegOvrBits = 1; }
93 class SegGS { bits<2> SegOvrBits = 2; }
94 class TB { bits<4> Prefix = 1; }
95 class REP { bits<4> Prefix = 2; }
96 class D8 { bits<4> Prefix = 3; }
97 class D9 { bits<4> Prefix = 4; }
98 class DA { bits<4> Prefix = 5; }
99 class DB { bits<4> Prefix = 6; }
100 class DC { bits<4> Prefix = 7; }
101 class DD { bits<4> Prefix = 8; }
102 class DE { bits<4> Prefix = 9; }
103 class DF { bits<4> Prefix = 10; }
104 class XD { bits<4> Prefix = 11; }
105 class XS { bits<4> Prefix = 12; }
106 class T8 { bits<4> Prefix = 13; }
107 class TA { bits<4> Prefix = 14; }
108 class TF { bits<4> Prefix = 15; }
109 class VEX { bit hasVEXPrefix = 1; }
110 class VEX_W { bit hasVEX_WPrefix = 1; }
111 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
112 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
113 class VEX_L { bit hasVEX_L = 1; }
114 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
116 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
117 string AsmStr, Domain d = GenericDomain>
119 let Namespace = "X86";
121 bits<8> Opcode = opcod;
123 bits<6> FormBits = Form.Value;
126 dag OutOperandList = outs;
127 dag InOperandList = ins;
128 string AsmString = AsmStr;
130 // If this is a pseudo instruction, mark it isCodeGenOnly.
131 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
134 // Attributes specific to X86 instructions...
136 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
137 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
139 bits<4> Prefix = 0; // Which prefix byte does this inst have?
140 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
141 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
142 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
143 bits<2> SegOvrBits = 0; // Segment override prefix.
144 Domain ExeDomain = d;
145 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
146 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
147 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
148 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
149 // to be encoded in a immediate field?
150 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
151 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
153 // TSFlags layout should be kept in sync with X86InstrInfo.h.
154 let TSFlags{5-0} = FormBits;
155 let TSFlags{6} = hasOpSizePrefix;
156 let TSFlags{7} = hasAdSizePrefix;
157 let TSFlags{11-8} = Prefix;
158 let TSFlags{12} = hasREX_WPrefix;
159 let TSFlags{15-13} = ImmT.Value;
160 let TSFlags{18-16} = FPForm.Value;
161 let TSFlags{19} = hasLockPrefix;
162 let TSFlags{21-20} = SegOvrBits;
163 let TSFlags{23-22} = ExeDomain.Value;
164 let TSFlags{31-24} = Opcode;
165 let TSFlags{32} = hasVEXPrefix;
166 let TSFlags{33} = hasVEX_WPrefix;
167 let TSFlags{34} = hasVEX_4VPrefix;
168 let TSFlags{35} = hasVEX_i8ImmReg;
169 let TSFlags{36} = hasVEX_L;
170 let TSFlags{37} = has3DNow0F0FOpcode;
173 class PseudoI<dag oops, dag iops, list<dag> pattern>
174 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
175 let Pattern = pattern;
178 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
179 list<dag> pattern, Domain d = GenericDomain>
180 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
181 let Pattern = pattern;
184 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
185 list<dag> pattern, Domain d = GenericDomain>
186 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
187 let Pattern = pattern;
190 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
192 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
193 let Pattern = pattern;
196 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
198 : X86Inst<o, f, Imm16, outs, ins, asm> {
199 let Pattern = pattern;
202 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
204 : X86Inst<o, f, Imm32, outs, ins, asm> {
205 let Pattern = pattern;
209 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
211 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
212 let Pattern = pattern;
216 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
218 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
219 let Pattern = pattern;
223 // FPStack Instruction Templates:
224 // FPI - Floating Point Instruction template.
225 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
226 : I<o, F, outs, ins, asm, []> {}
228 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
229 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
230 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
232 let Pattern = pattern;
235 // Templates for instructions that use a 16- or 32-bit segmented address as
236 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
238 // Iseg16 - 16-bit segment selector, 16-bit offset
239 // Iseg32 - 16-bit segment selector, 32-bit offset
241 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
242 list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
243 let Pattern = pattern;
247 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
248 list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
249 let Pattern = pattern;
253 // SI - SSE 1 & 2 scalar instructions
254 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
255 : I<o, F, outs, ins, asm, pattern> {
256 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
257 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
259 // AVX instructions have a 'v' prefix in the mnemonic
260 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
263 // SIi8 - SSE 1 & 2 scalar instructions
264 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
266 : Ii8<o, F, outs, ins, asm, pattern> {
267 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
268 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
270 // AVX instructions have a 'v' prefix in the mnemonic
271 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
274 // PI - SSE 1 & 2 packed instructions
275 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
277 : I<o, F, outs, ins, asm, pattern, d> {
278 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
279 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
281 // AVX instructions have a 'v' prefix in the mnemonic
282 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
285 // PIi8 - SSE 1 & 2 packed instructions with immediate
286 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
287 list<dag> pattern, Domain d>
288 : Ii8<o, F, outs, ins, asm, pattern, d> {
289 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
290 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
292 // AVX instructions have a 'v' prefix in the mnemonic
293 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
296 // SSE1 Instruction Templates:
298 // SSI - SSE1 instructions with XS prefix.
299 // PSI - SSE1 instructions with TB prefix.
300 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
301 // VSSI - SSE1 instructions with XS prefix in AVX form.
302 // VPSI - SSE1 instructions with TB prefix in AVX form.
304 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
305 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
306 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
308 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
309 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
310 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
312 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
314 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
316 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
318 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
320 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
322 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
325 // SSE2 Instruction Templates:
327 // SDI - SSE2 instructions with XD prefix.
328 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
329 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
330 // PDI - SSE2 instructions with TB and OpSize prefixes.
331 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
332 // VSDI - SSE2 instructions with XD prefix in AVX form.
333 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
335 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
336 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
337 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
339 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
340 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
342 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
343 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
344 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
346 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
348 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
350 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
352 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
354 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
356 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
357 OpSize, Requires<[HasAVX]>;
359 // SSE3 Instruction Templates:
361 // S3I - SSE3 instructions with TB and OpSize prefixes.
362 // S3SI - SSE3 instructions with XS prefix.
363 // S3DI - SSE3 instructions with XD prefix.
365 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
367 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
369 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
371 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
373 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
374 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
378 // SSSE3 Instruction Templates:
380 // SS38I - SSSE3 instructions with T8 prefix.
381 // SS3AI - SSSE3 instructions with TA prefix.
383 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
384 // uses the MMX registers. We put those instructions here because they better
385 // fit into the SSSE3 instruction category rather than the MMX category.
387 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
389 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
390 Requires<[HasSSSE3]>;
391 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
393 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
394 Requires<[HasSSSE3]>;
396 // SSE4.1 Instruction Templates:
398 // SS48I - SSE 4.1 instructions with T8 prefix.
399 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
401 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
403 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
404 Requires<[HasSSE41]>;
405 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
407 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
408 Requires<[HasSSE41]>;
410 // SSE4.2 Instruction Templates:
412 // SS428I - SSE 4.2 instructions with T8 prefix.
413 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
415 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
416 Requires<[HasSSE42]>;
418 // SS42FI - SSE 4.2 instructions with TF prefix.
419 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
421 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
423 // SS42AI = SSE 4.2 instructions with TA prefix
424 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
426 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
427 Requires<[HasSSE42]>;
429 // AVX Instruction Templates:
430 // Instructions introduced in AVX (no SSE equivalent forms)
432 // AVX8I - AVX instructions with T8 and OpSize prefix.
433 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
434 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
436 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
438 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
440 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
443 // AES Instruction Templates:
446 // These use the same encoding as the SSE4.2 T8 and TA encodings.
447 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
449 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
452 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
454 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
457 // CLMUL Instruction Templates
458 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
460 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
461 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
463 // FMA3 Instruction Templates
464 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
466 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
467 OpSize, VEX_4V, Requires<[HasFMA3]>;
469 // X86-64 Instruction templates...
472 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
473 : I<o, F, outs, ins, asm, pattern>, REX_W;
474 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
476 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
477 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
479 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
481 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
483 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
484 let Pattern = pattern;
488 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
490 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
491 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
493 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
494 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
496 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
498 // MMX Instruction templates
501 // MMXI - MMX instructions with TB prefix.
502 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
503 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
504 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
505 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
506 // MMXID - MMX instructions with XD prefix.
507 // MMXIS - MMX instructions with XS prefix.
508 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
510 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
511 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
513 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
514 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
516 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
517 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
519 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
520 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
522 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
523 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
525 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
526 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
528 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;