1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
47 // ImmType - This specifies the immediate type used by an instruction. This is
48 // part of the ad-hoc solution used to emit machine instruction encodings by our
49 // machine code emitter.
50 class ImmType<bits<3> val> {
53 def NoImm : ImmType<0>;
54 def Imm8 : ImmType<1>;
55 def Imm8PCRel : ImmType<2>;
56 def Imm16 : ImmType<3>;
57 def Imm16PCRel : ImmType<4>;
58 def Imm32 : ImmType<5>;
59 def Imm32PCRel : ImmType<6>;
60 def Imm64 : ImmType<7>;
62 // FPFormat - This specifies what form this FP instruction has. This is used by
63 // the Floating-Point stackifier pass.
64 class FPFormat<bits<3> val> {
67 def NotFP : FPFormat<0>;
68 def ZeroArgFP : FPFormat<1>;
69 def OneArgFP : FPFormat<2>;
70 def OneArgFPRW : FPFormat<3>;
71 def TwoArgFP : FPFormat<4>;
72 def CompareFP : FPFormat<5>;
73 def CondMovFP : FPFormat<6>;
74 def SpecialFP : FPFormat<7>;
76 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
77 // Keep in sync with tables in X86InstrInfo.cpp.
78 class Domain<bits<2> val> {
81 def GenericDomain : Domain<0>;
82 def SSEPackedSingle : Domain<1>;
83 def SSEPackedDouble : Domain<2>;
84 def SSEPackedInt : Domain<3>;
86 // Prefix byte classes which are used to indicate to the ad-hoc machine code
87 // emitter that various prefix bytes are required.
88 class OpSize { bit hasOpSizePrefix = 1; }
89 class AdSize { bit hasAdSizePrefix = 1; }
90 class REX_W { bit hasREX_WPrefix = 1; }
91 class LOCK { bit hasLockPrefix = 1; }
92 class SegFS { bits<2> SegOvrBits = 1; }
93 class SegGS { bits<2> SegOvrBits = 2; }
94 class TB { bits<5> Prefix = 1; }
95 class REP { bits<5> Prefix = 2; }
96 class D8 { bits<5> Prefix = 3; }
97 class D9 { bits<5> Prefix = 4; }
98 class DA { bits<5> Prefix = 5; }
99 class DB { bits<5> Prefix = 6; }
100 class DC { bits<5> Prefix = 7; }
101 class DD { bits<5> Prefix = 8; }
102 class DE { bits<5> Prefix = 9; }
103 class DF { bits<5> Prefix = 10; }
104 class XD { bits<5> Prefix = 11; }
105 class XS { bits<5> Prefix = 12; }
106 class T8 { bits<5> Prefix = 13; }
107 class TA { bits<5> Prefix = 14; }
108 class A6 { bits<5> Prefix = 15; }
109 class A7 { bits<5> Prefix = 16; }
110 class T8XD { bits<5> Prefix = 17; }
111 class T8XS { bits<5> Prefix = 18; }
112 class TAXD { bits<5> Prefix = 19; }
113 class XOP8 { bits<5> Prefix = 20; }
114 class XOP9 { bits<5> Prefix = 21; }
115 class VEX { bit hasVEXPrefix = 1; }
116 class VEX_W { bit hasVEX_WPrefix = 1; }
117 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
118 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
119 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
120 class VEX_L { bit hasVEX_L = 1; }
121 class VEX_LIG { bit ignoresVEX_L = 1; }
122 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
123 class XOP_W { bit hasXOP_WPrefix = 1; }
124 class XOP { bit hasXOP_Prefix = 1; }
125 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
126 string AsmStr, Domain d = GenericDomain>
128 let Namespace = "X86";
130 bits<8> Opcode = opcod;
132 bits<6> FormBits = Form.Value;
135 dag OutOperandList = outs;
136 dag InOperandList = ins;
137 string AsmString = AsmStr;
139 // If this is a pseudo instruction, mark it isCodeGenOnly.
140 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
143 // Attributes specific to X86 instructions...
145 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
146 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
148 bits<5> Prefix = 0; // Which prefix byte does this inst have?
149 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
150 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
151 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
152 bits<2> SegOvrBits = 0; // Segment override prefix.
153 Domain ExeDomain = d;
154 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
155 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
156 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
157 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
158 // encode the third operand?
159 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
160 // to be encoded in a immediate field?
161 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
162 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
163 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
164 bit hasXOP_WPrefix = 0; // Same bit as VEX_W, but used for swapping operands
165 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
167 // TSFlags layout should be kept in sync with X86InstrInfo.h.
168 let TSFlags{5-0} = FormBits;
169 let TSFlags{6} = hasOpSizePrefix;
170 let TSFlags{7} = hasAdSizePrefix;
171 let TSFlags{12-8} = Prefix;
172 let TSFlags{13} = hasREX_WPrefix;
173 let TSFlags{16-14} = ImmT.Value;
174 let TSFlags{19-17} = FPForm.Value;
175 let TSFlags{20} = hasLockPrefix;
176 let TSFlags{22-21} = SegOvrBits;
177 let TSFlags{24-23} = ExeDomain.Value;
178 let TSFlags{32-25} = Opcode;
179 let TSFlags{33} = hasVEXPrefix;
180 let TSFlags{34} = hasVEX_WPrefix;
181 let TSFlags{35} = hasVEX_4VPrefix;
182 let TSFlags{36} = hasVEX_4VOp3Prefix;
183 let TSFlags{37} = hasVEX_i8ImmReg;
184 let TSFlags{38} = hasVEX_L;
185 let TSFlags{39} = ignoresVEX_L;
186 let TSFlags{40} = has3DNow0F0FOpcode;
187 let TSFlags{41} = hasXOP_WPrefix;
188 let TSFlags{42} = hasXOP_Prefix;
191 class PseudoI<dag oops, dag iops, list<dag> pattern>
192 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
193 let Pattern = pattern;
196 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
197 list<dag> pattern, Domain d = GenericDomain>
198 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
199 let Pattern = pattern;
202 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
203 list<dag> pattern, Domain d = GenericDomain>
204 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
205 let Pattern = pattern;
208 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
210 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
211 let Pattern = pattern;
214 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
216 : X86Inst<o, f, Imm16, outs, ins, asm> {
217 let Pattern = pattern;
220 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
222 : X86Inst<o, f, Imm32, outs, ins, asm> {
223 let Pattern = pattern;
227 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
229 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
230 let Pattern = pattern;
234 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
236 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
237 let Pattern = pattern;
241 // FPStack Instruction Templates:
242 // FPI - Floating Point Instruction template.
243 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
244 : I<o, F, outs, ins, asm, []> {}
246 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
247 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
248 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
250 let Pattern = pattern;
253 // Templates for instructions that use a 16- or 32-bit segmented address as
254 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
256 // Iseg16 - 16-bit segment selector, 16-bit offset
257 // Iseg32 - 16-bit segment selector, 32-bit offset
259 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
260 list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
261 let Pattern = pattern;
265 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
266 list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
267 let Pattern = pattern;
271 // SI - SSE 1 & 2 scalar instructions
272 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
273 : I<o, F, outs, ins, asm, pattern> {
274 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
275 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
277 // AVX instructions have a 'v' prefix in the mnemonic
278 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
281 // SIi8 - SSE 1 & 2 scalar instructions
282 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
284 : Ii8<o, F, outs, ins, asm, pattern> {
285 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
286 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
288 // AVX instructions have a 'v' prefix in the mnemonic
289 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
292 // PI - SSE 1 & 2 packed instructions
293 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
295 : I<o, F, outs, ins, asm, pattern, d> {
296 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
297 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
299 // AVX instructions have a 'v' prefix in the mnemonic
300 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
303 // PIi8 - SSE 1 & 2 packed instructions with immediate
304 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
305 list<dag> pattern, Domain d>
306 : Ii8<o, F, outs, ins, asm, pattern, d> {
307 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
308 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
310 // AVX instructions have a 'v' prefix in the mnemonic
311 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
314 // SSE1 Instruction Templates:
316 // SSI - SSE1 instructions with XS prefix.
317 // PSI - SSE1 instructions with TB prefix.
318 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
319 // VSSI - SSE1 instructions with XS prefix in AVX form.
320 // VPSI - SSE1 instructions with TB prefix in AVX form.
322 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
323 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
324 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
326 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
327 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
328 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
330 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
332 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
334 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
336 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
338 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
340 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
342 class VoPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
344 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
347 // SSE2 Instruction Templates:
349 // SDI - SSE2 instructions with XD prefix.
350 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
351 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
352 // PDI - SSE2 instructions with TB and OpSize prefixes.
353 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
354 // VSDI - SSE2 instructions with XD prefix in AVX form.
355 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
357 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
358 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
359 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
361 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
362 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
364 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
365 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
366 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
368 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
370 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
372 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
374 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
376 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
378 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, TB,
379 OpSize, Requires<[HasAVX]>;
381 // SSE3 Instruction Templates:
383 // S3I - SSE3 instructions with TB and OpSize prefixes.
384 // S3SI - SSE3 instructions with XS prefix.
385 // S3DI - SSE3 instructions with XD prefix.
387 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
389 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
391 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
393 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
395 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
396 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
400 // SSSE3 Instruction Templates:
402 // SS38I - SSSE3 instructions with T8 prefix.
403 // SS3AI - SSSE3 instructions with TA prefix.
405 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
406 // uses the MMX registers. We put those instructions here because they better
407 // fit into the SSSE3 instruction category rather than the MMX category.
409 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
411 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
412 Requires<[HasSSSE3]>;
413 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
415 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
416 Requires<[HasSSSE3]>;
418 // SSE4.1 Instruction Templates:
420 // SS48I - SSE 4.1 instructions with T8 prefix.
421 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
423 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
425 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
426 Requires<[HasSSE41]>;
427 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
429 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
430 Requires<[HasSSE41]>;
432 // SSE4.2 Instruction Templates:
434 // SS428I - SSE 4.2 instructions with T8 prefix.
435 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
437 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
438 Requires<[HasSSE42]>;
440 // SS42FI - SSE 4.2 instructions with T8XD prefix.
441 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
443 : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>;
445 // SS42AI = SSE 4.2 instructions with TA prefix
446 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
448 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
449 Requires<[HasSSE42]>;
451 // AVX Instruction Templates:
452 // Instructions introduced in AVX (no SSE equivalent forms)
454 // AVX8I - AVX instructions with T8 and OpSize prefix.
455 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
456 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
458 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
460 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
462 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
465 // AVX2 Instruction Templates:
466 // Instructions introduced in AVX2 (no SSE equivalent forms)
468 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
469 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
470 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
472 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
474 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
476 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
479 // AES Instruction Templates:
482 // These use the same encoding as the SSE4.2 T8 and TA encodings.
483 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
485 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
486 Requires<[HasSSE2, HasAES]>;
488 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
490 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
491 Requires<[HasSSE2, HasAES]>;
493 // CLMUL Instruction Templates
494 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
496 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
497 OpSize, Requires<[HasSSE2, HasCLMUL]>;
499 class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
501 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
502 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
504 // FMA3 Instruction Templates
505 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
507 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
508 OpSize, VEX_4V, Requires<[HasFMA3]>;
510 // FMA4 Instruction Templates
511 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
513 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
514 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
516 // XOP 2, 3 and 4 Operand Instruction Template
517 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
519 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>,
520 XOP, XOP9, Requires<[HasXOP]>;
522 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
523 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
525 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>,
526 XOP, XOP8, Requires<[HasXOP]>;
528 // XOP 5 operand instruction (VEX encoding!)
529 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
531 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
532 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
534 // X86-64 Instruction templates...
537 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
538 : I<o, F, outs, ins, asm, pattern>, REX_W;
539 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
541 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
542 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
544 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
546 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
548 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
549 let Pattern = pattern;
553 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
555 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
556 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
558 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
559 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
561 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
562 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
564 : VPDI<o, F, outs, ins, asm, pattern>, VEX_W;
566 // MMX Instruction templates
569 // MMXI - MMX instructions with TB prefix.
570 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
571 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
572 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
573 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
574 // MMXID - MMX instructions with XD prefix.
575 // MMXIS - MMX instructions with XS prefix.
576 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
578 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
579 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
581 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
582 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
584 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
585 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
587 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
588 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
590 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
591 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
593 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
594 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
596 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;