1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_CA : Format<39>;
39 def MRM_CB : Format<40>;
40 def MRM_E8 : Format<41>;
41 def MRM_F0 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_F8 : Format<45>;
45 def MRM_F9 : Format<46>;
46 def MRM_D0 : Format<47>;
47 def MRM_D1 : Format<48>;
48 def MRM_D4 : Format<49>;
49 def MRM_D5 : Format<50>;
50 def MRM_D6 : Format<51>;
51 def MRM_D8 : Format<52>;
52 def MRM_D9 : Format<53>;
53 def MRM_DA : Format<54>;
54 def MRM_DB : Format<55>;
55 def MRM_DC : Format<56>;
56 def MRM_DD : Format<57>;
57 def MRM_DE : Format<58>;
58 def MRM_DF : Format<59>;
60 // ImmType - This specifies the immediate type used by an instruction. This is
61 // part of the ad-hoc solution used to emit machine instruction encodings by our
62 // machine code emitter.
63 class ImmType<bits<3> val> {
66 def NoImm : ImmType<0>;
67 def Imm8 : ImmType<1>;
68 def Imm8PCRel : ImmType<2>;
69 def Imm16 : ImmType<3>;
70 def Imm16PCRel : ImmType<4>;
71 def Imm32 : ImmType<5>;
72 def Imm32PCRel : ImmType<6>;
73 def Imm64 : ImmType<7>;
75 // FPFormat - This specifies what form this FP instruction has. This is used by
76 // the Floating-Point stackifier pass.
77 class FPFormat<bits<3> val> {
80 def NotFP : FPFormat<0>;
81 def ZeroArgFP : FPFormat<1>;
82 def OneArgFP : FPFormat<2>;
83 def OneArgFPRW : FPFormat<3>;
84 def TwoArgFP : FPFormat<4>;
85 def CompareFP : FPFormat<5>;
86 def CondMovFP : FPFormat<6>;
87 def SpecialFP : FPFormat<7>;
89 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
90 // Keep in sync with tables in X86InstrInfo.cpp.
91 class Domain<bits<2> val> {
94 def GenericDomain : Domain<0>;
95 def SSEPackedSingle : Domain<1>;
96 def SSEPackedDouble : Domain<2>;
97 def SSEPackedInt : Domain<3>;
99 // Prefix byte classes which are used to indicate to the ad-hoc machine code
100 // emitter that various prefix bytes are required.
101 class OpSize { bit hasOpSizePrefix = 1; }
102 class AdSize { bit hasAdSizePrefix = 1; }
103 class REX_W { bit hasREX_WPrefix = 1; }
104 class LOCK { bit hasLockPrefix = 1; }
105 class SegFS { bits<2> SegOvrBits = 1; }
106 class SegGS { bits<2> SegOvrBits = 2; }
107 class TB { bits<5> Prefix = 1; }
108 class REP { bits<5> Prefix = 2; }
109 class D8 { bits<5> Prefix = 3; }
110 class D9 { bits<5> Prefix = 4; }
111 class DA { bits<5> Prefix = 5; }
112 class DB { bits<5> Prefix = 6; }
113 class DC { bits<5> Prefix = 7; }
114 class DD { bits<5> Prefix = 8; }
115 class DE { bits<5> Prefix = 9; }
116 class DF { bits<5> Prefix = 10; }
117 class XD { bits<5> Prefix = 11; }
118 class XS { bits<5> Prefix = 12; }
119 class T8 { bits<5> Prefix = 13; }
120 class TA { bits<5> Prefix = 14; }
121 class A6 { bits<5> Prefix = 15; }
122 class A7 { bits<5> Prefix = 16; }
123 class T8XD { bits<5> Prefix = 17; }
124 class T8XS { bits<5> Prefix = 18; }
125 class TAXD { bits<5> Prefix = 19; }
126 class XOP8 { bits<5> Prefix = 20; }
127 class XOP9 { bits<5> Prefix = 21; }
128 class VEX { bit hasVEXPrefix = 1; }
129 class VEX_W { bit hasVEX_WPrefix = 1; }
130 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
131 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
132 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
133 class VEX_L { bit hasVEX_L = 1; }
134 class VEX_LIG { bit ignoresVEX_L = 1; }
135 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
136 class MemOp4 { bit hasMemOp4Prefix = 1; }
137 class XOP { bit hasXOP_Prefix = 1; }
138 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
141 Domain d = GenericDomain>
143 let Namespace = "X86";
145 bits<8> Opcode = opcod;
147 bits<6> FormBits = Form.Value;
150 dag OutOperandList = outs;
151 dag InOperandList = ins;
152 string AsmString = AsmStr;
154 // If this is a pseudo instruction, mark it isCodeGenOnly.
155 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
157 let Itinerary = itin;
160 // Attributes specific to X86 instructions...
162 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
163 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
165 bits<5> Prefix = 0; // Which prefix byte does this inst have?
166 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
167 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
168 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
169 bits<2> SegOvrBits = 0; // Segment override prefix.
170 Domain ExeDomain = d;
171 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
172 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
173 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
174 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
175 // encode the third operand?
176 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
177 // to be encoded in a immediate field?
178 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
179 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
180 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
181 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
182 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
184 // TSFlags layout should be kept in sync with X86InstrInfo.h.
185 let TSFlags{5-0} = FormBits;
186 let TSFlags{6} = hasOpSizePrefix;
187 let TSFlags{7} = hasAdSizePrefix;
188 let TSFlags{12-8} = Prefix;
189 let TSFlags{13} = hasREX_WPrefix;
190 let TSFlags{16-14} = ImmT.Value;
191 let TSFlags{19-17} = FPForm.Value;
192 let TSFlags{20} = hasLockPrefix;
193 let TSFlags{22-21} = SegOvrBits;
194 let TSFlags{24-23} = ExeDomain.Value;
195 let TSFlags{32-25} = Opcode;
196 let TSFlags{33} = hasVEXPrefix;
197 let TSFlags{34} = hasVEX_WPrefix;
198 let TSFlags{35} = hasVEX_4VPrefix;
199 let TSFlags{36} = hasVEX_4VOp3Prefix;
200 let TSFlags{37} = hasVEX_i8ImmReg;
201 let TSFlags{38} = hasVEX_L;
202 let TSFlags{39} = ignoresVEX_L;
203 let TSFlags{40} = has3DNow0F0FOpcode;
204 let TSFlags{41} = hasMemOp4Prefix;
205 let TSFlags{42} = hasXOP_Prefix;
208 class PseudoI<dag oops, dag iops, list<dag> pattern>
209 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
210 let Pattern = pattern;
213 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
214 list<dag> pattern, InstrItinClass itin = NoItinerary,
215 Domain d = GenericDomain>
216 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
217 let Pattern = pattern;
220 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
221 list<dag> pattern, InstrItinClass itin = NoItinerary,
222 Domain d = GenericDomain>
223 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
224 let Pattern = pattern;
227 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
228 list<dag> pattern, InstrItinClass itin = NoItinerary>
229 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
230 let Pattern = pattern;
233 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
234 list<dag> pattern, InstrItinClass itin = NoItinerary>
235 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
236 let Pattern = pattern;
239 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
240 list<dag> pattern, InstrItinClass itin = NoItinerary>
241 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
242 let Pattern = pattern;
246 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
247 list<dag> pattern, InstrItinClass itin = NoItinerary>
248 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
249 let Pattern = pattern;
253 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
254 list<dag> pattern, InstrItinClass itin = NoItinerary>
255 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
256 let Pattern = pattern;
260 // FPStack Instruction Templates:
261 // FPI - Floating Point Instruction template.
262 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
263 InstrItinClass itin = NoItinerary>
264 : I<o, F, outs, ins, asm, [], itin> {}
266 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
267 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
268 InstrItinClass itin = NoItinerary>
269 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
271 let Pattern = pattern;
274 // Templates for instructions that use a 16- or 32-bit segmented address as
275 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
277 // Iseg16 - 16-bit segment selector, 16-bit offset
278 // Iseg32 - 16-bit segment selector, 32-bit offset
280 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
281 list<dag> pattern, InstrItinClass itin = NoItinerary>
282 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
283 let Pattern = pattern;
287 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
288 list<dag> pattern, InstrItinClass itin = NoItinerary>
289 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
290 let Pattern = pattern;
297 // SI - SSE 1 & 2 scalar instructions
298 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
299 list<dag> pattern, InstrItinClass itin = NoItinerary>
300 : I<o, F, outs, ins, asm, pattern, itin> {
301 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
302 // !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
303 // !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])));
304 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
305 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
306 !if(hasOpSizePrefix, [UseSSE2], [UseSSE1]))));
308 // AVX instructions have a 'v' prefix in the mnemonic
309 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
312 // SIi8 - SSE 1 & 2 scalar instructions
313 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
314 list<dag> pattern, InstrItinClass itin = NoItinerary>
315 : Ii8<o, F, outs, ins, asm, pattern, itin> {
316 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
317 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
319 // AVX instructions have a 'v' prefix in the mnemonic
320 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
323 // PI - SSE 1 & 2 packed instructions
324 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
325 InstrItinClass itin, Domain d>
326 : I<o, F, outs, ins, asm, pattern, itin, d> {
327 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
328 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
330 // AVX instructions have a 'v' prefix in the mnemonic
331 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
334 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
335 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
336 InstrItinClass itin, Domain d>
337 : I<o, F, outs, ins, asm, pattern, itin, d> {
338 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
341 // PIi8 - SSE 1 & 2 packed instructions with immediate
342 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
343 list<dag> pattern, InstrItinClass itin, Domain d>
344 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
345 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
346 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
348 // AVX instructions have a 'v' prefix in the mnemonic
349 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
352 // SSE1 Instruction Templates:
354 // SSI - SSE1 instructions with XS prefix.
355 // PSI - SSE1 instructions with TB prefix.
356 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
357 // VSSI - SSE1 instructions with XS prefix in AVX form.
358 // VPSI - SSE1 instructions with TB prefix in AVX form.
360 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
361 list<dag> pattern, InstrItinClass itin = NoItinerary>
362 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
363 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
364 list<dag> pattern, InstrItinClass itin = NoItinerary>
365 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
366 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
367 list<dag> pattern, InstrItinClass itin = NoItinerary>
368 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
370 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
371 list<dag> pattern, InstrItinClass itin = NoItinerary>
372 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
374 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
375 list<dag> pattern, InstrItinClass itin = NoItinerary>
376 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
378 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
379 list<dag> pattern, InstrItinClass itin = NoItinerary>
380 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
383 // SSE2 Instruction Templates:
385 // SDI - SSE2 instructions with XD prefix.
386 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
387 // S2SI - SSE2 instructions with XS prefix.
388 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
389 // PDI - SSE2 instructions with TB and OpSize prefixes.
390 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
391 // VSDI - SSE2 instructions with XD prefix in AVX form.
392 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
393 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
395 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
398 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
399 list<dag> pattern, InstrItinClass itin = NoItinerary>
400 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
401 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
402 list<dag> pattern, InstrItinClass itin = NoItinerary>
403 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
404 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
405 list<dag> pattern, InstrItinClass itin = NoItinerary>
406 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
407 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
408 list<dag> pattern, InstrItinClass itin = NoItinerary>
409 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
410 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 list<dag> pattern, InstrItinClass itin = NoItinerary>
412 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
414 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
415 list<dag> pattern, InstrItinClass itin = NoItinerary>
416 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
418 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
419 list<dag> pattern, InstrItinClass itin = NoItinerary>
420 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
422 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
423 list<dag> pattern, InstrItinClass itin = NoItinerary>
424 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
426 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
427 list<dag> pattern, InstrItinClass itin = NoItinerary>
428 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
429 OpSize, Requires<[HasAVX]>;
430 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
431 list<dag> pattern, InstrItinClass itin = NoItinerary>
432 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
433 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
434 list<dag> pattern, InstrItinClass itin = NoItinerary>
435 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
437 // SSE3 Instruction Templates:
439 // S3I - SSE3 instructions with TB and OpSize prefixes.
440 // S3SI - SSE3 instructions with XS prefix.
441 // S3DI - SSE3 instructions with XD prefix.
443 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
444 list<dag> pattern, InstrItinClass itin = NoItinerary>
445 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
447 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
448 list<dag> pattern, InstrItinClass itin = NoItinerary>
449 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
451 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
452 list<dag> pattern, InstrItinClass itin = NoItinerary>
453 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
457 // SSSE3 Instruction Templates:
459 // SS38I - SSSE3 instructions with T8 prefix.
460 // SS3AI - SSSE3 instructions with TA prefix.
461 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
462 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
464 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
465 // uses the MMX registers. The 64-bit versions are grouped with the MMX
466 // classes. They need to be enabled even if AVX is enabled.
468 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
469 list<dag> pattern, InstrItinClass itin = NoItinerary>
470 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
471 Requires<[UseSSSE3]>;
472 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
473 list<dag> pattern, InstrItinClass itin = NoItinerary>
474 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
475 Requires<[UseSSSE3]>;
476 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
477 list<dag> pattern, InstrItinClass itin = NoItinerary>
478 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
479 Requires<[HasSSSE3]>;
480 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin = NoItinerary>
482 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
483 Requires<[HasSSSE3]>;
485 // SSE4.1 Instruction Templates:
487 // SS48I - SSE 4.1 instructions with T8 prefix.
488 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
490 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
491 list<dag> pattern, InstrItinClass itin = NoItinerary>
492 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
493 Requires<[UseSSE41]>;
494 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
495 list<dag> pattern, InstrItinClass itin = NoItinerary>
496 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
497 Requires<[UseSSE41]>;
499 // SSE4.2 Instruction Templates:
501 // SS428I - SSE 4.2 instructions with T8 prefix.
502 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
505 Requires<[UseSSE42]>;
507 // SS42FI - SSE 4.2 instructions with T8XD prefix.
508 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
509 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
510 list<dag> pattern, InstrItinClass itin = NoItinerary>
511 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
513 // SS42AI = SSE 4.2 instructions with TA prefix
514 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
515 list<dag> pattern, InstrItinClass itin = NoItinerary>
516 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
517 Requires<[UseSSE42]>;
519 // AVX Instruction Templates:
520 // Instructions introduced in AVX (no SSE equivalent forms)
522 // AVX8I - AVX instructions with T8 and OpSize prefix.
523 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
524 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
525 list<dag> pattern, InstrItinClass itin = NoItinerary>
526 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
528 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
529 list<dag> pattern, InstrItinClass itin = NoItinerary>
530 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
533 // AVX2 Instruction Templates:
534 // Instructions introduced in AVX2 (no SSE equivalent forms)
536 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
537 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
538 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
539 list<dag> pattern, InstrItinClass itin = NoItinerary>
540 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
542 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
543 list<dag> pattern, InstrItinClass itin = NoItinerary>
544 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
547 // AES Instruction Templates:
550 // These use the same encoding as the SSE4.2 T8 and TA encodings.
551 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
552 list<dag>pattern, InstrItinClass itin = NoItinerary>
553 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
556 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
557 list<dag> pattern, InstrItinClass itin = NoItinerary>
558 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
561 // PCLMUL Instruction Templates
562 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
563 list<dag>pattern, InstrItinClass itin = NoItinerary>
564 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
565 OpSize, Requires<[HasPCLMUL]>;
567 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
568 list<dag>pattern, InstrItinClass itin = NoItinerary>
569 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
570 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
572 // FMA3 Instruction Templates
573 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
574 list<dag>pattern, InstrItinClass itin = NoItinerary>
575 : I<o, F, outs, ins, asm, pattern, itin>, T8,
576 OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
578 // FMA4 Instruction Templates
579 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
580 list<dag>pattern, InstrItinClass itin = NoItinerary>
581 : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
582 OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
584 // XOP 2, 3 and 4 Operand Instruction Template
585 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
586 list<dag> pattern, InstrItinClass itin = NoItinerary>
587 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
588 XOP, XOP9, Requires<[HasXOP]>;
590 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
591 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
592 list<dag> pattern, InstrItinClass itin = NoItinerary>
593 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
594 XOP, XOP8, Requires<[HasXOP]>;
596 // XOP 5 operand instruction (VEX encoding!)
597 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag>pattern, InstrItinClass itin = NoItinerary>
599 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
600 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
602 // X86-64 Instruction templates...
605 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = NoItinerary>
607 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
608 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
609 list<dag> pattern, InstrItinClass itin = NoItinerary>
610 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
611 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
612 list<dag> pattern, InstrItinClass itin = NoItinerary>
613 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
615 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
616 list<dag> pattern, InstrItinClass itin = NoItinerary>
617 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
618 let Pattern = pattern;
622 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
623 list<dag> pattern, InstrItinClass itin = NoItinerary>
624 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
625 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
626 list<dag> pattern, InstrItinClass itin = NoItinerary>
627 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
628 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
629 list<dag> pattern, InstrItinClass itin = NoItinerary>
630 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
631 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
632 list<dag> pattern, InstrItinClass itin = NoItinerary>
633 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
635 // MMX Instruction templates
638 // MMXI - MMX instructions with TB prefix.
639 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
640 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
641 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
642 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
643 // MMXID - MMX instructions with XD prefix.
644 // MMXIS - MMX instructions with XS prefix.
645 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
646 list<dag> pattern, InstrItinClass itin = NoItinerary>
647 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
648 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
649 list<dag> pattern, InstrItinClass itin = NoItinerary>
650 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
651 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
652 list<dag> pattern, InstrItinClass itin = NoItinerary>
653 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
654 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
655 list<dag> pattern, InstrItinClass itin = NoItinerary>
656 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
657 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
658 list<dag> pattern, InstrItinClass itin = NoItinerary>
659 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
660 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
661 list<dag> pattern, InstrItinClass itin = NoItinerary>
662 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
663 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
664 list<dag> pattern, InstrItinClass itin = NoItinerary>
665 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;