1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
43 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
44 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
45 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
47 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
48 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
50 // Commutative and Associative FMIN and FMAX.
51 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
56 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
57 [SDNPCommutative, SDNPAssociative]>;
58 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
65 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
66 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
67 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
68 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
69 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
70 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
71 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
72 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
73 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
74 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
75 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86andnp : SDNode<"X86ISD::ANDNP",
85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def X86psign : SDNode<"X86ISD::PSIGN",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86pextrb : SDNode<"X86ISD::PEXTRB",
91 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
92 def X86pextrw : SDNode<"X86ISD::PEXTRW",
93 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
94 def X86pinsrb : SDNode<"X86ISD::PINSRB",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86pinsrw : SDNode<"X86ISD::PINSRW",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86insertps : SDNode<"X86ISD::INSERTPS",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
103 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
104 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
106 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
109 def X86vzext : SDNode<"X86ISD::VZEXT",
110 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
111 SDTCisInt<0>, SDTCisInt<1>,
112 SDTCisOpSmallerThanOp<1, 0>]>>;
114 def X86vsext : SDNode<"X86ISD::VSEXT",
115 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
116 SDTCisInt<0>, SDTCisInt<1>,
117 SDTCisOpSmallerThanOp<1, 0>]>>;
119 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
120 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
123 def X86trunc : SDNode<"X86ISD::TRUNC",
124 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
125 SDTCisOpSmallerThanOp<0, 1>]>>;
127 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
128 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisVec<2>, SDTCisInt<2>,
131 SDTCisOpSmallerThanOp<0, 2>]>>;
132 def X86vfpext : SDNode<"X86ISD::VFPEXT",
133 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
134 SDTCisFP<0>, SDTCisFP<1>,
135 SDTCisOpSmallerThanOp<1, 0>]>>;
136 def X86vfpround: SDNode<"X86ISD::VFPROUND",
137 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
138 SDTCisFP<0>, SDTCisFP<1>,
139 SDTCisOpSmallerThanOp<0, 1>]>>;
141 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
142 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
143 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
144 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
145 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
147 def X86IntCmpMask : SDTypeProfile<1, 2,
148 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
149 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
150 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
153 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
154 SDTCisVec<1>, SDTCisSameAs<2, 1>,
155 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
156 def X86CmpMaskCCRound :
157 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
158 SDTCisVec<1>, SDTCisSameAs<2, 1>,
159 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
161 def X86CmpMaskCCScalar :
162 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
164 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
165 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
166 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
167 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
169 def X86vshl : SDNode<"X86ISD::VSHL",
170 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
172 def X86vsrl : SDNode<"X86ISD::VSRL",
173 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
175 def X86vsra : SDNode<"X86ISD::VSRA",
176 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
179 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
180 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
181 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
183 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
185 SDTCisSameAs<2, 1>]>;
186 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
187 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
188 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
189 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
190 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
191 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
192 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
193 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
194 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
195 SDTCisVec<1>, SDTCisSameAs<2, 1>,
196 SDTCVecEltisVT<0, i1>,
197 SDTCisSameNumEltsAs<0, 1>]>>;
198 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
199 SDTCisVec<1>, SDTCisSameAs<2, 1>,
200 SDTCVecEltisVT<0, i1>,
201 SDTCisSameNumEltsAs<0, 1>]>>;
202 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
204 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
206 SDTCisSameAs<1,2>]>>;
207 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
208 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
209 SDTCisSameAs<1,2>]>>;
211 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
212 // translated into one of the target nodes below during lowering.
213 // Note: this is a work in progress...
214 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
215 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
217 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
218 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
220 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
222 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
223 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
224 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
226 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
229 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
230 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
232 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
233 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
235 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
236 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
238 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
239 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
241 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
242 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
243 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
244 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
245 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
246 SDTCisVec<0>, SDTCisInt<2>]>;
247 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
248 SDTCisVec<0>, SDTCisInt<3>]>;
249 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
250 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
252 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
253 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
254 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
256 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
257 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
258 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
260 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
261 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
263 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
264 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
265 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
267 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
268 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
270 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
271 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
272 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
274 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
275 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
277 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
278 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
279 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
281 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
282 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
284 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
285 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
286 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
287 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
288 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
289 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
291 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
293 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
294 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
296 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
297 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
298 SDTCisSubVecOfVec<1, 0>]>, []>;
299 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
300 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
301 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
302 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
303 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
305 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
307 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
309 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
310 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
311 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
312 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
313 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
314 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
315 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
316 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
317 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
319 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
320 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
321 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
322 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
323 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
324 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
326 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
327 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
328 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
329 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
330 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
331 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
333 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
334 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
335 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
337 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
338 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
339 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
341 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
342 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
344 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
345 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
346 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
349 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
350 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
352 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
353 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
354 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
355 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
357 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
358 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
360 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
361 def X86SuintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
363 //===----------------------------------------------------------------------===//
364 // SSE Complex Patterns
365 //===----------------------------------------------------------------------===//
367 // These are 'extloads' from a scalar to the low element of a vector, zeroing
368 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
370 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
371 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
373 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
374 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
377 def ssmem : Operand<v4f32> {
378 let PrintMethod = "printf32mem";
379 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
380 let ParserMatchClass = X86Mem32AsmOperand;
381 let OperandType = "OPERAND_MEMORY";
383 def sdmem : Operand<v2f64> {
384 let PrintMethod = "printf64mem";
385 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
386 let ParserMatchClass = X86Mem64AsmOperand;
387 let OperandType = "OPERAND_MEMORY";
390 //===----------------------------------------------------------------------===//
391 // SSE pattern fragments
392 //===----------------------------------------------------------------------===//
394 // 128-bit load pattern fragments
395 // NOTE: all 128-bit integer vector loads are promoted to v2i64
396 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
397 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
398 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
400 // 256-bit load pattern fragments
401 // NOTE: all 256-bit integer vector loads are promoted to v4i64
402 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
403 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
404 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
406 // 512-bit load pattern fragments
407 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
408 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
409 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
410 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
411 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
412 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
414 // 128-/256-/512-bit extload pattern fragments
415 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
416 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
417 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
419 // These are needed to match a scalar load that is used in a vector-only
420 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
421 // The memory operand is required to be a 128-bit load, so it must be converted
422 // from a vector to a scalar.
423 def loadf32_128 : PatFrag<(ops node:$ptr),
424 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
425 def loadf64_128 : PatFrag<(ops node:$ptr),
426 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
428 // Like 'store', but always requires 128-bit vector alignment.
429 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
430 (store node:$val, node:$ptr), [{
431 return cast<StoreSDNode>(N)->getAlignment() >= 16;
434 // Like 'store', but always requires 256-bit vector alignment.
435 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
436 (store node:$val, node:$ptr), [{
437 return cast<StoreSDNode>(N)->getAlignment() >= 32;
440 // Like 'store', but always requires 512-bit vector alignment.
441 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
442 (store node:$val, node:$ptr), [{
443 return cast<StoreSDNode>(N)->getAlignment() >= 64;
446 // Like 'load', but always requires 128-bit vector alignment.
447 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
448 return cast<LoadSDNode>(N)->getAlignment() >= 16;
451 // Like 'X86vzload', but always requires 128-bit vector alignment.
452 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
453 return cast<MemSDNode>(N)->getAlignment() >= 16;
456 // Like 'load', but always requires 256-bit vector alignment.
457 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
458 return cast<LoadSDNode>(N)->getAlignment() >= 32;
461 // Like 'load', but always requires 512-bit vector alignment.
462 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
463 return cast<LoadSDNode>(N)->getAlignment() >= 64;
466 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
467 (f32 (alignedload node:$ptr))>;
468 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
469 (f64 (alignedload node:$ptr))>;
471 // 128-bit aligned load pattern fragments
472 // NOTE: all 128-bit integer vector loads are promoted to v2i64
473 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
474 (v4f32 (alignedload node:$ptr))>;
475 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
476 (v2f64 (alignedload node:$ptr))>;
477 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
478 (v2i64 (alignedload node:$ptr))>;
480 // 256-bit aligned load pattern fragments
481 // NOTE: all 256-bit integer vector loads are promoted to v4i64
482 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
483 (v8f32 (alignedload256 node:$ptr))>;
484 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
485 (v4f64 (alignedload256 node:$ptr))>;
486 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
487 (v4i64 (alignedload256 node:$ptr))>;
489 // 512-bit aligned load pattern fragments
490 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
491 (v16f32 (alignedload512 node:$ptr))>;
492 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
493 (v16i32 (alignedload512 node:$ptr))>;
494 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
495 (v8f64 (alignedload512 node:$ptr))>;
496 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
497 (v8i64 (alignedload512 node:$ptr))>;
499 // Like 'load', but uses special alignment checks suitable for use in
500 // memory operands in most SSE instructions, which are required to
501 // be naturally aligned on some targets but not on others. If the subtarget
502 // allows unaligned accesses, match any load, though this may require
503 // setting a feature bit in the processor (on startup, for example).
504 // Opteron 10h and later implement such a feature.
505 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
506 return Subtarget->hasSSEUnalignedMem()
507 || cast<LoadSDNode>(N)->getAlignment() >= 16;
510 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
511 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
513 // 128-bit memop pattern fragments
514 // NOTE: all 128-bit integer vector loads are promoted to v2i64
515 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
516 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
517 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
519 // These are needed to match a scalar memop that is used in a vector-only
520 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
521 // The memory operand is required to be a 128-bit load, so it must be converted
522 // from a vector to a scalar.
523 def memopfsf32_128 : PatFrag<(ops node:$ptr),
524 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
525 def memopfsf64_128 : PatFrag<(ops node:$ptr),
526 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
529 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
531 // FIXME: 8 byte alignment for mmx reads is not required
532 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
533 return cast<LoadSDNode>(N)->getAlignment() >= 8;
536 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
539 // Like 'store', but requires the non-temporal bit to be set
540 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
541 (st node:$val, node:$ptr), [{
542 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
543 return ST->isNonTemporal();
547 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
548 (st node:$val, node:$ptr), [{
549 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
550 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
551 ST->getAddressingMode() == ISD::UNINDEXED &&
552 ST->getAlignment() >= 16;
556 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
557 (st node:$val, node:$ptr), [{
558 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
559 return ST->isNonTemporal() &&
560 ST->getAlignment() < 16;
564 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
565 (masked_gather node:$src1, node:$src2, node:$src3) , [{
566 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
567 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
568 Mgt->getBasePtr().getValueType() == MVT::v4i32);
572 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
573 (masked_gather node:$src1, node:$src2, node:$src3) , [{
574 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
575 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
576 Mgt->getBasePtr().getValueType() == MVT::v8i32);
580 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
581 (masked_gather node:$src1, node:$src2, node:$src3) , [{
582 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
583 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
584 Mgt->getBasePtr().getValueType() == MVT::v2i64);
587 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
588 (masked_gather node:$src1, node:$src2, node:$src3) , [{
589 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
590 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
591 Mgt->getBasePtr().getValueType() == MVT::v4i64);
594 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
595 (masked_gather node:$src1, node:$src2, node:$src3) , [{
596 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
597 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
598 Mgt->getBasePtr().getValueType() == MVT::v8i64);
601 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
602 (masked_gather node:$src1, node:$src2, node:$src3) , [{
603 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
604 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
605 Mgt->getBasePtr().getValueType() == MVT::v16i32);
609 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
610 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
611 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
612 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
613 Sc->getBasePtr().getValueType() == MVT::v8i32);
617 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
618 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
619 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
620 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
621 Sc->getBasePtr().getValueType() == MVT::v8i64);
624 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
625 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
626 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
627 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
628 Sc->getBasePtr().getValueType() == MVT::v16i32);
632 // 128-bit bitconvert pattern fragments
633 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
634 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
635 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
636 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
637 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
638 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
640 // 256-bit bitconvert pattern fragments
641 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
642 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
643 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
644 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
645 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
647 // 512-bit bitconvert pattern fragments
648 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
649 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
650 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
651 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
653 def vzmovl_v2i64 : PatFrag<(ops node:$src),
654 (bitconvert (v2i64 (X86vzmovl
655 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
656 def vzmovl_v4i32 : PatFrag<(ops node:$src),
657 (bitconvert (v4i32 (X86vzmovl
658 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
660 def vzload_v2i64 : PatFrag<(ops node:$src),
661 (bitconvert (v2i64 (X86vzload node:$src)))>;
664 def fp32imm0 : PatLeaf<(f32 fpimm), [{
665 return N->isExactlyValue(+0.0);
668 def I8Imm : SDNodeXForm<imm, [{
669 // Transformation function: get the low 8 bits.
670 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
673 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
674 def FROUND_CURRENT : ImmLeaf<i32, [{
675 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
678 // BYTE_imm - Transform bit immediates into byte immediates.
679 def BYTE_imm : SDNodeXForm<imm, [{
680 // Transformation function: imm >> 3
681 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
684 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
685 // to VEXTRACTF128/VEXTRACTI128 imm.
686 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
687 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
690 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
691 // VINSERTF128/VINSERTI128 imm.
692 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
693 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
696 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
697 // to VEXTRACTF64x4 imm.
698 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
699 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
702 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
704 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
705 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
708 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
709 (extract_subvector node:$bigvec,
711 return X86::isVEXTRACT128Index(N);
712 }], EXTRACT_get_vextract128_imm>;
714 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
716 (insert_subvector node:$bigvec, node:$smallvec,
718 return X86::isVINSERT128Index(N);
719 }], INSERT_get_vinsert128_imm>;
722 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
723 (extract_subvector node:$bigvec,
725 return X86::isVEXTRACT256Index(N);
726 }], EXTRACT_get_vextract256_imm>;
728 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
730 (insert_subvector node:$bigvec, node:$smallvec,
732 return X86::isVINSERT256Index(N);
733 }], INSERT_get_vinsert256_imm>;
735 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
736 (masked_load node:$src1, node:$src2, node:$src3), [{
737 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
738 return Load->getAlignment() >= 16;
742 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
743 (masked_load node:$src1, node:$src2, node:$src3), [{
744 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
745 return Load->getAlignment() >= 32;
749 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
750 (masked_load node:$src1, node:$src2, node:$src3), [{
751 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
752 return Load->getAlignment() >= 64;
756 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
757 (masked_load node:$src1, node:$src2, node:$src3), [{
758 return isa<MaskedLoadSDNode>(N);
761 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
762 (masked_store node:$src1, node:$src2, node:$src3), [{
763 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
764 return Store->getAlignment() >= 16;
768 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
769 (masked_store node:$src1, node:$src2, node:$src3), [{
770 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
771 return Store->getAlignment() >= 32;
775 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
776 (masked_store node:$src1, node:$src2, node:$src3), [{
777 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
778 return Store->getAlignment() >= 64;
782 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
783 (masked_store node:$src1, node:$src2, node:$src3), [{
784 return isa<MaskedStoreSDNode>(N);