1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
62 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
64 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
65 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
66 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
67 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
68 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
69 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
70 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
71 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
73 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTCisVT<1, v4i32>]>>;
75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
84 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
85 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
86 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
87 def X86andnp : SDNode<"X86ISD::ANDNP",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86psign : SDNode<"X86ISD::PSIGN",
91 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
93 def X86pextrb : SDNode<"X86ISD::PEXTRB",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pextrw : SDNode<"X86ISD::PEXTRW",
96 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
97 def X86pinsrb : SDNode<"X86ISD::PINSRB",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86pinsrw : SDNode<"X86ISD::PINSRW",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
103 def X86insertps : SDNode<"X86ISD::INSERTPS",
104 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
105 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
106 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
107 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
109 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
110 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
112 def X86vzext : SDNode<"X86ISD::VZEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def X86vsext : SDNode<"X86ISD::VSEXT",
118 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
119 SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<1, 0>]>>;
122 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
123 SDTCisInt<0>, SDTCisInt<1>,
124 SDTCisOpSmallerThanOp<0, 1>]>;
126 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
127 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
128 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
130 def X86trunc : SDNode<"X86ISD::TRUNC",
131 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
132 SDTCisOpSmallerThanOp<0, 1>]>>;
133 def X86vfpext : SDNode<"X86ISD::VFPEXT",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<1, 0>]>>;
137 def X86vfpround: SDNode<"X86ISD::VFPROUND",
138 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
139 SDTCisFP<0>, SDTCisFP<1>,
140 SDTCisOpSmallerThanOp<0, 1>]>>;
142 def X86fround: SDNode<"X86ISD::VFPROUND",
143 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
144 SDTCVecEltisVT<0, f32>,
145 SDTCVecEltisVT<1, f64>,
146 SDTCVecEltisVT<2, f64>,
147 SDTCisOpSmallerThanOp<0, 1>]>>;
148 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
149 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
150 SDTCVecEltisVT<0, f32>,
151 SDTCVecEltisVT<1, f64>,
152 SDTCVecEltisVT<2, f64>,
153 SDTCisOpSmallerThanOp<0, 1>,
156 def X86fpext : SDNode<"X86ISD::VFPEXT",
157 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
158 SDTCVecEltisVT<0, f64>,
159 SDTCVecEltisVT<1, f32>,
160 SDTCVecEltisVT<2, f32>,
161 SDTCisOpSmallerThanOp<1, 0>]>>;
163 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
164 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
165 SDTCVecEltisVT<0, f64>,
166 SDTCVecEltisVT<1, f32>,
167 SDTCVecEltisVT<2, f32>,
168 SDTCisOpSmallerThanOp<1, 0>,
171 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
172 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
173 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
174 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
175 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
177 def X86IntCmpMask : SDTypeProfile<1, 2,
178 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
179 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
180 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
183 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
186 def X86CmpMaskCCRound :
187 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
191 def X86CmpMaskCCScalar :
192 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
194 def X86CmpMaskCCScalarRound :
195 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
198 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
199 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
200 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
201 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
202 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
204 def X86vshl : SDNode<"X86ISD::VSHL",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 def X86vsrl : SDNode<"X86ISD::VSRL",
208 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 def X86vsra : SDNode<"X86ISD::VSRA",
211 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
215 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
216 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
218 def X86vprot : SDNode<"X86ISD::VPROT",
219 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 def X86vproti : SDNode<"X86ISD::VPROTI",
222 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 def X86vpshl : SDNode<"X86ISD::VPSHL",
226 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
228 def X86vpsha : SDNode<"X86ISD::VPSHA",
229 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
232 def X86vpcom : SDNode<"X86ISD::VPCOM",
233 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
235 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
236 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
237 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
239 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
241 SDTCisSameAs<2, 1>]>;
242 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
243 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
244 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
245 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
246 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
247 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
248 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
249 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
250 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
251 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
252 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
253 SDTCisVec<1>, SDTCisSameAs<2, 1>,
254 SDTCVecEltisVT<0, i1>,
255 SDTCisSameNumEltsAs<0, 1>]>>;
256 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
257 SDTCisVec<1>, SDTCisSameAs<2, 1>,
258 SDTCVecEltisVT<0, i1>,
259 SDTCisSameNumEltsAs<0, 1>]>>;
260 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
262 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
263 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
264 SDTCisSameAs<1,2>]>>;
265 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
266 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
267 SDTCisSameAs<1,2>]>>;
269 def X86extrqi : SDNode<"X86ISD::EXTRQI",
270 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
271 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
272 def X86insertqi : SDNode<"X86ISD::INSERTQI",
273 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
274 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
277 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
278 // translated into one of the target nodes below during lowering.
279 // Note: this is a work in progress...
280 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
281 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
283 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
284 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
286 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
288 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
289 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
290 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
291 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
292 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
293 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
294 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
295 SDTCisInt<2>, SDTCisInt<3>]>;
297 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
298 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
299 SDTCisInt<0>, SDTCisInt<1>]>;
301 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
302 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
304 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
305 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
308 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
309 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
311 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
312 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
314 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
315 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
316 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
317 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
318 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
319 SDTCisVec<0>, SDTCisInt<2>]>;
320 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
321 SDTCisVec<0>, SDTCisInt<3>]>;
322 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
323 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
325 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
326 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
328 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
329 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
331 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
332 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
333 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
335 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
336 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
338 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
339 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
340 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
342 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
343 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
345 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
346 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
347 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
349 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
350 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
352 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
353 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
354 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
356 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
357 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
359 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
360 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
362 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
363 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
364 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
365 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
366 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
367 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
368 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
370 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
372 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
373 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
374 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
375 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
376 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
377 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
378 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
379 SDTCisVec<1>, SDTCisInt<2>]>, []>;
380 def X86Vfpclasss : SDNode<"X86ISD::VFPCLASS", SDTypeProfile<1, 2, [SDTCisInt<0>,
381 SDTCisFP<1>, SDTCisInt<2>]>,[]>;
383 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
384 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
385 SDTCisSubVecOfVec<1, 0>]>, []>;
386 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
387 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
388 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>, []>;
390 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
391 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
392 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
393 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
394 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
395 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
397 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
399 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
401 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
402 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
403 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
404 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
405 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
406 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
407 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
408 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
409 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
410 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
411 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
413 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
414 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
415 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
416 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
417 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
418 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
420 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
421 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
422 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
423 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
424 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
425 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
427 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
428 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
429 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
431 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
432 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
433 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
434 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
435 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
437 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
438 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
440 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
441 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
442 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
445 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
446 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
448 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
449 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
450 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
451 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
453 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
454 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
456 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
457 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
458 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
459 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
461 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
462 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
463 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
464 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
465 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
466 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
467 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
468 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
469 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
470 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
472 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
473 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
476 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
477 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
479 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
480 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
484 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
485 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
487 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
488 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
489 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
490 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
491 // Vector with rounding mode
493 // cvtt fp-to-int staff
494 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
495 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
496 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
497 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
499 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
500 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
501 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
502 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
504 // cvt fp-to-int staff
505 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
506 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
507 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
508 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
510 // Vector without rounding mode
511 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
512 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
513 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
514 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
516 def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
517 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
518 SDTCVecEltisVT<0, f32>,
519 SDTCVecEltisVT<1, i16>,
520 SDTCisFP<0>, SDTCisInt<2>]> >;
522 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
523 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
524 SDTCVecEltisVT<0, i16>,
525 SDTCVecEltisVT<1, f32>,
526 SDTCisFP<1>, SDTCisInt<2>, SDTCisInt<3>]> >;
527 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
528 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
529 SDTCisFP<0>, SDTCisFP<1>,
530 SDTCisOpSmallerThanOp<1, 0>,
532 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
533 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
534 SDTCisFP<0>, SDTCisFP<1>,
535 SDTCVecEltisVT<0, f32>,
536 SDTCVecEltisVT<1, f64>,
539 //===----------------------------------------------------------------------===//
540 // SSE Complex Patterns
541 //===----------------------------------------------------------------------===//
543 // These are 'extloads' from a scalar to the low element of a vector, zeroing
544 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
546 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
547 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
549 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
550 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
553 def ssmem : Operand<v4f32> {
554 let PrintMethod = "printf32mem";
555 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
556 let ParserMatchClass = X86Mem32AsmOperand;
557 let OperandType = "OPERAND_MEMORY";
559 def sdmem : Operand<v2f64> {
560 let PrintMethod = "printf64mem";
561 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
562 let ParserMatchClass = X86Mem64AsmOperand;
563 let OperandType = "OPERAND_MEMORY";
566 //===----------------------------------------------------------------------===//
567 // SSE pattern fragments
568 //===----------------------------------------------------------------------===//
570 // 128-bit load pattern fragments
571 // NOTE: all 128-bit integer vector loads are promoted to v2i64
572 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
573 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
574 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
576 // 256-bit load pattern fragments
577 // NOTE: all 256-bit integer vector loads are promoted to v4i64
578 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
579 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
580 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
582 // 512-bit load pattern fragments
583 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
584 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
585 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
586 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
587 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
588 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
590 // 128-/256-/512-bit extload pattern fragments
591 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
592 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
593 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
595 // These are needed to match a scalar load that is used in a vector-only
596 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
597 // The memory operand is required to be a 128-bit load, so it must be converted
598 // from a vector to a scalar.
599 def loadf32_128 : PatFrag<(ops node:$ptr),
600 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
601 def loadf64_128 : PatFrag<(ops node:$ptr),
602 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
604 // Like 'store', but always requires 128-bit vector alignment.
605 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
606 (store node:$val, node:$ptr), [{
607 return cast<StoreSDNode>(N)->getAlignment() >= 16;
610 // Like 'store', but always requires 256-bit vector alignment.
611 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
612 (store node:$val, node:$ptr), [{
613 return cast<StoreSDNode>(N)->getAlignment() >= 32;
616 // Like 'store', but always requires 512-bit vector alignment.
617 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
618 (store node:$val, node:$ptr), [{
619 return cast<StoreSDNode>(N)->getAlignment() >= 64;
622 // Like 'load', but always requires 128-bit vector alignment.
623 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
624 return cast<LoadSDNode>(N)->getAlignment() >= 16;
627 // Like 'X86vzload', but always requires 128-bit vector alignment.
628 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
629 return cast<MemSDNode>(N)->getAlignment() >= 16;
632 // Like 'load', but always requires 256-bit vector alignment.
633 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
634 return cast<LoadSDNode>(N)->getAlignment() >= 32;
637 // Like 'load', but always requires 512-bit vector alignment.
638 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
639 return cast<LoadSDNode>(N)->getAlignment() >= 64;
642 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
643 (f32 (alignedload node:$ptr))>;
644 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
645 (f64 (alignedload node:$ptr))>;
647 // 128-bit aligned load pattern fragments
648 // NOTE: all 128-bit integer vector loads are promoted to v2i64
649 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
650 (v4f32 (alignedload node:$ptr))>;
651 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
652 (v2f64 (alignedload node:$ptr))>;
653 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
654 (v2i64 (alignedload node:$ptr))>;
656 // 256-bit aligned load pattern fragments
657 // NOTE: all 256-bit integer vector loads are promoted to v4i64
658 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
659 (v8f32 (alignedload256 node:$ptr))>;
660 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
661 (v4f64 (alignedload256 node:$ptr))>;
662 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
663 (v4i64 (alignedload256 node:$ptr))>;
665 // 512-bit aligned load pattern fragments
666 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
667 (v16f32 (alignedload512 node:$ptr))>;
668 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
669 (v16i32 (alignedload512 node:$ptr))>;
670 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
671 (v8f64 (alignedload512 node:$ptr))>;
672 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
673 (v8i64 (alignedload512 node:$ptr))>;
675 // Like 'load', but uses special alignment checks suitable for use in
676 // memory operands in most SSE instructions, which are required to
677 // be naturally aligned on some targets but not on others. If the subtarget
678 // allows unaligned accesses, match any load, though this may require
679 // setting a feature bit in the processor (on startup, for example).
680 // Opteron 10h and later implement such a feature.
681 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
682 return Subtarget->hasSSEUnalignedMem()
683 || cast<LoadSDNode>(N)->getAlignment() >= 16;
686 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
687 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
689 // 128-bit memop pattern fragments
690 // NOTE: all 128-bit integer vector loads are promoted to v2i64
691 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
692 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
693 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
695 // These are needed to match a scalar memop that is used in a vector-only
696 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
697 // The memory operand is required to be a 128-bit load, so it must be converted
698 // from a vector to a scalar.
699 def memopfsf32_128 : PatFrag<(ops node:$ptr),
700 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
701 def memopfsf64_128 : PatFrag<(ops node:$ptr),
702 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
705 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
707 // FIXME: 8 byte alignment for mmx reads is not required
708 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
709 return cast<LoadSDNode>(N)->getAlignment() >= 8;
712 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
714 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
715 (masked_gather node:$src1, node:$src2, node:$src3) , [{
716 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
717 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
718 Mgt->getBasePtr().getValueType() == MVT::v4i32);
722 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
723 (masked_gather node:$src1, node:$src2, node:$src3) , [{
724 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
725 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
726 Mgt->getBasePtr().getValueType() == MVT::v8i32);
730 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
731 (masked_gather node:$src1, node:$src2, node:$src3) , [{
732 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
733 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
734 Mgt->getBasePtr().getValueType() == MVT::v2i64);
737 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
738 (masked_gather node:$src1, node:$src2, node:$src3) , [{
739 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
740 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
741 Mgt->getBasePtr().getValueType() == MVT::v4i64);
744 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
745 (masked_gather node:$src1, node:$src2, node:$src3) , [{
746 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
747 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
748 Mgt->getBasePtr().getValueType() == MVT::v8i64);
751 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
752 (masked_gather node:$src1, node:$src2, node:$src3) , [{
753 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
754 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
755 Mgt->getBasePtr().getValueType() == MVT::v16i32);
759 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
760 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
761 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
762 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
763 Sc->getBasePtr().getValueType() == MVT::v2i64);
767 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
768 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
769 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
770 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
771 Sc->getBasePtr().getValueType() == MVT::v4i32);
775 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
776 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
777 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
778 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
779 Sc->getBasePtr().getValueType() == MVT::v4i64);
783 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
784 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
785 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
786 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
787 Sc->getBasePtr().getValueType() == MVT::v8i32);
791 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
792 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
793 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
794 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
795 Sc->getBasePtr().getValueType() == MVT::v8i64);
798 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
799 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
800 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
801 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
802 Sc->getBasePtr().getValueType() == MVT::v16i32);
806 // 128-bit bitconvert pattern fragments
807 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
808 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
809 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
810 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
811 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
812 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
814 // 256-bit bitconvert pattern fragments
815 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
816 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
817 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
818 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
819 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
821 // 512-bit bitconvert pattern fragments
822 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
823 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
824 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
825 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
827 def vzmovl_v2i64 : PatFrag<(ops node:$src),
828 (bitconvert (v2i64 (X86vzmovl
829 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
830 def vzmovl_v4i32 : PatFrag<(ops node:$src),
831 (bitconvert (v4i32 (X86vzmovl
832 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
834 def vzload_v2i64 : PatFrag<(ops node:$src),
835 (bitconvert (v2i64 (X86vzload node:$src)))>;
838 def fp32imm0 : PatLeaf<(f32 fpimm), [{
839 return N->isExactlyValue(+0.0);
842 def I8Imm : SDNodeXForm<imm, [{
843 // Transformation function: get the low 8 bits.
844 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
847 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
848 def FROUND_CURRENT : ImmLeaf<i32, [{
849 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
852 // BYTE_imm - Transform bit immediates into byte immediates.
853 def BYTE_imm : SDNodeXForm<imm, [{
854 // Transformation function: imm >> 3
855 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
858 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
859 // to VEXTRACTF128/VEXTRACTI128 imm.
860 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
861 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
864 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
865 // VINSERTF128/VINSERTI128 imm.
866 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
867 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
870 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
871 // to VEXTRACTF64x4 imm.
872 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
873 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
876 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
878 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
879 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
882 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
883 (extract_subvector node:$bigvec,
885 return X86::isVEXTRACT128Index(N);
886 }], EXTRACT_get_vextract128_imm>;
888 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
890 (insert_subvector node:$bigvec, node:$smallvec,
892 return X86::isVINSERT128Index(N);
893 }], INSERT_get_vinsert128_imm>;
896 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
897 (extract_subvector node:$bigvec,
899 return X86::isVEXTRACT256Index(N);
900 }], EXTRACT_get_vextract256_imm>;
902 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
904 (insert_subvector node:$bigvec, node:$smallvec,
906 return X86::isVINSERT256Index(N);
907 }], INSERT_get_vinsert256_imm>;
909 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
910 (masked_load node:$src1, node:$src2, node:$src3), [{
911 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
912 return Load->getAlignment() >= 16;
916 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
917 (masked_load node:$src1, node:$src2, node:$src3), [{
918 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
919 return Load->getAlignment() >= 32;
923 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
924 (masked_load node:$src1, node:$src2, node:$src3), [{
925 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
926 return Load->getAlignment() >= 64;
930 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
931 (masked_load node:$src1, node:$src2, node:$src3), [{
932 return isa<MaskedLoadSDNode>(N);
935 // masked store fragments.
936 // X86mstore can't be implemented in core DAG files because some targets
937 // doesn't support vector type ( llvm-tblgen will fail)
938 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
939 (masked_store node:$src1, node:$src2, node:$src3), [{
940 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
943 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
944 (X86mstore node:$src1, node:$src2, node:$src3), [{
945 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
946 return Store->getAlignment() >= 16;
950 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
951 (X86mstore node:$src1, node:$src2, node:$src3), [{
952 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
953 return Store->getAlignment() >= 32;
957 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
958 (X86mstore node:$src1, node:$src2, node:$src3), [{
959 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
960 return Store->getAlignment() >= 64;
964 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
965 (X86mstore node:$src1, node:$src2, node:$src3), [{
966 return isa<MaskedStoreSDNode>(N);
969 // masked truncstore fragments
970 // X86mtruncstore can't be implemented in core DAG files because some targets
971 // doesn't support vector type ( llvm-tblgen will fail)
972 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
973 (masked_store node:$src1, node:$src2, node:$src3), [{
974 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
976 def masked_truncstorevi8 :
977 PatFrag<(ops node:$src1, node:$src2, node:$src3),
978 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
979 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
981 def masked_truncstorevi16 :
982 PatFrag<(ops node:$src1, node:$src2, node:$src3),
983 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
984 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
986 def masked_truncstorevi32 :
987 PatFrag<(ops node:$src1, node:$src2, node:$src3),
988 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
989 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;