1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
32 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
38 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
39 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
40 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
41 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
42 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
43 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
44 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
45 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
46 def X86pshufb : SDNode<"X86ISD::PSHUFB",
47 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
49 def X86andnp : SDNode<"X86ISD::ANDNP",
50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
52 def X86psignb : SDNode<"X86ISD::PSIGNB",
53 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
55 def X86psignw : SDNode<"X86ISD::PSIGNW",
56 SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
58 def X86psignd : SDNode<"X86ISD::PSIGND",
59 SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
61 def X86pextrb : SDNode<"X86ISD::PEXTRB",
62 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
63 def X86pextrw : SDNode<"X86ISD::PEXTRW",
64 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
65 def X86pinsrb : SDNode<"X86ISD::PINSRB",
66 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
67 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
68 def X86pinsrw : SDNode<"X86ISD::PINSRW",
69 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
70 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
71 def X86insrtps : SDNode<"X86ISD::INSERTPS",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
73 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
74 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
75 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
76 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
77 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
78 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
79 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
80 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
81 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
82 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
83 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
84 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
85 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
86 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
87 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
88 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
89 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
91 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
94 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
95 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
97 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
98 // translated into one of the target nodes below during lowering.
99 // Note: this is a work in progress...
100 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
101 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
104 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
105 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
106 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
107 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
109 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
111 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
113 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
114 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
115 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
117 def X86Shufpd : SDNode<"X86ISD::SHUFPD", SDTShuff3OpI>;
118 def X86Shufps : SDNode<"X86ISD::SHUFPS", SDTShuff3OpI>;
120 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
121 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
122 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
124 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
125 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
127 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
128 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
129 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
130 def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
132 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
133 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
135 def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
136 def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
137 def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
138 def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
140 def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
141 def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
142 def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>;
143 def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>;
145 def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>;
146 def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>;
147 def X86Punpckldq : SDNode<"X86ISD::PUNPCKLDQ", SDTShuff2Op>;
148 def X86Punpcklqdq : SDNode<"X86ISD::PUNPCKLQDQ", SDTShuff2Op>;
150 def X86Punpckhbw : SDNode<"X86ISD::PUNPCKHBW", SDTShuff2Op>;
151 def X86Punpckhwd : SDNode<"X86ISD::PUNPCKHWD", SDTShuff2Op>;
152 def X86Punpckhdq : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>;
153 def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>;
155 def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>;
156 def X86VPermilpsy : SDNode<"X86ISD::VPERMILPSY", SDTShuff2OpI>;
157 def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>;
158 def X86VPermilpdy : SDNode<"X86ISD::VPERMILPDY", SDTShuff2OpI>;
160 def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
162 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
164 //===----------------------------------------------------------------------===//
165 // SSE Complex Patterns
166 //===----------------------------------------------------------------------===//
168 // These are 'extloads' from a scalar to the low element of a vector, zeroing
169 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
171 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
172 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
174 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
175 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
178 def ssmem : Operand<v4f32> {
179 let PrintMethod = "printf32mem";
180 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
181 let ParserMatchClass = X86MemAsmOperand;
182 let OperandType = "OPERAND_MEMORY";
184 def sdmem : Operand<v2f64> {
185 let PrintMethod = "printf64mem";
186 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
187 let ParserMatchClass = X86MemAsmOperand;
188 let OperandType = "OPERAND_MEMORY";
191 //===----------------------------------------------------------------------===//
192 // SSE pattern fragments
193 //===----------------------------------------------------------------------===//
195 // 128-bit load pattern fragments
196 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
197 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
198 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
199 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
201 // 256-bit load pattern fragments
202 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
203 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
204 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
205 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
207 // Like 'store', but always requires vector alignment.
208 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
209 (store node:$val, node:$ptr), [{
210 return cast<StoreSDNode>(N)->getAlignment() >= 16;
213 // Like 'load', but always requires vector alignment.
214 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
215 return cast<LoadSDNode>(N)->getAlignment() >= 16;
218 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
219 (f32 (alignedload node:$ptr))>;
220 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
221 (f64 (alignedload node:$ptr))>;
223 // 128-bit aligned load pattern fragments
224 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
225 (v4f32 (alignedload node:$ptr))>;
226 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
227 (v2f64 (alignedload node:$ptr))>;
228 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
229 (v4i32 (alignedload node:$ptr))>;
230 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
231 (v2i64 (alignedload node:$ptr))>;
233 // 256-bit aligned load pattern fragments
234 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
235 (v8f32 (alignedload node:$ptr))>;
236 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
237 (v4f64 (alignedload node:$ptr))>;
238 def alignedloadv8i32 : PatFrag<(ops node:$ptr),
239 (v8i32 (alignedload node:$ptr))>;
240 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
241 (v4i64 (alignedload node:$ptr))>;
243 // Like 'load', but uses special alignment checks suitable for use in
244 // memory operands in most SSE instructions, which are required to
245 // be naturally aligned on some targets but not on others. If the subtarget
246 // allows unaligned accesses, match any load, though this may require
247 // setting a feature bit in the processor (on startup, for example).
248 // Opteron 10h and later implement such a feature.
249 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
250 return Subtarget->hasVectorUAMem()
251 || cast<LoadSDNode>(N)->getAlignment() >= 16;
254 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
255 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
257 // 128-bit memop pattern fragments
258 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
259 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
260 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
261 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
262 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
263 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
265 // 256-bit memop pattern fragments
266 def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
267 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
268 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
269 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
270 def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>;
272 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
274 // FIXME: 8 byte alignment for mmx reads is not required
275 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
276 return cast<LoadSDNode>(N)->getAlignment() >= 8;
279 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
282 // Like 'store', but requires the non-temporal bit to be set
283 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
284 (st node:$val, node:$ptr), [{
285 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
286 return ST->isNonTemporal();
290 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
291 (st node:$val, node:$ptr), [{
292 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
293 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
294 ST->getAddressingMode() == ISD::UNINDEXED &&
295 ST->getAlignment() >= 16;
299 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
300 (st node:$val, node:$ptr), [{
301 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
302 return ST->isNonTemporal() &&
303 ST->getAlignment() < 16;
307 // 128-bit bitconvert pattern fragments
308 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
309 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
310 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
311 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
312 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
313 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
315 // 256-bit bitconvert pattern fragments
316 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
317 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
319 def vzmovl_v2i64 : PatFrag<(ops node:$src),
320 (bitconvert (v2i64 (X86vzmovl
321 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
322 def vzmovl_v4i32 : PatFrag<(ops node:$src),
323 (bitconvert (v4i32 (X86vzmovl
324 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
326 def vzload_v2i64 : PatFrag<(ops node:$src),
327 (bitconvert (v2i64 (X86vzload node:$src)))>;
330 def fp32imm0 : PatLeaf<(f32 fpimm), [{
331 return N->isExactlyValue(+0.0);
334 // BYTE_imm - Transform bit immediates into byte immediates.
335 def BYTE_imm : SDNodeXForm<imm, [{
336 // Transformation function: imm >> 3
337 return getI32Imm(N->getZExtValue() >> 3);
340 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
342 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
343 return getI8Imm(X86::getShuffleSHUFImmediate(N));
346 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
348 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
349 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
352 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
354 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
355 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
358 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
360 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
361 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
364 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
365 // to VEXTRACTF128 imm.
366 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
367 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
370 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
372 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
373 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
376 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
377 (vector_shuffle node:$lhs, node:$rhs), [{
378 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
379 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
382 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
383 (vector_shuffle node:$lhs, node:$rhs), [{
384 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
387 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
388 (vector_shuffle node:$lhs, node:$rhs), [{
389 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
392 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
393 (vector_shuffle node:$lhs, node:$rhs), [{
394 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
397 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
398 (vector_shuffle node:$lhs, node:$rhs), [{
399 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
402 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
403 (vector_shuffle node:$lhs, node:$rhs), [{
404 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
407 def movl : PatFrag<(ops node:$lhs, node:$rhs),
408 (vector_shuffle node:$lhs, node:$rhs), [{
409 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
412 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
413 (vector_shuffle node:$lhs, node:$rhs), [{
414 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
417 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
418 (vector_shuffle node:$lhs, node:$rhs), [{
419 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
422 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
423 (vector_shuffle node:$lhs, node:$rhs), [{
424 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
425 }], SHUFFLE_get_shuf_imm>;
427 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
428 (vector_shuffle node:$lhs, node:$rhs), [{
429 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
430 }], SHUFFLE_get_shuf_imm>;
432 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
433 (vector_shuffle node:$lhs, node:$rhs), [{
434 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
435 }], SHUFFLE_get_pshufhw_imm>;
437 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
438 (vector_shuffle node:$lhs, node:$rhs), [{
439 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
440 }], SHUFFLE_get_pshuflw_imm>;
442 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
443 (extract_subvector node:$bigvec,
445 return X86::isVEXTRACTF128Index(N);
446 }], EXTRACT_get_vextractf128_imm>;
448 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
450 (insert_subvector node:$bigvec, node:$smallvec,
452 return X86::isVINSERTF128Index(N);
453 }], INSERT_get_vinsertf128_imm>;