1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
62 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
64 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
65 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
66 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
67 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
68 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
69 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
70 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
71 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
73 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTCisVT<1, v4i32>]>>;
75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
85 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
86 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
87 def X86andnp : SDNode<"X86ISD::ANDNP",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86psign : SDNode<"X86ISD::PSIGN",
91 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
93 def X86pextrb : SDNode<"X86ISD::PEXTRB",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pextrw : SDNode<"X86ISD::PEXTRW",
96 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
97 def X86pinsrb : SDNode<"X86ISD::PINSRB",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86pinsrw : SDNode<"X86ISD::PINSRW",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
103 def X86insertps : SDNode<"X86ISD::INSERTPS",
104 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
105 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
106 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
107 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
109 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
110 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
112 def X86vzext : SDNode<"X86ISD::VZEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def X86vsext : SDNode<"X86ISD::VSEXT",
118 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
119 SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<1, 0>]>>;
122 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
123 SDTCisInt<0>, SDTCisInt<1>,
124 SDTCisOpSmallerThanOp<0, 1>]>;
126 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
127 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
128 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
130 def X86trunc : SDNode<"X86ISD::TRUNC",
131 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
132 SDTCisOpSmallerThanOp<0, 1>]>>;
133 def X86vfpext : SDNode<"X86ISD::VFPEXT",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<1, 0>]>>;
137 def X86vfpround: SDNode<"X86ISD::VFPROUND",
138 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
139 SDTCisFP<0>, SDTCisFP<1>,
140 SDTCisOpSmallerThanOp<0, 1>]>>;
142 def X86fround: SDNode<"X86ISD::VFPROUND",
143 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
144 SDTCVecEltisVT<0, f32>,
145 SDTCVecEltisVT<1, f64>,
146 SDTCVecEltisVT<2, f64>,
147 SDTCisOpSmallerThanOp<0, 1>]>>;
148 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
149 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
150 SDTCVecEltisVT<0, f32>,
151 SDTCVecEltisVT<1, f64>,
152 SDTCVecEltisVT<2, f64>,
153 SDTCisOpSmallerThanOp<0, 1>,
156 def X86fpext : SDNode<"X86ISD::VFPEXT",
157 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
158 SDTCVecEltisVT<0, f64>,
159 SDTCVecEltisVT<1, f32>,
160 SDTCVecEltisVT<2, f32>,
161 SDTCisOpSmallerThanOp<1, 0>]>>;
163 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
164 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
165 SDTCVecEltisVT<0, f64>,
166 SDTCVecEltisVT<1, f32>,
167 SDTCVecEltisVT<2, f32>,
168 SDTCisOpSmallerThanOp<1, 0>,
171 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
172 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
173 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
174 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
175 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
177 def X86IntCmpMask : SDTypeProfile<1, 2,
178 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
179 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
180 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
183 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
186 def X86CmpMaskCCRound :
187 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
191 def X86CmpMaskCCScalar :
192 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
194 def X86CmpMaskCCScalarRound :
195 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
198 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
199 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
200 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
201 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
202 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
204 def X86vshl : SDNode<"X86ISD::VSHL",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 def X86vsrl : SDNode<"X86ISD::VSRL",
208 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 def X86vsra : SDNode<"X86ISD::VSRA",
211 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
215 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
216 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
218 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
220 SDTCisSameAs<2, 1>]>;
221 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
222 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
223 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
224 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
225 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
226 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
227 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
228 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
229 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
230 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
231 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
232 SDTCisVec<1>, SDTCisSameAs<2, 1>,
233 SDTCVecEltisVT<0, i1>,
234 SDTCisSameNumEltsAs<0, 1>]>>;
235 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
236 SDTCisVec<1>, SDTCisSameAs<2, 1>,
237 SDTCVecEltisVT<0, i1>,
238 SDTCisSameNumEltsAs<0, 1>]>>;
239 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
241 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
242 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
243 SDTCisSameAs<1,2>]>>;
244 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
245 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
246 SDTCisSameAs<1,2>]>>;
248 def X86extrqi : SDNode<"X86ISD::EXTRQI",
249 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
250 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
251 def X86insertqi : SDNode<"X86ISD::INSERTQI",
252 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
253 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
256 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
257 // translated into one of the target nodes below during lowering.
258 // Note: this is a work in progress...
259 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
260 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
262 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
263 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
265 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
267 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
268 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
269 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
270 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
271 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
272 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
273 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
274 SDTCisInt<2>, SDTCisInt<3>]>;
276 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
277 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
279 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
280 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
282 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
283 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
285 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
286 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
288 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
289 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
290 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
291 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
292 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
293 SDTCisVec<0>, SDTCisInt<2>]>;
294 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
295 SDTCisVec<0>, SDTCisInt<3>]>;
296 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
297 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
299 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
300 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
302 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
303 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
305 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
306 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
307 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
309 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
310 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
312 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
313 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
314 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
316 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
317 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
319 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
320 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
321 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
323 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
324 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
326 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
327 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
328 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
330 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
331 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
333 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
334 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
336 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
337 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
338 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
339 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
340 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
341 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
343 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
345 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
346 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
347 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
348 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
349 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
350 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
351 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
352 SDTCisVec<1>, SDTCisInt<2>]>, []>;
354 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
355 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
356 SDTCisSubVecOfVec<1, 0>]>, []>;
357 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
358 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
359 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
360 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
361 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
363 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
365 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
367 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
368 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
369 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
370 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
371 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
372 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
373 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
374 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
375 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
376 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
377 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
379 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
380 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
381 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
382 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
383 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
384 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
386 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
387 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
388 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
389 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
390 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
391 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
393 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
394 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
395 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
397 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
398 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
399 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
400 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
401 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
403 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
404 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
406 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
407 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
408 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
411 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
412 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
414 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
415 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
416 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
417 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
419 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
420 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
422 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
423 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
424 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
425 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
427 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
428 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
429 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
430 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
431 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
432 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
433 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
434 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
435 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
436 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
438 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
439 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
442 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
443 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
445 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
446 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
450 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
451 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
453 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
454 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
455 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
456 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
457 // Vector with rounding mode
459 // cvtt fp-to-int staff
460 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
461 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
462 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
463 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
465 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
466 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
467 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
468 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
470 // cvt fp-to-int staff
471 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
472 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
473 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
474 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
476 // Vector without rounding mode
477 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
478 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
479 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
480 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
482 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
483 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
484 SDTCisFP<0>, SDTCisFP<1>,
485 SDTCisOpSmallerThanOp<1, 0>,
487 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
488 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
489 SDTCisFP<0>, SDTCisFP<1>,
490 SDTCVecEltisVT<0, f32>,
491 SDTCVecEltisVT<1, f64>,
494 //===----------------------------------------------------------------------===//
495 // SSE Complex Patterns
496 //===----------------------------------------------------------------------===//
498 // These are 'extloads' from a scalar to the low element of a vector, zeroing
499 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
501 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
502 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
504 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
505 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
508 def ssmem : Operand<v4f32> {
509 let PrintMethod = "printf32mem";
510 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
511 let ParserMatchClass = X86Mem32AsmOperand;
512 let OperandType = "OPERAND_MEMORY";
514 def sdmem : Operand<v2f64> {
515 let PrintMethod = "printf64mem";
516 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
517 let ParserMatchClass = X86Mem64AsmOperand;
518 let OperandType = "OPERAND_MEMORY";
521 //===----------------------------------------------------------------------===//
522 // SSE pattern fragments
523 //===----------------------------------------------------------------------===//
525 // 128-bit load pattern fragments
526 // NOTE: all 128-bit integer vector loads are promoted to v2i64
527 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
528 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
529 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
531 // 256-bit load pattern fragments
532 // NOTE: all 256-bit integer vector loads are promoted to v4i64
533 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
534 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
535 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
537 // 512-bit load pattern fragments
538 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
539 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
540 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
541 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
542 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
543 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
545 // 128-/256-/512-bit extload pattern fragments
546 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
547 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
548 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
550 // These are needed to match a scalar load that is used in a vector-only
551 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
552 // The memory operand is required to be a 128-bit load, so it must be converted
553 // from a vector to a scalar.
554 def loadf32_128 : PatFrag<(ops node:$ptr),
555 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
556 def loadf64_128 : PatFrag<(ops node:$ptr),
557 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
559 // Like 'store', but always requires 128-bit vector alignment.
560 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
561 (store node:$val, node:$ptr), [{
562 return cast<StoreSDNode>(N)->getAlignment() >= 16;
565 // Like 'store', but always requires 256-bit vector alignment.
566 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
567 (store node:$val, node:$ptr), [{
568 return cast<StoreSDNode>(N)->getAlignment() >= 32;
571 // Like 'store', but always requires 512-bit vector alignment.
572 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
573 (store node:$val, node:$ptr), [{
574 return cast<StoreSDNode>(N)->getAlignment() >= 64;
577 // Like 'load', but always requires 128-bit vector alignment.
578 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
579 return cast<LoadSDNode>(N)->getAlignment() >= 16;
582 // Like 'X86vzload', but always requires 128-bit vector alignment.
583 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
584 return cast<MemSDNode>(N)->getAlignment() >= 16;
587 // Like 'load', but always requires 256-bit vector alignment.
588 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
589 return cast<LoadSDNode>(N)->getAlignment() >= 32;
592 // Like 'load', but always requires 512-bit vector alignment.
593 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
594 return cast<LoadSDNode>(N)->getAlignment() >= 64;
597 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
598 (f32 (alignedload node:$ptr))>;
599 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
600 (f64 (alignedload node:$ptr))>;
602 // 128-bit aligned load pattern fragments
603 // NOTE: all 128-bit integer vector loads are promoted to v2i64
604 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
605 (v4f32 (alignedload node:$ptr))>;
606 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
607 (v2f64 (alignedload node:$ptr))>;
608 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
609 (v2i64 (alignedload node:$ptr))>;
611 // 256-bit aligned load pattern fragments
612 // NOTE: all 256-bit integer vector loads are promoted to v4i64
613 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
614 (v8f32 (alignedload256 node:$ptr))>;
615 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
616 (v4f64 (alignedload256 node:$ptr))>;
617 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
618 (v4i64 (alignedload256 node:$ptr))>;
620 // 512-bit aligned load pattern fragments
621 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
622 (v16f32 (alignedload512 node:$ptr))>;
623 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
624 (v16i32 (alignedload512 node:$ptr))>;
625 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
626 (v8f64 (alignedload512 node:$ptr))>;
627 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
628 (v8i64 (alignedload512 node:$ptr))>;
630 // Like 'load', but uses special alignment checks suitable for use in
631 // memory operands in most SSE instructions, which are required to
632 // be naturally aligned on some targets but not on others. If the subtarget
633 // allows unaligned accesses, match any load, though this may require
634 // setting a feature bit in the processor (on startup, for example).
635 // Opteron 10h and later implement such a feature.
636 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
637 return Subtarget->hasSSEUnalignedMem()
638 || cast<LoadSDNode>(N)->getAlignment() >= 16;
641 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
642 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
644 // 128-bit memop pattern fragments
645 // NOTE: all 128-bit integer vector loads are promoted to v2i64
646 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
647 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
648 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
650 // These are needed to match a scalar memop that is used in a vector-only
651 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
652 // The memory operand is required to be a 128-bit load, so it must be converted
653 // from a vector to a scalar.
654 def memopfsf32_128 : PatFrag<(ops node:$ptr),
655 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
656 def memopfsf64_128 : PatFrag<(ops node:$ptr),
657 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
660 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
662 // FIXME: 8 byte alignment for mmx reads is not required
663 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
664 return cast<LoadSDNode>(N)->getAlignment() >= 8;
667 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
669 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
670 (masked_gather node:$src1, node:$src2, node:$src3) , [{
671 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
672 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
673 Mgt->getBasePtr().getValueType() == MVT::v4i32);
677 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
678 (masked_gather node:$src1, node:$src2, node:$src3) , [{
679 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
680 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
681 Mgt->getBasePtr().getValueType() == MVT::v8i32);
685 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
686 (masked_gather node:$src1, node:$src2, node:$src3) , [{
687 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
688 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
689 Mgt->getBasePtr().getValueType() == MVT::v2i64);
692 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
693 (masked_gather node:$src1, node:$src2, node:$src3) , [{
694 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
695 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
696 Mgt->getBasePtr().getValueType() == MVT::v4i64);
699 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
700 (masked_gather node:$src1, node:$src2, node:$src3) , [{
701 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
702 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
703 Mgt->getBasePtr().getValueType() == MVT::v8i64);
706 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
707 (masked_gather node:$src1, node:$src2, node:$src3) , [{
708 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
709 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
710 Mgt->getBasePtr().getValueType() == MVT::v16i32);
714 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
715 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
716 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
717 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
718 Sc->getBasePtr().getValueType() == MVT::v2i64);
722 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
723 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
724 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
725 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
726 Sc->getBasePtr().getValueType() == MVT::v4i32);
730 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
731 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
732 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
733 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
734 Sc->getBasePtr().getValueType() == MVT::v4i64);
738 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
739 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
740 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
741 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
742 Sc->getBasePtr().getValueType() == MVT::v8i32);
746 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
747 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
748 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
749 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
750 Sc->getBasePtr().getValueType() == MVT::v8i64);
753 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
754 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
755 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
756 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
757 Sc->getBasePtr().getValueType() == MVT::v16i32);
761 // 128-bit bitconvert pattern fragments
762 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
763 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
764 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
765 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
766 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
767 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
769 // 256-bit bitconvert pattern fragments
770 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
771 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
772 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
773 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
774 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
776 // 512-bit bitconvert pattern fragments
777 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
778 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
779 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
780 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
782 def vzmovl_v2i64 : PatFrag<(ops node:$src),
783 (bitconvert (v2i64 (X86vzmovl
784 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
785 def vzmovl_v4i32 : PatFrag<(ops node:$src),
786 (bitconvert (v4i32 (X86vzmovl
787 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
789 def vzload_v2i64 : PatFrag<(ops node:$src),
790 (bitconvert (v2i64 (X86vzload node:$src)))>;
793 def fp32imm0 : PatLeaf<(f32 fpimm), [{
794 return N->isExactlyValue(+0.0);
797 def I8Imm : SDNodeXForm<imm, [{
798 // Transformation function: get the low 8 bits.
799 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
802 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
803 def FROUND_CURRENT : ImmLeaf<i32, [{
804 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
807 // BYTE_imm - Transform bit immediates into byte immediates.
808 def BYTE_imm : SDNodeXForm<imm, [{
809 // Transformation function: imm >> 3
810 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
813 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
814 // to VEXTRACTF128/VEXTRACTI128 imm.
815 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
816 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
819 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
820 // VINSERTF128/VINSERTI128 imm.
821 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
822 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
825 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
826 // to VEXTRACTF64x4 imm.
827 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
828 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
831 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
833 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
834 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
837 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
838 (extract_subvector node:$bigvec,
840 return X86::isVEXTRACT128Index(N);
841 }], EXTRACT_get_vextract128_imm>;
843 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
845 (insert_subvector node:$bigvec, node:$smallvec,
847 return X86::isVINSERT128Index(N);
848 }], INSERT_get_vinsert128_imm>;
851 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
852 (extract_subvector node:$bigvec,
854 return X86::isVEXTRACT256Index(N);
855 }], EXTRACT_get_vextract256_imm>;
857 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
859 (insert_subvector node:$bigvec, node:$smallvec,
861 return X86::isVINSERT256Index(N);
862 }], INSERT_get_vinsert256_imm>;
864 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
865 (masked_load node:$src1, node:$src2, node:$src3), [{
866 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
867 return Load->getAlignment() >= 16;
871 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
872 (masked_load node:$src1, node:$src2, node:$src3), [{
873 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
874 return Load->getAlignment() >= 32;
878 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
879 (masked_load node:$src1, node:$src2, node:$src3), [{
880 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
881 return Load->getAlignment() >= 64;
885 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
886 (masked_load node:$src1, node:$src2, node:$src3), [{
887 return isa<MaskedLoadSDNode>(N);
890 // masked store fragments.
891 // X86mstore can't be implemented in core DAG files because some targets
892 // doesn't support vector type ( llvm-tblgen will fail)
893 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
894 (masked_store node:$src1, node:$src2, node:$src3), [{
895 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
898 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
899 (X86mstore node:$src1, node:$src2, node:$src3), [{
900 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
901 return Store->getAlignment() >= 16;
905 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
906 (X86mstore node:$src1, node:$src2, node:$src3), [{
907 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
908 return Store->getAlignment() >= 32;
912 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
913 (X86mstore node:$src1, node:$src2, node:$src3), [{
914 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
915 return Store->getAlignment() >= 64;
919 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
920 (X86mstore node:$src1, node:$src2, node:$src3), [{
921 return isa<MaskedStoreSDNode>(N);
924 // masked truncstore fragments
925 // X86mtruncstore can't be implemented in core DAG files because some targets
926 // doesn't support vector type ( llvm-tblgen will fail)
927 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
928 (masked_store node:$src1, node:$src2, node:$src3), [{
929 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
931 def masked_truncstorevi8 :
932 PatFrag<(ops node:$src1, node:$src2, node:$src3),
933 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
934 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
936 def masked_truncstorevi16 :
937 PatFrag<(ops node:$src1, node:$src2, node:$src3),
938 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
939 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
941 def masked_truncstorevi32 :
942 PatFrag<(ops node:$src1, node:$src2, node:$src3),
943 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
944 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;