1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
32 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
38 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
39 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
40 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
41 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
42 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
43 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
44 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
45 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
46 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
47 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
48 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
49 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
50 def X86pshufb : SDNode<"X86ISD::PSHUFB",
51 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
53 def X86andnp : SDNode<"X86ISD::ANDNP",
54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
56 def X86psign : SDNode<"X86ISD::PSIGN",
57 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
59 def X86pextrb : SDNode<"X86ISD::PEXTRB",
60 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
61 def X86pextrw : SDNode<"X86ISD::PEXTRW",
62 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
63 def X86pinsrb : SDNode<"X86ISD::PINSRB",
64 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
65 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
66 def X86pinsrw : SDNode<"X86ISD::PINSRW",
67 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
68 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
69 def X86insrtps : SDNode<"X86ISD::INSERTPS",
70 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
71 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
72 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
73 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
74 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
75 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
76 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
77 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
78 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
79 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
80 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
81 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
82 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
83 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
84 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
85 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
86 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
87 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
89 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
92 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
93 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
95 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
96 // translated into one of the target nodes below during lowering.
97 // Note: this is a work in progress...
98 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
99 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
102 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
103 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
104 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
105 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
107 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
109 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
111 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
112 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
113 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
115 def X86Shufpd : SDNode<"X86ISD::SHUFPD", SDTShuff3OpI>;
116 def X86Shufps : SDNode<"X86ISD::SHUFPS", SDTShuff3OpI>;
118 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
119 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
120 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
122 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
123 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
125 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
126 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
127 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
128 def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
130 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
131 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
133 def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
134 def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
135 def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
136 def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
138 def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
139 def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
140 def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>;
141 def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>;
143 def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>;
144 def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>;
145 def X86Punpckldq : SDNode<"X86ISD::PUNPCKLDQ", SDTShuff2Op>;
146 def X86Punpcklqdq : SDNode<"X86ISD::PUNPCKLQDQ", SDTShuff2Op>;
147 def X86Punpcklwdy : SDNode<"X86ISD::VPUNPCKLWDY", SDTShuff2Op>;
148 def X86Punpckldqy : SDNode<"X86ISD::VPUNPCKLDQY", SDTShuff2Op>;
149 def X86Punpcklqdqy : SDNode<"X86ISD::VPUNPCKLQDQY", SDTShuff2Op>;
151 def X86Punpckhbw : SDNode<"X86ISD::PUNPCKHBW", SDTShuff2Op>;
152 def X86Punpckhwd : SDNode<"X86ISD::PUNPCKHWD", SDTShuff2Op>;
153 def X86Punpckhdq : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>;
154 def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>;
155 def X86Punpckhwdy : SDNode<"X86ISD::VPUNPCKHWDY", SDTShuff2Op>;
156 def X86Punpckhdqy : SDNode<"X86ISD::VPUNPCKHDQY", SDTShuff2Op>;
157 def X86Punpckhqdqy : SDNode<"X86ISD::VPUNPCKHQDQY", SDTShuff2Op>;
159 def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>;
160 def X86VPermilpsy : SDNode<"X86ISD::VPERMILPSY", SDTShuff2OpI>;
161 def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>;
162 def X86VPermilpdy : SDNode<"X86ISD::VPERMILPDY", SDTShuff2OpI>;
164 def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
166 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
168 //===----------------------------------------------------------------------===//
169 // SSE Complex Patterns
170 //===----------------------------------------------------------------------===//
172 // These are 'extloads' from a scalar to the low element of a vector, zeroing
173 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
175 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
176 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
178 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
179 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
182 def ssmem : Operand<v4f32> {
183 let PrintMethod = "printf32mem";
184 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
185 let ParserMatchClass = X86MemAsmOperand;
186 let OperandType = "OPERAND_MEMORY";
188 def sdmem : Operand<v2f64> {
189 let PrintMethod = "printf64mem";
190 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
191 let ParserMatchClass = X86MemAsmOperand;
192 let OperandType = "OPERAND_MEMORY";
195 //===----------------------------------------------------------------------===//
196 // SSE pattern fragments
197 //===----------------------------------------------------------------------===//
199 // 128-bit load pattern fragments
200 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
201 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
202 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
203 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
205 // 256-bit load pattern fragments
206 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
207 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
208 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
209 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
211 // Like 'store', but always requires 128-bit vector alignment.
212 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
213 (store node:$val, node:$ptr), [{
214 return cast<StoreSDNode>(N)->getAlignment() >= 16;
217 // Like 'store', but always requires 256-bit vector alignment.
218 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
219 (store node:$val, node:$ptr), [{
220 return cast<StoreSDNode>(N)->getAlignment() >= 32;
223 // Like 'load', but always requires 128-bit vector alignment.
224 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
225 return cast<LoadSDNode>(N)->getAlignment() >= 16;
228 // Like 'load', but always requires 256-bit vector alignment.
229 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
230 return cast<LoadSDNode>(N)->getAlignment() >= 32;
233 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
234 (f32 (alignedload node:$ptr))>;
235 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
236 (f64 (alignedload node:$ptr))>;
238 // 128-bit aligned load pattern fragments
239 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
240 (v4f32 (alignedload node:$ptr))>;
241 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
242 (v2f64 (alignedload node:$ptr))>;
243 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
244 (v4i32 (alignedload node:$ptr))>;
245 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
246 (v2i64 (alignedload node:$ptr))>;
248 // 256-bit aligned load pattern fragments
249 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
250 (v8f32 (alignedload256 node:$ptr))>;
251 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
252 (v4f64 (alignedload256 node:$ptr))>;
253 def alignedloadv8i32 : PatFrag<(ops node:$ptr),
254 (v8i32 (alignedload256 node:$ptr))>;
255 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
256 (v4i64 (alignedload256 node:$ptr))>;
258 // Like 'load', but uses special alignment checks suitable for use in
259 // memory operands in most SSE instructions, which are required to
260 // be naturally aligned on some targets but not on others. If the subtarget
261 // allows unaligned accesses, match any load, though this may require
262 // setting a feature bit in the processor (on startup, for example).
263 // Opteron 10h and later implement such a feature.
264 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
265 return Subtarget->hasVectorUAMem()
266 || cast<LoadSDNode>(N)->getAlignment() >= 16;
269 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
270 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
272 // 128-bit memop pattern fragments
273 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
274 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
275 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
276 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
277 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
278 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
280 // 256-bit memop pattern fragments
281 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
282 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
283 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
284 def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>;
285 def memopv16i16 : PatFrag<(ops node:$ptr), (v16i16 (memop node:$ptr))>;
286 def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
288 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
290 // FIXME: 8 byte alignment for mmx reads is not required
291 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
292 return cast<LoadSDNode>(N)->getAlignment() >= 8;
295 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
298 // Like 'store', but requires the non-temporal bit to be set
299 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
300 (st node:$val, node:$ptr), [{
301 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
302 return ST->isNonTemporal();
306 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
307 (st node:$val, node:$ptr), [{
308 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
309 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
310 ST->getAddressingMode() == ISD::UNINDEXED &&
311 ST->getAlignment() >= 16;
315 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
316 (st node:$val, node:$ptr), [{
317 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
318 return ST->isNonTemporal() &&
319 ST->getAlignment() < 16;
323 // 128-bit bitconvert pattern fragments
324 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
325 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
326 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
327 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
328 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
329 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
331 // 256-bit bitconvert pattern fragments
332 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
333 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
334 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
335 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
337 def vzmovl_v2i64 : PatFrag<(ops node:$src),
338 (bitconvert (v2i64 (X86vzmovl
339 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
340 def vzmovl_v4i32 : PatFrag<(ops node:$src),
341 (bitconvert (v4i32 (X86vzmovl
342 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
344 def vzload_v2i64 : PatFrag<(ops node:$src),
345 (bitconvert (v2i64 (X86vzload node:$src)))>;
348 def fp32imm0 : PatLeaf<(f32 fpimm), [{
349 return N->isExactlyValue(+0.0);
352 // BYTE_imm - Transform bit immediates into byte immediates.
353 def BYTE_imm : SDNodeXForm<imm, [{
354 // Transformation function: imm >> 3
355 return getI32Imm(N->getZExtValue() >> 3);
358 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
360 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
361 return getI8Imm(X86::getShuffleSHUFImmediate(N));
364 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
366 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
367 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
370 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
372 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
373 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
376 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
378 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
379 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
382 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
383 // to VEXTRACTF128 imm.
384 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
385 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
388 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
390 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
391 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
394 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
395 (vector_shuffle node:$lhs, node:$rhs), [{
396 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
397 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
400 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
401 (vector_shuffle node:$lhs, node:$rhs), [{
402 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
405 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
406 (vector_shuffle node:$lhs, node:$rhs), [{
407 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
410 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
411 (vector_shuffle node:$lhs, node:$rhs), [{
412 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
415 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
416 (vector_shuffle node:$lhs, node:$rhs), [{
417 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
420 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
421 (vector_shuffle node:$lhs, node:$rhs), [{
422 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
425 def movl : PatFrag<(ops node:$lhs, node:$rhs),
426 (vector_shuffle node:$lhs, node:$rhs), [{
427 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
430 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
431 (vector_shuffle node:$lhs, node:$rhs), [{
432 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
435 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
436 (vector_shuffle node:$lhs, node:$rhs), [{
437 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
440 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
441 (vector_shuffle node:$lhs, node:$rhs), [{
442 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
443 }], SHUFFLE_get_shuf_imm>;
445 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
446 (vector_shuffle node:$lhs, node:$rhs), [{
447 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
448 }], SHUFFLE_get_shuf_imm>;
450 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
451 (vector_shuffle node:$lhs, node:$rhs), [{
452 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
453 }], SHUFFLE_get_pshufhw_imm>;
455 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
456 (vector_shuffle node:$lhs, node:$rhs), [{
457 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
458 }], SHUFFLE_get_pshuflw_imm>;
460 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
461 (extract_subvector node:$bigvec,
463 return X86::isVEXTRACTF128Index(N);
464 }], EXTRACT_get_vextractf128_imm>;
466 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
468 (insert_subvector node:$bigvec, node:$smallvec,
470 return X86::isVINSERTF128Index(N);
471 }], INSERT_get_vinsertf128_imm>;