1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
31 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
32 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
33 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
35 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
36 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
38 // Commutative and Associative FMIN and FMAX.
39 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
44 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
45 [SDNPCommutative, SDNPAssociative]>;
46 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
52 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
53 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
54 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
55 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
56 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
57 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
58 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
59 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
60 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
61 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
62 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
63 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
64 def X86pshufb : SDNode<"X86ISD::PSHUFB",
65 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
67 def X86andnp : SDNode<"X86ISD::ANDNP",
68 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
70 def X86psign : SDNode<"X86ISD::PSIGN",
71 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
73 def X86pextrb : SDNode<"X86ISD::PEXTRB",
74 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
75 def X86pextrw : SDNode<"X86ISD::PEXTRW",
76 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
77 def X86pinsrb : SDNode<"X86ISD::PINSRB",
78 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
79 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
80 def X86pinsrw : SDNode<"X86ISD::PINSRW",
81 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
82 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
83 def X86insrtps : SDNode<"X86ISD::INSERTPS",
84 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
85 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
86 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
87 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
89 def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL",
90 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
91 SDTCisOpSmallerThanOp<1, 0> ]>>;
93 def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
95 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
97 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
98 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
100 def X86vzext : SDNode<"X86ISD::VZEXT",
101 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
102 SDTCisInt<0>, SDTCisInt<1>]>>;
104 def X86vsext : SDNode<"X86ISD::VSEXT",
105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106 SDTCisInt<0>, SDTCisInt<1>]>>;
108 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
109 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
110 SDTCisInt<0>, SDTCisInt<1>]>>;
111 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
112 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisVec<2>, SDTCisInt<2>]>>;
115 def X86vfpext : SDNode<"X86ISD::VFPEXT",
116 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117 SDTCisFP<0>, SDTCisFP<1>]>>;
118 def X86vfpround: SDNode<"X86ISD::VFPROUND",
119 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
120 SDTCisFP<0>, SDTCisFP<1>]>>;
122 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
123 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
124 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
125 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
126 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
128 def X86IntCmpMask : SDTypeProfile<1, 2,
129 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
130 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
131 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
133 def X86CmpMaskCC : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
134 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
135 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
137 def X86vshl : SDNode<"X86ISD::VSHL",
138 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
140 def X86vsrl : SDNode<"X86ISD::VSRL",
141 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
143 def X86vsra : SDNode<"X86ISD::VSRA",
144 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
147 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
148 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
149 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
151 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
153 SDTCisSameAs<2, 1>]>;
154 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
155 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
156 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
157 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
158 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
159 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
161 SDTCisSameAs<2, 1>]>>;
163 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
164 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
165 SDTCisSameAs<1,2>]>>;
167 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
168 // translated into one of the target nodes below during lowering.
169 // Note: this is a work in progress...
170 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
171 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
173 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
174 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
176 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
177 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
178 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
179 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
181 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
182 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
184 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
185 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
187 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
188 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
190 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
192 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
193 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
194 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
196 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
198 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
199 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
200 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
202 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
203 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
205 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
206 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
207 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
209 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
210 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
212 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
213 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
215 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
216 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
217 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
218 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
220 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
222 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
223 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
224 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
225 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
227 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
228 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
229 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
230 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
231 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
232 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
233 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
235 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
236 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
238 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
239 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
240 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
243 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
244 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
246 //===----------------------------------------------------------------------===//
247 // SSE Complex Patterns
248 //===----------------------------------------------------------------------===//
250 // These are 'extloads' from a scalar to the low element of a vector, zeroing
251 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
253 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
254 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
256 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
257 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
260 def ssmem : Operand<v4f32> {
261 let PrintMethod = "printf32mem";
262 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
263 let ParserMatchClass = X86Mem32AsmOperand;
264 let OperandType = "OPERAND_MEMORY";
266 def sdmem : Operand<v2f64> {
267 let PrintMethod = "printf64mem";
268 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
269 let ParserMatchClass = X86Mem64AsmOperand;
270 let OperandType = "OPERAND_MEMORY";
273 //===----------------------------------------------------------------------===//
274 // SSE pattern fragments
275 //===----------------------------------------------------------------------===//
277 // 128-bit load pattern fragments
278 // NOTE: all 128-bit integer vector loads are promoted to v2i64
279 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
280 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
281 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
283 // 256-bit load pattern fragments
284 // NOTE: all 256-bit integer vector loads are promoted to v4i64
285 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
286 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
287 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
289 // 512-bit load pattern fragments
290 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
291 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
292 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
294 // 128-/256-/512-bit extload pattern fragments
295 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
296 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
297 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
299 // Like 'store', but always requires 128-bit vector alignment.
300 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 16;
305 // Like 'store', but always requires 256-bit vector alignment.
306 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
307 (store node:$val, node:$ptr), [{
308 return cast<StoreSDNode>(N)->getAlignment() >= 32;
311 // Like 'store', but always requires 512-bit vector alignment.
312 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
313 (store node:$val, node:$ptr), [{
314 return cast<StoreSDNode>(N)->getAlignment() >= 64;
317 // Like 'load', but always requires 128-bit vector alignment.
318 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
319 return cast<LoadSDNode>(N)->getAlignment() >= 16;
322 // Like 'X86vzload', but always requires 128-bit vector alignment.
323 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
324 return cast<MemSDNode>(N)->getAlignment() >= 16;
327 // Like 'load', but always requires 256-bit vector alignment.
328 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() >= 32;
332 // Like 'load', but always requires 512-bit vector alignment.
333 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
334 return cast<LoadSDNode>(N)->getAlignment() >= 64;
337 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
338 (f32 (alignedload node:$ptr))>;
339 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
340 (f64 (alignedload node:$ptr))>;
342 // 128-bit aligned load pattern fragments
343 // NOTE: all 128-bit integer vector loads are promoted to v2i64
344 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
345 (v4f32 (alignedload node:$ptr))>;
346 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
347 (v2f64 (alignedload node:$ptr))>;
348 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
349 (v2i64 (alignedload node:$ptr))>;
351 // 256-bit aligned load pattern fragments
352 // NOTE: all 256-bit integer vector loads are promoted to v4i64
353 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
354 (v8f32 (alignedload256 node:$ptr))>;
355 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
356 (v4f64 (alignedload256 node:$ptr))>;
357 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
358 (v4i64 (alignedload256 node:$ptr))>;
360 // 512-bit aligned load pattern fragments
361 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
362 (v16f32 (alignedload512 node:$ptr))>;
363 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
364 (v16i32 (alignedload512 node:$ptr))>;
365 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
366 (v8f64 (alignedload512 node:$ptr))>;
367 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
368 (v8i64 (alignedload512 node:$ptr))>;
370 // Like 'load', but uses special alignment checks suitable for use in
371 // memory operands in most SSE instructions, which are required to
372 // be naturally aligned on some targets but not on others. If the subtarget
373 // allows unaligned accesses, match any load, though this may require
374 // setting a feature bit in the processor (on startup, for example).
375 // Opteron 10h and later implement such a feature.
376 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
377 return Subtarget->hasVectorUAMem()
378 || cast<LoadSDNode>(N)->getAlignment() >= 16;
381 def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
382 return Subtarget->hasVectorUAMem()
383 || cast<LoadSDNode>(N)->getAlignment() >= 4;
386 def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
387 return Subtarget->hasVectorUAMem()
388 || cast<LoadSDNode>(N)->getAlignment() >= 8;
391 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
392 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
394 // 128-bit memop pattern fragments
395 // NOTE: all 128-bit integer vector loads are promoted to v2i64
396 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
397 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
398 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
400 // 256-bit memop pattern fragments
401 // NOTE: all 256-bit integer vector loads are promoted to v4i64
402 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
403 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
404 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
406 // 512-bit memop pattern fragments
407 def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>;
408 def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>;
409 def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>;
410 def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>;
412 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
414 // FIXME: 8 byte alignment for mmx reads is not required
415 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() >= 8;
419 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
422 // Like 'store', but requires the non-temporal bit to be set
423 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
424 (st node:$val, node:$ptr), [{
425 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
426 return ST->isNonTemporal();
430 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
431 (st node:$val, node:$ptr), [{
432 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
433 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
434 ST->getAddressingMode() == ISD::UNINDEXED &&
435 ST->getAlignment() >= 16;
439 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
440 (st node:$val, node:$ptr), [{
441 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
442 return ST->isNonTemporal() &&
443 ST->getAlignment() < 16;
447 // 128-bit bitconvert pattern fragments
448 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
449 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
450 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
451 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
452 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
453 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
455 // 256-bit bitconvert pattern fragments
456 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
457 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
458 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
459 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
461 // 512-bit bitconvert pattern fragments
462 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
463 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
465 def vzmovl_v2i64 : PatFrag<(ops node:$src),
466 (bitconvert (v2i64 (X86vzmovl
467 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
468 def vzmovl_v4i32 : PatFrag<(ops node:$src),
469 (bitconvert (v4i32 (X86vzmovl
470 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
472 def vzload_v2i64 : PatFrag<(ops node:$src),
473 (bitconvert (v2i64 (X86vzload node:$src)))>;
476 def fp32imm0 : PatLeaf<(f32 fpimm), [{
477 return N->isExactlyValue(+0.0);
480 // BYTE_imm - Transform bit immediates into byte immediates.
481 def BYTE_imm : SDNodeXForm<imm, [{
482 // Transformation function: imm >> 3
483 return getI32Imm(N->getZExtValue() >> 3);
486 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
487 // to VEXTRACTF128/VEXTRACTI128 imm.
488 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
489 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
492 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
493 // VINSERTF128/VINSERTI128 imm.
494 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
495 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
498 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
499 // to VEXTRACTF64x4 imm.
500 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
501 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
504 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
506 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
507 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
510 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
511 (extract_subvector node:$bigvec,
513 return X86::isVEXTRACT128Index(N);
514 }], EXTRACT_get_vextract128_imm>;
516 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
518 (insert_subvector node:$bigvec, node:$smallvec,
520 return X86::isVINSERT128Index(N);
521 }], INSERT_get_vinsert128_imm>;
524 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
525 (extract_subvector node:$bigvec,
527 return X86::isVEXTRACT256Index(N);
528 }], EXTRACT_get_vextract256_imm>;
530 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
532 (insert_subvector node:$bigvec, node:$smallvec,
534 return X86::isVINSERT256Index(N);
535 }], INSERT_get_vinsert256_imm>;