lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32 def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
  33
  34 //===----------------------------------------------------------------------===//
  35 // SSE specific DAG Nodes.
  36 //===----------------------------------------------------------------------===//
  37
  38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
  39                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  40                                        SDTCisVec<1>]>;
  41 def SDTX86CmpTestSae : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
  42                                      SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
  43
  44 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  45 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  46
  47 // Commutative and Associative FMIN and FMAX.
  48 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  49     [SDNPCommutative, SDNPAssociative]>;
  50 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  51     [SDNPCommutative, SDNPAssociative]>;
  52
  53 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  56                         [SDNPCommutative, SDNPAssociative]>;
  57 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  58                         [SDNPCommutative, SDNPAssociative]>;
  59 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
  60                         [SDNPCommutative, SDNPAssociative]>;
  61 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  62 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  63 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT",  SDTFPBinOp>;
  64 def X86frcp14s : SDNode<"X86ISD::FRCP",    SDTFPBinOp>;
  65 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
  66 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  67 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  68 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  69 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  70 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  71 def X86comiSae : SDNode<"X86ISD::COMI",      SDTX86CmpTestSae>;
  72 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  73 def X86ucomiSae: SDNode<"X86ISD::UCOMI",     SDTX86CmpTestSae>;
  74 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  75 //def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
  76 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
  77                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  78                                       SDTCisVT<1, v4i32>]>>;
  79 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
  80                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  81                                       SDTCisVT<1, v4i32>]>>;
  82 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  83                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  84                                       SDTCisSameAs<0,2>]>>;
  85 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  86                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  87                                       SDTCVecEltisVT<1, i8>,
  88                                       SDTCisSameSizeAs<0,1>,
  89                                       SDTCisSameAs<1,2>]>>;
  90 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  91                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  92                                        SDTCVecEltisVT<1, i8>,
  93                                        SDTCisSameSizeAs<0,1>,
  94                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  95 def X86andnp   : SDNode<"X86ISD::ANDNP",
  96                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  97                                       SDTCisSameAs<0,2>]>>;
  98 def X86psign   : SDNode<"X86ISD::PSIGN",
  99                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 100                                       SDTCisSameAs<0,2>]>>;
 101 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
 102                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
 103                                       SDTCisPtrTy<2>]>>;
 104 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
 105                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
 106                                       SDTCisPtrTy<2>]>>;
 107 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
 108                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 109                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 110 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
 111                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 112                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 113 def X86insertps : SDNode<"X86ISD::INSERTPS",
 114                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 115                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 116 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 117                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 118
 119 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 120                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 121
 122 def X86vzext   : SDNode<"X86ISD::VZEXT",
 123                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 124                                               SDTCisInt<0>, SDTCisInt<1>,
 125                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 126
 127 def X86vsext   : SDNode<"X86ISD::VSEXT",
 128                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 129                                               SDTCisInt<0>, SDTCisInt<1>,
 130                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 131
 132 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 133                                        SDTCisInt<0>, SDTCisInt<1>,
 134                                        SDTCisOpSmallerThanOp<0, 1>]>;
 135
 136 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 137 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 138 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 139
 140 def X86trunc    : SDNode<"X86ISD::TRUNC",
 141                          SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
 142                                               SDTCisOpSmallerThanOp<0, 1>]>>;
 143 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 144                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 145                                              SDTCisFP<0>, SDTCisFP<1>,
 146                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 147 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 148                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 149                                              SDTCisFP<0>, SDTCisFP<1>,
 150                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 151
 152 def X86fround: SDNode<"X86ISD::VFPROUND",
 153                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 154                                              SDTCVecEltisVT<0, f32>,
 155                                              SDTCVecEltisVT<1, f64>,
 156                                              SDTCVecEltisVT<2, f64>,
 157                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 158 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
 159                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 160                                              SDTCVecEltisVT<0, f32>,
 161                                              SDTCVecEltisVT<1, f64>,
 162                                              SDTCVecEltisVT<2, f64>,
 163                                              SDTCisOpSmallerThanOp<0, 1>,
 164                                              SDTCisInt<3>]>>;
 165
 166 def X86fpext  : SDNode<"X86ISD::VFPEXT",
 167                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 168                                              SDTCVecEltisVT<0, f64>,
 169                                              SDTCVecEltisVT<1, f32>,
 170                                              SDTCVecEltisVT<2, f32>,
 171                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 172
 173 def X86fpextRnd  : SDNode<"X86ISD::VFPEXT",
 174                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 175                                              SDTCVecEltisVT<0, f64>,
 176                                              SDTCVecEltisVT<1, f32>,
 177                                              SDTCVecEltisVT<2, f32>,
 178                                              SDTCisOpSmallerThanOp<1, 0>,
 179                                              SDTCisInt<3>]>>;
 180
 181 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 182 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 183 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 184 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 185 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 186
 187 def X86IntCmpMask : SDTypeProfile<1, 2,
 188     [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
 189 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 190 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 191
 192 def X86CmpMaskCC :
 193       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 194                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 195                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 196 def X86CmpMaskCCRound :
 197       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 198                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 199                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 200                        SDTCisInt<4>]>;
 201 def X86CmpMaskCCScalar :
 202       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 203
 204 def X86CmpMaskCCScalarRound :
 205       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 206                            SDTCisInt<4>]>;
 207
 208 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 209 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 210 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 211 def X86cmpms    : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalar>;
 212 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalarRound>;
 213
 214 def X86vshl    : SDNode<"X86ISD::VSHL",
 215                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 216                                       SDTCisVec<2>]>>;
 217 def X86vsrl    : SDNode<"X86ISD::VSRL",
 218                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 219                                       SDTCisVec<2>]>>;
 220 def X86vsra    : SDNode<"X86ISD::VSRA",
 221                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 222                                       SDTCisVec<2>]>>;
 223
 224 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 225 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 226 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 227
 228 def X86vrotli  : SDNode<"X86ISD::VROTLI", SDTIntShiftOp>;
 229
 230 def X86vprot   : SDNode<"X86ISD::VPROT",
 231                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 232                                              SDTCisSameAs<0,2>]>>;
 233 def X86vproti  : SDNode<"X86ISD::VPROTI",
 234                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 235                                              SDTCisVT<2, i8>]>>;
 236
 237 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 238                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 239                                              SDTCisSameAs<0,2>]>>;
 240 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 241                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 242                                              SDTCisSameAs<0,2>]>>;
 243
 244 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 245                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 246                                              SDTCisSameAs<0,2>,
 247                                              SDTCisVT<3, i8>]>>;
 248 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 249                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 250                                              SDTCisSameAs<0,2>,
 251                                              SDTCisVT<3, i8>]>>;
 252
 253 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 254                                           SDTCisVec<1>,
 255                                           SDTCisSameAs<2, 1>]>;
 256 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
 257 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 258 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
 259 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 260 def X86mulhrs  : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
 261 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
 262 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 263 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 264 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 265 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 266 def X86testm   : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 267                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 268                                           SDTCVecEltisVT<0, i1>,
 269                                           SDTCisSameNumEltsAs<0, 1>]>>;
 270 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 271                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 272                                           SDTCVecEltisVT<0, i1>,
 273                                           SDTCisSameNumEltsAs<0, 1>]>>;
 274 def X86select  : SDNode<"X86ISD::SELECT"     , SDTSelect>;
 275
 276 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 277                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 278                                              SDTCVecEltisVT<1, i32>,
 279                                              SDTCisSameSizeAs<0,1>,
 280                                              SDTCisSameAs<1,2>]>>;
 281 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 282                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 283                                              SDTCVecEltisVT<1, i32>,
 284                                              SDTCisSameSizeAs<0,1>,
 285                                              SDTCisSameAs<1,2>]>>;
 286
 287 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 288                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 289                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 290 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 291                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 292                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 293                                          SDTCisVT<4, i8>]>>;
 294
 295 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 296 // translated into one of the target nodes below during lowering.
 297 // Note: this is a work in progress...
 298 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 299 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 300                                 SDTCisSameAs<0,2>]>;
 301
 302 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 303                                         SDTCisSameSizeAs<0,2>,
 304                                         SDTCisSameNumEltsAs<0,2>]>;
 305 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 306                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 307 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 308                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 309 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 310                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
 311 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 312                               SDTCisInt<2>, SDTCisInt<3>]>;
 313
 314 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 315 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 316                                           SDTCisInt<0>, SDTCisInt<1>]>;
 317
 318 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 319                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 320
 321 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 322                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
 323                                 SDTCisVT<4, i8>]>;
 324
 325 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 326   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
 327
 328 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 329   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
 330
 331 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 332                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 333 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 334                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
 335 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
 336                            SDTCisVec<0>, SDTCisVT<2, i32>]>;
 337 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 338                            SDTCisVec<0>, SDTCisVT<3, i32>]>;
 339 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 340                            SDTCisVec<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
 341
 342 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 343 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 344
 345 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 346 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 347
 348 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 349 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 350 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 351
 352 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 353 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 354
 355 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 356 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 357 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 358
 359 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 360 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 361
 362 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 363 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 364 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 365
 366 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 367 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 368
 369 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 370                                    SDTCisSameSizeAs<0,1>,
 371                                    SDTCisSameAs<1,2>]>;
 372 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 373 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 374
 375 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 376 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 377
 378 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 379 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack>;
 380
 381 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 382 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 383 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 384                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 385                                                 SDTCisSameNumEltsAs<0,1>,
 386                                                 SDTCisSameSizeAs<0,1>,
 387                                                 SDTCisSameAs<0,2>]>>;
 388 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 389 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 390                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 391                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 392                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 393                                          SDTCisSameSizeAs<0,2>,
 394                                          SDTCisSameAs<0,3>]>, []>;
 395
 396 def X86VPermi2X   : SDNode<"X86ISD::VPERMIV3",
 397                     SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>,
 398                                          SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>,
 399                                          SDTCisSameSizeAs<0,1>,
 400                                          SDTCisSameAs<0,2>,
 401                                          SDTCisSameAs<0,3>]>, []>;
 402
 403 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 404
 405 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 406
 407 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 408 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 409 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 410 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 411 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 412 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 413                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 414                                             SDTCisVec<1>, SDTCisFP<1>,
 415                                             SDTCisSameNumEltsAs<0,1>,
 416                                             SDTCisVT<2, i32>]>, []>;
 417 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 418                        SDTypeProfile<1, 2, [SDTCisVT<0, i1>,
 419                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 420
 421 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 422                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 423                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 424 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
 425 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 426                     SDTypeProfile<1, 1, [SDTCisVec<0>,
 427                                          SDTCisSameAs<0,1>]>, []>;
 428
 429 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 430 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 431 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 432                               [SDTCisSameAs<0, 1>, SDTCisEltOfVec<2, 1>,
 433                                SDTCisPtrTy<3>]>, []>;
 434 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 435                               [SDTCisEltOfVec<0, 1>, SDTCisVec<1>,
 436                                SDTCisPtrTy<2>]>, []>;
 437
 438 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 439
 440 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 441
 442 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 443 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 444 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 445 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 446 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 447 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 448 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 449 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 450 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRT_RND",   STDFp2SrcRm>;
 451 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 452 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
 453
 454 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 455 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 456 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 457 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 458 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 459 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 460
 461 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 462 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 463 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 464 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 465 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 466 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 467
 468 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  STDFp1SrcRm>;
 469 def X86rcp28     : SDNode<"X86ISD::RCP28",    STDFp1SrcRm>;
 470 def X86exp2      : SDNode<"X86ISD::EXP2",     STDFp1SrcRm>;
 471
 472 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",   STDFp2SrcRm>;
 473 def X86rcp28s    : SDNode<"X86ISD::RCP28",     STDFp2SrcRm>;
 474 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
 475 def X86Reduces   : SDNode<"X86ISD::VREDUCE",   STDFp3SrcRm>;
 476 def X86GetMants  : SDNode<"X86ISD::VGETMANT",  STDFp3SrcRm>;
 477
 478 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 479                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 480                                          SDTCisVT<4, i8>]>;
 481 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 482                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 483                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 484                                          SDTCisVT<6, i8>]>;
 485
 486 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 487 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 488
 489 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 490                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 491 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 492                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 493
 494 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 495                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 496                                           SDTCisVT<3, i32>]>;
 497
 498 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 499                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 500 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 501                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 502
 503 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 504                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 505 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
 506                                              SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
 507 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 508                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 509 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 510                                             SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
 511 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 512                                            SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
 513                                            SDTCisInt<2>]>;
 514 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 515                                            SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
 516                                            SDTCisInt<2>]>;
 517
 518 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 519                                            SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
 520                                            SDTCisInt<2>]>;
 521 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 522                                            SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
 523                                            SDTCisInt<2>]>;
 524
 525 // Scalar
 526 def X86SintToFpRnd  : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTintToFPRound>;
 527 def X86UintToFpRnd  : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTintToFPRound>;
 528
 529 def X86cvttss2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSFloatToIntRnd>;
 530 def X86cvttss2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSFloatToIntRnd>;
 531 def X86cvttsd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSDoubleToIntRnd>;
 532 def X86cvttsd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSDoubleToIntRnd>;
 533 // Vector with rounding mode
 534
 535 // cvtt fp-to-int staff
 536 def X86VFpToSintRnd   : SDNode<"ISD::FP_TO_SINT",  SDTVFPToIntRound>;
 537 def X86VFpToUintRnd   : SDNode<"ISD::FP_TO_UINT",  SDTVFPToIntRound>;
 538 def X86VFpToSlongRnd  : SDNode<"ISD::FP_TO_SINT",  SDTVFPToLongRound>;
 539 def X86VFpToUlongRnd  : SDNode<"ISD::FP_TO_UINT",  SDTVFPToLongRound>;
 540
 541 def X86VSintToFpRnd   : SDNode<"ISD::SINT_TO_FP",  SDTVintToFPRound>;
 542 def X86VUintToFpRnd   : SDNode<"ISD::UINT_TO_FP",  SDTVintToFPRound>;
 543 def X86VSlongToFpRnd  : SDNode<"ISD::SINT_TO_FP",  SDTVlongToFPRound>;
 544 def X86VUlongToFpRnd  : SDNode<"ISD::UINT_TO_FP",  SDTVlongToFPRound>;
 545
 546 // cvt fp-to-int staff
 547 def X86cvtps2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToIntRnd>;
 548 def X86cvtps2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToIntRnd>;
 549 def X86cvtpd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToIntRnd>;
 550 def X86cvtpd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToIntRnd>;
 551
 552 // Vector without rounding mode
 553 def X86cvtps2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToInt>;
 554 def X86cvtps2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToInt>;
 555 def X86cvtpd2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToInt>;
 556 def X86cvtpd2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToInt>;
 557
 558 def X86cvtph2ps     : SDNode<"ISD::FP16_TO_FP",
 559                               SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 560                                                    SDTCVecEltisVT<0, f32>,
 561                                                    SDTCVecEltisVT<1, i16>,
 562                                                    SDTCisFP<0>,
 563                                                    SDTCisVT<2, i32>]> >;
 564
 565 def X86cvtps2ph   : SDNode<"ISD::FP_TO_FP16",
 566                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 567                                              SDTCVecEltisVT<0, i16>,
 568                                              SDTCVecEltisVT<1, f32>,
 569                                              SDTCisFP<1>, SDTCisVT<2, i32>,
 570                                              SDTCisVT<3, i32>]> >;
 571 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT",
 572                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 573                                              SDTCisFP<0>, SDTCisFP<1>,
 574                                              SDTCVecEltisVT<0, f64>,
 575                                              SDTCVecEltisVT<1, f32>,
 576                                              SDTCisOpSmallerThanOp<1, 0>,
 577                                              SDTCisVT<2, i32>]>>;
 578 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
 579                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 580                                              SDTCisFP<0>, SDTCisFP<1>,
 581                                              SDTCVecEltisVT<0, f32>,
 582                                              SDTCVecEltisVT<1, f64>,
 583                                              SDTCisOpSmallerThanOp<0, 1>,
 584                                              SDTCisVT<2, i32>]>>;
 585
 586 def X86cvt2mask   : SDNode<"X86ISD::CVT2MASK", SDTIntTruncOp>;
 587
 588 //===----------------------------------------------------------------------===//
 589 // SSE Complex Patterns
 590 //===----------------------------------------------------------------------===//
 591
 592 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 593 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 594 // forms.
 595 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 596                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 597                                    SDNPWantRoot]>;
 598 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 599                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 600                                    SDNPWantRoot]>;
 601
 602 def ssmem : Operand<v4f32> {
 603   let PrintMethod = "printf32mem";
 604   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 605   let ParserMatchClass = X86Mem32AsmOperand;
 606   let OperandType = "OPERAND_MEMORY";
 607 }
 608 def sdmem : Operand<v2f64> {
 609   let PrintMethod = "printf64mem";
 610   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 611   let ParserMatchClass = X86Mem64AsmOperand;
 612   let OperandType = "OPERAND_MEMORY";
 613 }
 614
 615 //===----------------------------------------------------------------------===//
 616 // SSE pattern fragments
 617 //===----------------------------------------------------------------------===//
 618
 619 // 128-bit load pattern fragments
 620 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 621 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 622 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 623 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 624
 625 // 256-bit load pattern fragments
 626 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 627 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 628 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 629 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 630
 631 // 512-bit load pattern fragments
 632 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 633 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 634 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
 635 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 636 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 637 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 638
 639 // 128-/256-/512-bit extload pattern fragments
 640 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 641 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 642 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 643
 644 // These are needed to match a scalar load that is used in a vector-only
 645 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 646 // The memory operand is required to be a 128-bit load, so it must be converted
 647 // from a vector to a scalar.
 648 def loadf32_128 : PatFrag<(ops node:$ptr),
 649   (f32 (extractelt (loadv4f32 node:$ptr), (iPTR 0)))>;
 650 def loadf64_128 : PatFrag<(ops node:$ptr),
 651   (f64 (extractelt (loadv2f64 node:$ptr), (iPTR 0)))>;
 652
 653 // Like 'store', but always requires 128-bit vector alignment.
 654 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 655                            (store node:$val, node:$ptr), [{
 656   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 657 }]>;
 658
 659 // Like 'store', but always requires 256-bit vector alignment.
 660 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 661                               (store node:$val, node:$ptr), [{
 662   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 663 }]>;
 664
 665 // Like 'store', but always requires 512-bit vector alignment.
 666 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 667                               (store node:$val, node:$ptr), [{
 668   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 669 }]>;
 670
 671 // Like 'load', but always requires 128-bit vector alignment.
 672 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 673   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 674 }]>;
 675
 676 // Like 'X86vzload', but always requires 128-bit vector alignment.
 677 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
 678   return cast<MemSDNode>(N)->getAlignment() >= 16;
 679 }]>;
 680
 681 // Like 'load', but always requires 256-bit vector alignment.
 682 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 683   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 684 }]>;
 685
 686 // Like 'load', but always requires 512-bit vector alignment.
 687 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 688   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 689 }]>;
 690
 691 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
 692                                (f32 (alignedload node:$ptr))>;
 693 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
 694                                (f64 (alignedload node:$ptr))>;
 695
 696 // 128-bit aligned load pattern fragments
 697 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 698 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 699                                (v4f32 (alignedload node:$ptr))>;
 700 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 701                                (v2f64 (alignedload node:$ptr))>;
 702 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 703                                (v2i64 (alignedload node:$ptr))>;
 704
 705 // 256-bit aligned load pattern fragments
 706 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 707 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 708                                (v8f32 (alignedload256 node:$ptr))>;
 709 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 710                                (v4f64 (alignedload256 node:$ptr))>;
 711 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 712                                (v4i64 (alignedload256 node:$ptr))>;
 713
 714 // 512-bit aligned load pattern fragments
 715 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 716                                 (v16f32 (alignedload512 node:$ptr))>;
 717 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 718                                 (v16i32 (alignedload512 node:$ptr))>;
 719 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 720                                 (v8f64  (alignedload512 node:$ptr))>;
 721 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 722                                 (v8i64  (alignedload512 node:$ptr))>;
 723
 724 // Like 'load', but uses special alignment checks suitable for use in
 725 // memory operands in most SSE instructions, which are required to
 726 // be naturally aligned on some targets but not on others.  If the subtarget
 727 // allows unaligned accesses, match any load, though this may require
 728 // setting a feature bit in the processor (on startup, for example).
 729 // Opteron 10h and later implement such a feature.
 730 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 731   return    Subtarget->hasSSEUnalignedMem()
 732          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 733 }]>;
 734
 735 def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
 736 def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
 737
 738 // 128-bit memop pattern fragments
 739 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 740 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 741 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 742 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 743
 744 // These are needed to match a scalar memop that is used in a vector-only
 745 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 746 // The memory operand is required to be a 128-bit load, so it must be converted
 747 // from a vector to a scalar.
 748 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 749   (f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
 750 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 751   (f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;
 752
 753
 754 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 755 // 16-byte boundary.
 756 // FIXME: 8 byte alignment for mmx reads is not required
 757 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 758   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 759 }]>;
 760
 761 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 762
 763 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 764   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 765   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 766     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 767             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 768   return false;
 769 }]>;
 770
 771 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 772   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 773   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 774     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 775             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 776   return false;
 777 }]>;
 778
 779 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 780   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 781   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 782     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 783             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 784   return false;
 785 }]>;
 786 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 787   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 788   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 789     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 790             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 791   return false;
 792 }]>;
 793 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 794   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 795   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 796     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 797             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 798   return false;
 799 }]>;
 800 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 801   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 802   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 803     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 804             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 805   return false;
 806 }]>;
 807
 808 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 809   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 810   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 811     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 812             Sc->getBasePtr().getValueType() == MVT::v2i64);
 813   return false;
 814 }]>;
 815
 816 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 817   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 818   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 819     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 820             Sc->getBasePtr().getValueType() == MVT::v4i32);
 821   return false;
 822 }]>;
 823
 824 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 825   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 826   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 827     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 828             Sc->getBasePtr().getValueType() == MVT::v4i64);
 829   return false;
 830 }]>;
 831
 832 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 833   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 834   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 835     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 836             Sc->getBasePtr().getValueType() == MVT::v8i32);
 837   return false;
 838 }]>;
 839
 840 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 841   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 842   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 843     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 844             Sc->getBasePtr().getValueType() == MVT::v8i64);
 845   return false;
 846 }]>;
 847 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 848   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 849   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 850     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 851             Sc->getBasePtr().getValueType() == MVT::v16i32);
 852   return false;
 853 }]>;
 854
 855 // 128-bit bitconvert pattern fragments
 856 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 857 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 858 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 859 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 860 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 861 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 862
 863 // 256-bit bitconvert pattern fragments
 864 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 865 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 866 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 867 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 868 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 869
 870 // 512-bit bitconvert pattern fragments
 871 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 872 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 873 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 874 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 875
 876 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 877                            (bitconvert (v2i64 (X86vzmovl
 878                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 879 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 880                            (bitconvert (v4i32 (X86vzmovl
 881                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 882
 883 def vzload_v2i64 : PatFrag<(ops node:$src),
 884                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 885
 886
 887 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 888   return N->isExactlyValue(+0.0);
 889 }]>;
 890
 891 def I8Imm : SDNodeXForm<imm, [{
 892   // Transformation function: get the low 8 bits.
 893   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 894 }]>;
 895
 896 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 897 def FROUND_CURRENT : ImmLeaf<i32, [{
 898   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 899 }]>;
 900
 901 // BYTE_imm - Transform bit immediates into byte immediates.
 902 def BYTE_imm  : SDNodeXForm<imm, [{
 903   // Transformation function: imm >> 3
 904   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 905 }]>;
 906
 907 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 908 // to VEXTRACTF128/VEXTRACTI128 imm.
 909 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 910   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 911 }]>;
 912
 913 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 914 // VINSERTF128/VINSERTI128 imm.
 915 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 916   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 917 }]>;
 918
 919 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 920 // to VEXTRACTF64x4 imm.
 921 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 922   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 923 }]>;
 924
 925 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 926 // VINSERTF64x4 imm.
 927 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 928   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 929 }]>;
 930
 931 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 932                                    (extract_subvector node:$bigvec,
 933                                                       node:$index), [{
 934   return X86::isVEXTRACT128Index(N);
 935 }], EXTRACT_get_vextract128_imm>;
 936
 937 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 938                                       node:$index),
 939                                  (insert_subvector node:$bigvec, node:$smallvec,
 940                                                    node:$index), [{
 941   return X86::isVINSERT128Index(N);
 942 }], INSERT_get_vinsert128_imm>;
 943
 944
 945 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 946                                    (extract_subvector node:$bigvec,
 947                                                       node:$index), [{
 948   return X86::isVEXTRACT256Index(N);
 949 }], EXTRACT_get_vextract256_imm>;
 950
 951 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 952                                       node:$index),
 953                                  (insert_subvector node:$bigvec, node:$smallvec,
 954                                                    node:$index), [{
 955   return X86::isVINSERT256Index(N);
 956 }], INSERT_get_vinsert256_imm>;
 957
 958 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 959                          (masked_load node:$src1, node:$src2, node:$src3), [{
 960   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 961     return Load->getAlignment() >= 16;
 962   return false;
 963 }]>;
 964
 965 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 966                          (masked_load node:$src1, node:$src2, node:$src3), [{
 967   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 968     return Load->getAlignment() >= 32;
 969   return false;
 970 }]>;
 971
 972 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 973                          (masked_load node:$src1, node:$src2, node:$src3), [{
 974   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 975     return Load->getAlignment() >= 64;
 976   return false;
 977 }]>;
 978
 979 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 980                          (masked_load node:$src1, node:$src2, node:$src3), [{
 981   return isa<MaskedLoadSDNode>(N);
 982 }]>;
 983
 984 // masked store fragments.
 985 // X86mstore can't be implemented in core DAG files because some targets
 986 // doesn't support vector type ( llvm-tblgen will fail)
 987 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 988                         (masked_store node:$src1, node:$src2, node:$src3), [{
 989   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 990 }]>;
 991
 992 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 993                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 994   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 995     return Store->getAlignment() >= 16;
 996   return false;
 997 }]>;
 998
 999 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1000                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1001   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
1002     return Store->getAlignment() >= 32;
1003   return false;
1004 }]>;
1005
1006 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1007                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1008   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
1009     return Store->getAlignment() >= 64;
1010   return false;
1011 }]>;
1012
1013 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1014                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1015   return isa<MaskedStoreSDNode>(N);
1016 }]>;
1017
1018 // masked truncstore fragments
1019 // X86mtruncstore can't be implemented in core DAG files because some targets
1020 // doesn't support vector type ( llvm-tblgen will fail)
1021 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1022                              (masked_store node:$src1, node:$src2, node:$src3), [{
1023     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1024 }]>;
1025 def masked_truncstorevi8 :
1026   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1027           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1028   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1029 }]>;
1030 def masked_truncstorevi16 :
1031   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1032           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1033   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1034 }]>;
1035 def masked_truncstorevi32 :
1036   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1037           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1038   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1039 }]>;