1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
39 SDTCisFP<0>, SDTCisInt<2> ]>;
40 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
41 SDTCisFP<1>, SDTCisVT<3, i8>,
44 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
45 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
46 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
47 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
49 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
50 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
52 // Commutative and Associative FMIN and FMAX.
53 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
58 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
65 [SDNPCommutative, SDNPAssociative]>;
66 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
67 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
68 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
69 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
70 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
71 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
72 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
73 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
74 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
75 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
76 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
77 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86andnp : SDNode<"X86ISD::ANDNP",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86psign : SDNode<"X86ISD::PSIGN",
85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def X86pextrb : SDNode<"X86ISD::PEXTRB",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89 def X86pextrw : SDNode<"X86ISD::PEXTRW",
90 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
91 def X86pinsrb : SDNode<"X86ISD::PINSRB",
92 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
93 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
94 def X86pinsrw : SDNode<"X86ISD::PINSRW",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86insertps : SDNode<"X86ISD::INSERTPS",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
100 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
101 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
103 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
104 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
106 def X86vzext : SDNode<"X86ISD::VZEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
111 def X86vsext : SDNode<"X86ISD::VSEXT",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<1, 0>]>>;
116 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<0, 1>]>>;
120 def X86trunc : SDNode<"X86ISD::TRUNC",
121 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
124 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
125 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
126 SDTCisInt<0>, SDTCisInt<1>,
127 SDTCisVec<2>, SDTCisInt<2>,
128 SDTCisOpSmallerThanOp<0, 2>]>>;
129 def X86vfpext : SDNode<"X86ISD::VFPEXT",
130 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
131 SDTCisFP<0>, SDTCisFP<1>,
132 SDTCisOpSmallerThanOp<1, 0>]>>;
133 def X86vfpround: SDNode<"X86ISD::VFPROUND",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<0, 1>]>>;
138 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
139 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
140 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
141 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
142 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
144 def X86IntCmpMask : SDTypeProfile<1, 2,
145 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
146 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
147 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
150 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
151 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
152 def X86CmpMaskCCScalar :
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
155 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
156 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
157 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
159 def X86vshl : SDNode<"X86ISD::VSHL",
160 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
162 def X86vsrl : SDNode<"X86ISD::VSRL",
163 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
165 def X86vsra : SDNode<"X86ISD::VSRA",
166 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
169 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
170 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
171 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
173 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
175 SDTCisSameAs<2, 1>]>;
176 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
177 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
178 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
179 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
180 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
181 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
182 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
183 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCVecEltisVT<0, i1>,
186 SDTCisSameNumEltsAs<0, 1>]>>;
187 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCVecEltisVT<0, i1>,
190 SDTCisSameNumEltsAs<0, 1>]>>;
191 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
193 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
194 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
195 SDTCisSameAs<1,2>]>>;
196 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
197 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
198 SDTCisSameAs<1,2>]>>;
200 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
201 // translated into one of the target nodes below during lowering.
202 // Note: this is a work in progress...
203 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
204 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
206 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
209 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
211 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
212 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
213 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
216 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
217 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
219 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
220 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
222 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
223 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
225 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
226 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
227 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
228 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
229 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
230 SDTCisVec<0>, SDTCisInt<2>]>;
231 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
232 SDTCisVec<0>, SDTCisInt<3>]>;
233 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
234 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
236 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
237 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
239 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
240 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
241 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
243 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
245 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
246 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
247 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
249 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
250 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
252 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
253 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
254 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
256 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
257 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
259 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
260 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
261 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
263 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
264 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
266 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
267 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
268 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
269 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
270 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
271 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
273 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
275 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
276 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
277 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
278 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
279 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
280 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
282 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
284 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
286 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
287 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
288 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
289 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
290 def X86fmaxRnd : SDNode<"X86ISD::FMAX", SDTFPBinOpRound>;
291 def X86fminRnd : SDNode<"X86ISD::FMIN", SDTFPBinOpRound>;
293 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
294 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
295 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
296 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
297 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
298 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
300 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
301 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
302 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
303 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
304 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
305 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
307 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
308 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
309 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
311 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
312 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
313 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
315 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
316 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
318 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
319 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
320 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
323 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
324 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
326 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
327 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
328 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
329 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
331 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
333 //===----------------------------------------------------------------------===//
334 // SSE Complex Patterns
335 //===----------------------------------------------------------------------===//
337 // These are 'extloads' from a scalar to the low element of a vector, zeroing
338 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
340 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
341 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
343 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
344 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
347 def ssmem : Operand<v4f32> {
348 let PrintMethod = "printf32mem";
349 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
350 let ParserMatchClass = X86Mem32AsmOperand;
351 let OperandType = "OPERAND_MEMORY";
353 def sdmem : Operand<v2f64> {
354 let PrintMethod = "printf64mem";
355 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
356 let ParserMatchClass = X86Mem64AsmOperand;
357 let OperandType = "OPERAND_MEMORY";
360 //===----------------------------------------------------------------------===//
361 // SSE pattern fragments
362 //===----------------------------------------------------------------------===//
364 // 128-bit load pattern fragments
365 // NOTE: all 128-bit integer vector loads are promoted to v2i64
366 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
367 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
368 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
370 // 256-bit load pattern fragments
371 // NOTE: all 256-bit integer vector loads are promoted to v4i64
372 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
373 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
374 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
376 // 512-bit load pattern fragments
377 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
378 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
379 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
380 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
381 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
382 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
384 // 128-/256-/512-bit extload pattern fragments
385 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
386 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
387 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
389 // These are needed to match a scalar load that is used in a vector-only
390 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
391 // The memory operand is required to be a 128-bit load, so it must be converted
392 // from a vector to a scalar.
393 def loadf32_128 : PatFrag<(ops node:$ptr),
394 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
395 def loadf64_128 : PatFrag<(ops node:$ptr),
396 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
398 // Like 'store', but always requires 128-bit vector alignment.
399 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
400 (store node:$val, node:$ptr), [{
401 return cast<StoreSDNode>(N)->getAlignment() >= 16;
404 // Like 'store', but always requires 256-bit vector alignment.
405 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
406 (store node:$val, node:$ptr), [{
407 return cast<StoreSDNode>(N)->getAlignment() >= 32;
410 // Like 'store', but always requires 512-bit vector alignment.
411 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() >= 64;
416 // Like 'load', but always requires 128-bit vector alignment.
417 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
418 return cast<LoadSDNode>(N)->getAlignment() >= 16;
421 // Like 'X86vzload', but always requires 128-bit vector alignment.
422 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
423 return cast<MemSDNode>(N)->getAlignment() >= 16;
426 // Like 'load', but always requires 256-bit vector alignment.
427 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
428 return cast<LoadSDNode>(N)->getAlignment() >= 32;
431 // Like 'load', but always requires 512-bit vector alignment.
432 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
433 return cast<LoadSDNode>(N)->getAlignment() >= 64;
436 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
437 (f32 (alignedload node:$ptr))>;
438 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
439 (f64 (alignedload node:$ptr))>;
441 // 128-bit aligned load pattern fragments
442 // NOTE: all 128-bit integer vector loads are promoted to v2i64
443 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
444 (v4f32 (alignedload node:$ptr))>;
445 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
446 (v2f64 (alignedload node:$ptr))>;
447 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
448 (v2i64 (alignedload node:$ptr))>;
450 // 256-bit aligned load pattern fragments
451 // NOTE: all 256-bit integer vector loads are promoted to v4i64
452 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
453 (v8f32 (alignedload256 node:$ptr))>;
454 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
455 (v4f64 (alignedload256 node:$ptr))>;
456 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
457 (v4i64 (alignedload256 node:$ptr))>;
459 // 512-bit aligned load pattern fragments
460 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
461 (v16f32 (alignedload512 node:$ptr))>;
462 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
463 (v16i32 (alignedload512 node:$ptr))>;
464 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
465 (v8f64 (alignedload512 node:$ptr))>;
466 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
467 (v8i64 (alignedload512 node:$ptr))>;
469 // Like 'load', but uses special alignment checks suitable for use in
470 // memory operands in most SSE instructions, which are required to
471 // be naturally aligned on some targets but not on others. If the subtarget
472 // allows unaligned accesses, match any load, though this may require
473 // setting a feature bit in the processor (on startup, for example).
474 // Opteron 10h and later implement such a feature.
475 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
476 return Subtarget->hasSSEUnalignedMem()
477 || cast<LoadSDNode>(N)->getAlignment() >= 16;
480 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
481 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
483 // 128-bit memop pattern fragments
484 // NOTE: all 128-bit integer vector loads are promoted to v2i64
485 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
486 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
487 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
489 // These are needed to match a scalar memop that is used in a vector-only
490 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
491 // The memory operand is required to be a 128-bit load, so it must be converted
492 // from a vector to a scalar.
493 def memopfsf32_128 : PatFrag<(ops node:$ptr),
494 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
495 def memopfsf64_128 : PatFrag<(ops node:$ptr),
496 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
499 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
501 // FIXME: 8 byte alignment for mmx reads is not required
502 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
503 return cast<LoadSDNode>(N)->getAlignment() >= 8;
506 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
509 // Like 'store', but requires the non-temporal bit to be set
510 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
511 (st node:$val, node:$ptr), [{
512 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
513 return ST->isNonTemporal();
517 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
518 (st node:$val, node:$ptr), [{
519 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
520 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
521 ST->getAddressingMode() == ISD::UNINDEXED &&
522 ST->getAlignment() >= 16;
526 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
527 (st node:$val, node:$ptr), [{
528 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
529 return ST->isNonTemporal() &&
530 ST->getAlignment() < 16;
534 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
535 (masked_gather node:$src1, node:$src2, node:$src3) , [{
536 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
537 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
538 Mgt->getBasePtr().getValueType() == MVT::v8i32);
542 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
543 (masked_gather node:$src1, node:$src2, node:$src3) , [{
544 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
545 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
546 Mgt->getBasePtr().getValueType() == MVT::v8i64);
549 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
550 (masked_gather node:$src1, node:$src2, node:$src3) , [{
551 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
552 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
553 Mgt->getBasePtr().getValueType() == MVT::v16i32);
557 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
558 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
559 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
560 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
561 Sc->getBasePtr().getValueType() == MVT::v8i32);
565 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
566 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
567 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
568 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
569 Sc->getBasePtr().getValueType() == MVT::v8i64);
572 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
573 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
574 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
575 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
576 Sc->getBasePtr().getValueType() == MVT::v16i32);
580 // 128-bit bitconvert pattern fragments
581 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
582 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
583 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
584 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
585 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
586 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
588 // 256-bit bitconvert pattern fragments
589 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
590 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
591 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
592 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
593 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
595 // 512-bit bitconvert pattern fragments
596 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
597 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
598 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
599 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
601 def vzmovl_v2i64 : PatFrag<(ops node:$src),
602 (bitconvert (v2i64 (X86vzmovl
603 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
604 def vzmovl_v4i32 : PatFrag<(ops node:$src),
605 (bitconvert (v4i32 (X86vzmovl
606 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
608 def vzload_v2i64 : PatFrag<(ops node:$src),
609 (bitconvert (v2i64 (X86vzload node:$src)))>;
612 def fp32imm0 : PatLeaf<(f32 fpimm), [{
613 return N->isExactlyValue(+0.0);
616 def I8Imm : SDNodeXForm<imm, [{
617 // Transformation function: get the low 8 bits.
618 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
621 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
622 def FROUND_CURRENT : ImmLeaf<i32, [{
623 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
626 // BYTE_imm - Transform bit immediates into byte immediates.
627 def BYTE_imm : SDNodeXForm<imm, [{
628 // Transformation function: imm >> 3
629 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
632 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
633 // to VEXTRACTF128/VEXTRACTI128 imm.
634 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
635 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
638 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
639 // VINSERTF128/VINSERTI128 imm.
640 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
641 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
644 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
645 // to VEXTRACTF64x4 imm.
646 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
647 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
650 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
652 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
653 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
656 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
657 (extract_subvector node:$bigvec,
659 return X86::isVEXTRACT128Index(N);
660 }], EXTRACT_get_vextract128_imm>;
662 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
664 (insert_subvector node:$bigvec, node:$smallvec,
666 return X86::isVINSERT128Index(N);
667 }], INSERT_get_vinsert128_imm>;
670 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
671 (extract_subvector node:$bigvec,
673 return X86::isVEXTRACT256Index(N);
674 }], EXTRACT_get_vextract256_imm>;
676 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
678 (insert_subvector node:$bigvec, node:$smallvec,
680 return X86::isVINSERT256Index(N);
681 }], INSERT_get_vinsert256_imm>;
683 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
684 (masked_load node:$src1, node:$src2, node:$src3), [{
685 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
686 return Load->getAlignment() >= 16;
690 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
691 (masked_load node:$src1, node:$src2, node:$src3), [{
692 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
693 return Load->getAlignment() >= 32;
697 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
698 (masked_load node:$src1, node:$src2, node:$src3), [{
699 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
700 return Load->getAlignment() >= 64;
704 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
705 (masked_load node:$src1, node:$src2, node:$src3), [{
706 return isa<MaskedLoadSDNode>(N);
709 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
710 (masked_store node:$src1, node:$src2, node:$src3), [{
711 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
712 return Store->getAlignment() >= 16;
716 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
717 (masked_store node:$src1, node:$src2, node:$src3), [{
718 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
719 return Store->getAlignment() >= 32;
723 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
724 (masked_store node:$src1, node:$src2, node:$src3), [{
725 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
726 return Store->getAlignment() >= 64;
730 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
731 (masked_store node:$src1, node:$src2, node:$src3), [{
732 return isa<MaskedStoreSDNode>(N);