1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
32 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
38 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
39 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
40 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
41 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
42 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
43 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
44 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
45 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
46 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
47 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
48 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
49 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
50 def X86pshufb : SDNode<"X86ISD::PSHUFB",
51 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
53 def X86andnp : SDNode<"X86ISD::ANDNP",
54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
56 def X86psign : SDNode<"X86ISD::PSIGN",
57 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
59 def X86pextrb : SDNode<"X86ISD::PEXTRB",
60 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
61 def X86pextrw : SDNode<"X86ISD::PEXTRW",
62 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
63 def X86pinsrb : SDNode<"X86ISD::PINSRB",
64 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
65 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
66 def X86pinsrw : SDNode<"X86ISD::PINSRW",
67 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
68 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
69 def X86insrtps : SDNode<"X86ISD::INSERTPS",
70 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
71 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
72 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
73 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
74 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
75 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
76 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
77 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
78 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
79 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
80 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
82 def X86vshl : SDNode<"X86ISD::VSHL",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86vsrl : SDNode<"X86ISD::VSRL",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86vsra : SDNode<"X86ISD::VSRA",
89 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
93 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
94 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
96 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
99 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
100 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
102 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
103 // translated into one of the target nodes below during lowering.
104 // Note: this is a work in progress...
105 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
106 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
109 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
110 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
111 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
112 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
114 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
116 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
118 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
119 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
120 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
122 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
124 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
125 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
126 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
128 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
129 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
131 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
132 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
133 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
135 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
136 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
138 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
139 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
141 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
143 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
145 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
147 //===----------------------------------------------------------------------===//
148 // SSE Complex Patterns
149 //===----------------------------------------------------------------------===//
151 // These are 'extloads' from a scalar to the low element of a vector, zeroing
152 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
154 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
155 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
157 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
158 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
161 def ssmem : Operand<v4f32> {
162 let PrintMethod = "printf32mem";
163 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
164 let ParserMatchClass = X86MemAsmOperand;
165 let OperandType = "OPERAND_MEMORY";
167 def sdmem : Operand<v2f64> {
168 let PrintMethod = "printf64mem";
169 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
170 let ParserMatchClass = X86MemAsmOperand;
171 let OperandType = "OPERAND_MEMORY";
174 //===----------------------------------------------------------------------===//
175 // SSE pattern fragments
176 //===----------------------------------------------------------------------===//
178 // 128-bit load pattern fragments
179 // NOTE: all 128-bit integer vector loads are promoted to v2i64
180 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
181 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
182 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
184 // 256-bit load pattern fragments
185 // NOTE: all 256-bit integer vector loads are promoted to v4i64
186 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
187 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
188 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
190 // Like 'store', but always requires 128-bit vector alignment.
191 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
192 (store node:$val, node:$ptr), [{
193 return cast<StoreSDNode>(N)->getAlignment() >= 16;
196 // Like 'store', but always requires 256-bit vector alignment.
197 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
198 (store node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getAlignment() >= 32;
202 // Like 'load', but always requires 128-bit vector alignment.
203 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
204 return cast<LoadSDNode>(N)->getAlignment() >= 16;
207 // Like 'load', but always requires 256-bit vector alignment.
208 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
209 return cast<LoadSDNode>(N)->getAlignment() >= 32;
212 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
213 (f32 (alignedload node:$ptr))>;
214 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
215 (f64 (alignedload node:$ptr))>;
217 // 128-bit aligned load pattern fragments
218 // NOTE: all 128-bit integer vector loads are promoted to v2i64
219 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
220 (v4f32 (alignedload node:$ptr))>;
221 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
222 (v2f64 (alignedload node:$ptr))>;
223 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
224 (v2i64 (alignedload node:$ptr))>;
226 // 256-bit aligned load pattern fragments
227 // NOTE: all 256-bit integer vector loads are promoted to v4i64
228 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
229 (v8f32 (alignedload256 node:$ptr))>;
230 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
231 (v4f64 (alignedload256 node:$ptr))>;
232 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
233 (v4i64 (alignedload256 node:$ptr))>;
235 // Like 'load', but uses special alignment checks suitable for use in
236 // memory operands in most SSE instructions, which are required to
237 // be naturally aligned on some targets but not on others. If the subtarget
238 // allows unaligned accesses, match any load, though this may require
239 // setting a feature bit in the processor (on startup, for example).
240 // Opteron 10h and later implement such a feature.
241 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
242 return Subtarget->hasVectorUAMem()
243 || cast<LoadSDNode>(N)->getAlignment() >= 16;
246 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
247 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
249 // 128-bit memop pattern fragments
250 // NOTE: all 128-bit integer vector loads are promoted to v2i64
251 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
252 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
253 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
255 // 256-bit memop pattern fragments
256 // NOTE: all 256-bit integer vector loads are promoted to v4i64
257 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
258 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
259 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
261 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
263 // FIXME: 8 byte alignment for mmx reads is not required
264 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
265 return cast<LoadSDNode>(N)->getAlignment() >= 8;
268 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
271 // Like 'store', but requires the non-temporal bit to be set
272 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
273 (st node:$val, node:$ptr), [{
274 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
275 return ST->isNonTemporal();
279 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
280 (st node:$val, node:$ptr), [{
281 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
282 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
283 ST->getAddressingMode() == ISD::UNINDEXED &&
284 ST->getAlignment() >= 16;
288 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
289 (st node:$val, node:$ptr), [{
290 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
291 return ST->isNonTemporal() &&
292 ST->getAlignment() < 16;
296 // 128-bit bitconvert pattern fragments
297 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
298 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
299 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
300 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
301 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
302 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
304 // 256-bit bitconvert pattern fragments
305 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
306 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
307 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
308 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
310 def vzmovl_v2i64 : PatFrag<(ops node:$src),
311 (bitconvert (v2i64 (X86vzmovl
312 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
313 def vzmovl_v4i32 : PatFrag<(ops node:$src),
314 (bitconvert (v4i32 (X86vzmovl
315 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
317 def vzload_v2i64 : PatFrag<(ops node:$src),
318 (bitconvert (v2i64 (X86vzload node:$src)))>;
321 def fp32imm0 : PatLeaf<(f32 fpimm), [{
322 return N->isExactlyValue(+0.0);
325 // BYTE_imm - Transform bit immediates into byte immediates.
326 def BYTE_imm : SDNodeXForm<imm, [{
327 // Transformation function: imm >> 3
328 return getI32Imm(N->getZExtValue() >> 3);
331 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
333 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
334 return getI8Imm(X86::getShuffleSHUFImmediate(cast<ShuffleVectorSDNode>(N)));
337 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
339 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
340 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
343 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
345 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
346 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
349 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
350 // to VEXTRACTF128 imm.
351 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
352 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
355 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
357 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
358 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
361 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
362 (vector_shuffle node:$lhs, node:$rhs), [{
363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
364 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
367 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
368 (vector_shuffle node:$lhs, node:$rhs), [{
369 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
372 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
373 (vector_shuffle node:$lhs, node:$rhs), [{
374 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
377 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
378 (vector_shuffle node:$lhs, node:$rhs), [{
379 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
382 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
383 (vector_shuffle node:$lhs, node:$rhs), [{
384 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
387 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
388 (vector_shuffle node:$lhs, node:$rhs), [{
389 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
392 def movl : PatFrag<(ops node:$lhs, node:$rhs),
393 (vector_shuffle node:$lhs, node:$rhs), [{
394 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
397 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
398 (vector_shuffle node:$lhs, node:$rhs), [{
399 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
402 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
403 (vector_shuffle node:$lhs, node:$rhs), [{
404 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
407 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
408 (vector_shuffle node:$lhs, node:$rhs), [{
409 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
410 }], SHUFFLE_get_shuf_imm>;
412 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
413 (vector_shuffle node:$lhs, node:$rhs), [{
414 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX());
415 }], SHUFFLE_get_shuf_imm>;
417 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
418 (vector_shuffle node:$lhs, node:$rhs), [{
419 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
420 }], SHUFFLE_get_pshufhw_imm>;
422 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
423 (vector_shuffle node:$lhs, node:$rhs), [{
424 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
425 }], SHUFFLE_get_pshuflw_imm>;
427 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
428 (extract_subvector node:$bigvec,
430 return X86::isVEXTRACTF128Index(N);
431 }], EXTRACT_get_vextractf128_imm>;
433 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
435 (insert_subvector node:$bigvec, node:$smallvec,
437 return X86::isVINSERTF128Index(N);
438 }], INSERT_get_vinsertf128_imm>;