1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
41 def SDTX86CmpTestSae : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
42 SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
44 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
45 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
47 // Commutative and Associative FMIN and FMAX.
48 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
53 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
60 [SDNPCommutative, SDNPAssociative]>;
61 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
62 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
63 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
64 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
65 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
66 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
67 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
68 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
69 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
70 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
71 def X86comiSae : SDNode<"X86ISD::COMI", SDTX86CmpTestSae>;
72 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
73 def X86ucomiSae: SDNode<"X86ISD::UCOMI", SDTX86CmpTestSae>;
74 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
75 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
76 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
77 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
78 SDTCisVT<1, v4i32>]>>;
79 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
80 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
81 SDTCisVT<1, v4i32>]>>;
82 def X86pshufb : SDNode<"X86ISD::PSHUFB",
83 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
85 def X86psadbw : SDNode<"X86ISD::PSADBW",
86 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
87 SDTCVecEltisVT<1, i8>,
88 SDTCisSameSizeAs<0,1>,
90 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
91 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
92 SDTCVecEltisVT<1, i8>,
93 SDTCisSameSizeAs<0,1>,
94 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
95 def X86andnp : SDNode<"X86ISD::ANDNP",
96 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
98 def X86psign : SDNode<"X86ISD::PSIGN",
99 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
100 SDTCisSameAs<0,2>]>>;
101 def X86pextrb : SDNode<"X86ISD::PEXTRB",
102 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
104 def X86pextrw : SDNode<"X86ISD::PEXTRW",
105 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
107 def X86pinsrb : SDNode<"X86ISD::PINSRB",
108 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
109 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
110 def X86pinsrw : SDNode<"X86ISD::PINSRW",
111 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
112 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
113 def X86insertps : SDNode<"X86ISD::INSERTPS",
114 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
115 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
116 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
117 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
119 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def X86vzext : SDNode<"X86ISD::VZEXT",
123 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
124 SDTCisInt<0>, SDTCisInt<1>,
125 SDTCisOpSmallerThanOp<1, 0>]>>;
127 def X86vsext : SDNode<"X86ISD::VSEXT",
128 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<1, 0>]>>;
132 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisInt<0>, SDTCisInt<1>,
134 SDTCisOpSmallerThanOp<0, 1>]>;
136 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
137 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
138 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
140 def X86trunc : SDNode<"X86ISD::TRUNC",
141 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
142 SDTCisOpSmallerThanOp<0, 1>]>>;
143 def X86vfpext : SDNode<"X86ISD::VFPEXT",
144 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
145 SDTCisFP<0>, SDTCisFP<1>,
146 SDTCisOpSmallerThanOp<1, 0>]>>;
147 def X86vfpround: SDNode<"X86ISD::VFPROUND",
148 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
149 SDTCisFP<0>, SDTCisFP<1>,
150 SDTCisOpSmallerThanOp<0, 1>]>>;
152 def X86fround: SDNode<"X86ISD::VFPROUND",
153 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
154 SDTCVecEltisVT<0, f32>,
155 SDTCVecEltisVT<1, f64>,
156 SDTCVecEltisVT<2, f64>,
157 SDTCisOpSmallerThanOp<0, 1>]>>;
158 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
159 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
160 SDTCVecEltisVT<0, f32>,
161 SDTCVecEltisVT<1, f64>,
162 SDTCVecEltisVT<2, f64>,
163 SDTCisOpSmallerThanOp<0, 1>,
166 def X86fpext : SDNode<"X86ISD::VFPEXT",
167 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
168 SDTCVecEltisVT<0, f64>,
169 SDTCVecEltisVT<1, f32>,
170 SDTCVecEltisVT<2, f32>,
171 SDTCisOpSmallerThanOp<1, 0>]>>;
173 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
174 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
175 SDTCVecEltisVT<0, f64>,
176 SDTCVecEltisVT<1, f32>,
177 SDTCVecEltisVT<2, f32>,
178 SDTCisOpSmallerThanOp<1, 0>,
181 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
182 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
183 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
184 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
185 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
187 def X86IntCmpMask : SDTypeProfile<1, 2,
188 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
189 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
190 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
193 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
194 SDTCisVec<1>, SDTCisSameAs<2, 1>,
195 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
196 def X86CmpMaskCCRound :
197 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
198 SDTCisVec<1>, SDTCisSameAs<2, 1>,
199 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
201 def X86CmpMaskCCScalar :
202 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
204 def X86CmpMaskCCScalarRound :
205 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
208 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
209 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
210 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
211 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
212 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
214 def X86vshl : SDNode<"X86ISD::VSHL",
215 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
217 def X86vsrl : SDNode<"X86ISD::VSRL",
218 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
220 def X86vsra : SDNode<"X86ISD::VSRA",
221 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
224 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
225 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
226 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
228 def X86vrotli : SDNode<"X86ISD::VROTLI", SDTIntShiftOp>;
229 def X86vrotri : SDNode<"X86ISD::VROTRI", SDTIntShiftOp>;
231 def X86vprot : SDNode<"X86ISD::VPROT",
232 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
233 SDTCisSameAs<0,2>]>>;
234 def X86vproti : SDNode<"X86ISD::VPROTI",
235 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
238 def X86vpshl : SDNode<"X86ISD::VPSHL",
239 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
240 SDTCisSameAs<0,2>]>>;
241 def X86vpsha : SDNode<"X86ISD::VPSHA",
242 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
243 SDTCisSameAs<0,2>]>>;
245 def X86vpcom : SDNode<"X86ISD::VPCOM",
246 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
249 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
250 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
254 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
256 SDTCisSameAs<2, 1>]>;
257 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
258 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
259 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
260 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
261 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
262 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
263 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
264 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
265 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
266 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
267 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
268 SDTCisVec<1>, SDTCisSameAs<2, 1>,
269 SDTCVecEltisVT<0, i1>,
270 SDTCisSameNumEltsAs<0, 1>]>>;
271 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
272 SDTCisVec<1>, SDTCisSameAs<2, 1>,
273 SDTCVecEltisVT<0, i1>,
274 SDTCisSameNumEltsAs<0, 1>]>>;
275 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
277 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
278 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
279 SDTCVecEltisVT<1, i32>,
280 SDTCisSameSizeAs<0,1>,
281 SDTCisSameAs<1,2>]>>;
282 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
283 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
284 SDTCVecEltisVT<1, i32>,
285 SDTCisSameSizeAs<0,1>,
286 SDTCisSameAs<1,2>]>>;
288 def X86extrqi : SDNode<"X86ISD::EXTRQI",
289 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
290 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
291 def X86insertqi : SDNode<"X86ISD::INSERTQI",
292 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
293 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
296 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
297 // translated into one of the target nodes below during lowering.
298 // Note: this is a work in progress...
299 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
300 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
303 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
304 SDTCisSameSizeAs<0,2>,
305 SDTCisSameNumEltsAs<0,2>]>;
306 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
307 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
308 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
309 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
310 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
311 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
312 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
313 SDTCisInt<2>, SDTCisInt<3>]>;
315 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
316 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
317 SDTCisInt<0>, SDTCisInt<1>]>;
319 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
320 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
322 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
323 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
326 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
327 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
329 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
330 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
332 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
333 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
334 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
335 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
336 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
337 SDTCisVec<0>, SDTCisVT<2, i32>]>;
338 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
339 SDTCisVec<0>, SDTCisVT<3, i32>]>;
340 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
341 SDTCisVec<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
343 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
344 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
346 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
347 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
349 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
350 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
351 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
353 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
354 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
356 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
357 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
358 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
360 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
361 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
363 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
364 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
365 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
367 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
368 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
370 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
371 SDTCisSameSizeAs<0,1>,
373 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
374 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
376 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
377 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
379 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
380 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
382 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
383 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
384 def X86VPermv : SDNode<"X86ISD::VPERMV",
385 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
386 SDTCisSameNumEltsAs<0,1>,
387 SDTCisSameSizeAs<0,1>,
388 SDTCisSameAs<0,2>]>>;
389 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
390 def X86VPermt2 : SDNode<"X86ISD::VPERMV3",
391 SDTypeProfile<1, 3, [SDTCisVec<0>,
392 SDTCisSameAs<0,1>, SDTCisInt<2>,
393 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
394 SDTCisSameSizeAs<0,2>,
395 SDTCisSameAs<0,3>]>, []>;
397 def X86VPermi2X : SDNode<"X86ISD::VPERMIV3",
398 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>,
399 SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>,
400 SDTCisSameSizeAs<0,1>,
402 SDTCisSameAs<0,3>]>, []>;
404 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
406 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
408 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
409 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
410 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
411 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
412 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
413 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
414 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
415 SDTCisVec<1>, SDTCisFP<1>,
416 SDTCisSameNumEltsAs<0,1>,
417 SDTCisVT<2, i32>]>, []>;
418 def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS",
419 SDTypeProfile<1, 2, [SDTCisVT<0, i1>,
420 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
422 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
423 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
424 SDTCisSubVecOfVec<1, 0>]>, []>;
425 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
426 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
427 SDTypeProfile<1, 1, [SDTCisVec<0>,
428 SDTCisSameAs<0,1>]>, []>;
430 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
431 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
432 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
433 [SDTCisSameAs<0, 1>, SDTCisEltOfVec<2, 1>,
434 SDTCisPtrTy<3>]>, []>;
435 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
436 [SDTCisEltOfVec<0, 1>, SDTCisVec<1>,
437 SDTCisPtrTy<2>]>, []>;
439 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
441 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
443 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
444 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
445 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
446 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
447 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
448 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
449 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
450 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
451 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
452 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
453 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
455 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
456 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
457 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
458 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
459 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
460 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
462 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
463 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
464 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
465 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
466 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
467 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
469 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
470 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
471 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
473 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
474 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
475 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
476 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
477 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
479 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
480 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
482 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
483 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
484 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
487 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
488 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
490 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
491 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
492 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
493 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
495 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
496 SDTCisSameAs<0,1>, SDTCisInt<2>,
499 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
500 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
501 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
502 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
504 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
505 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
506 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
507 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
508 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
509 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
510 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
511 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
512 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
513 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
515 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
516 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
519 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
520 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
522 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
523 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
527 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
528 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
530 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
531 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
532 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
533 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
534 // Vector with rounding mode
536 // cvtt fp-to-int staff
537 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
538 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
539 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
540 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
542 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
543 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
544 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
545 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
547 // cvt fp-to-int staff
548 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
549 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
550 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
551 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
553 // Vector without rounding mode
554 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
555 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
556 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
557 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
559 def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
560 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
561 SDTCVecEltisVT<0, f32>,
562 SDTCVecEltisVT<1, i16>,
564 SDTCisVT<2, i32>]> >;
566 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
567 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
568 SDTCVecEltisVT<0, i16>,
569 SDTCVecEltisVT<1, f32>,
570 SDTCisFP<1>, SDTCisVT<2, i32>,
571 SDTCisVT<3, i32>]> >;
572 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
573 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
574 SDTCisFP<0>, SDTCisFP<1>,
575 SDTCVecEltisVT<0, f64>,
576 SDTCVecEltisVT<1, f32>,
577 SDTCisOpSmallerThanOp<1, 0>,
579 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
580 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
581 SDTCisFP<0>, SDTCisFP<1>,
582 SDTCVecEltisVT<0, f32>,
583 SDTCVecEltisVT<1, f64>,
584 SDTCisOpSmallerThanOp<0, 1>,
587 def X86cvt2mask : SDNode<"X86ISD::CVT2MASK", SDTIntTruncOp>;
589 //===----------------------------------------------------------------------===//
590 // SSE Complex Patterns
591 //===----------------------------------------------------------------------===//
593 // These are 'extloads' from a scalar to the low element of a vector, zeroing
594 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
596 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
597 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
599 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
600 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
603 def ssmem : Operand<v4f32> {
604 let PrintMethod = "printf32mem";
605 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
606 let ParserMatchClass = X86Mem32AsmOperand;
607 let OperandType = "OPERAND_MEMORY";
609 def sdmem : Operand<v2f64> {
610 let PrintMethod = "printf64mem";
611 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
612 let ParserMatchClass = X86Mem64AsmOperand;
613 let OperandType = "OPERAND_MEMORY";
616 //===----------------------------------------------------------------------===//
617 // SSE pattern fragments
618 //===----------------------------------------------------------------------===//
620 // 128-bit load pattern fragments
621 // NOTE: all 128-bit integer vector loads are promoted to v2i64
622 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
623 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
624 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
626 // 256-bit load pattern fragments
627 // NOTE: all 256-bit integer vector loads are promoted to v4i64
628 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
629 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
630 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
632 // 512-bit load pattern fragments
633 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
634 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
635 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
636 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
637 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
638 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
640 // 128-/256-/512-bit extload pattern fragments
641 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
642 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
643 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
645 // These are needed to match a scalar load that is used in a vector-only
646 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
647 // The memory operand is required to be a 128-bit load, so it must be converted
648 // from a vector to a scalar.
649 def loadf32_128 : PatFrag<(ops node:$ptr),
650 (f32 (extractelt (loadv4f32 node:$ptr), (iPTR 0)))>;
651 def loadf64_128 : PatFrag<(ops node:$ptr),
652 (f64 (extractelt (loadv2f64 node:$ptr), (iPTR 0)))>;
654 // Like 'store', but always requires 128-bit vector alignment.
655 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
656 (store node:$val, node:$ptr), [{
657 return cast<StoreSDNode>(N)->getAlignment() >= 16;
660 // Like 'store', but always requires 256-bit vector alignment.
661 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
662 (store node:$val, node:$ptr), [{
663 return cast<StoreSDNode>(N)->getAlignment() >= 32;
666 // Like 'store', but always requires 512-bit vector alignment.
667 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
668 (store node:$val, node:$ptr), [{
669 return cast<StoreSDNode>(N)->getAlignment() >= 64;
672 // Like 'load', but always requires 128-bit vector alignment.
673 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
674 return cast<LoadSDNode>(N)->getAlignment() >= 16;
677 // Like 'X86vzload', but always requires 128-bit vector alignment.
678 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
679 return cast<MemSDNode>(N)->getAlignment() >= 16;
682 // Like 'load', but always requires 256-bit vector alignment.
683 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
684 return cast<LoadSDNode>(N)->getAlignment() >= 32;
687 // Like 'load', but always requires 512-bit vector alignment.
688 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
689 return cast<LoadSDNode>(N)->getAlignment() >= 64;
692 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
693 (f32 (alignedload node:$ptr))>;
694 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
695 (f64 (alignedload node:$ptr))>;
697 // 128-bit aligned load pattern fragments
698 // NOTE: all 128-bit integer vector loads are promoted to v2i64
699 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
700 (v4f32 (alignedload node:$ptr))>;
701 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
702 (v2f64 (alignedload node:$ptr))>;
703 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
704 (v2i64 (alignedload node:$ptr))>;
706 // 256-bit aligned load pattern fragments
707 // NOTE: all 256-bit integer vector loads are promoted to v4i64
708 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
709 (v8f32 (alignedload256 node:$ptr))>;
710 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
711 (v4f64 (alignedload256 node:$ptr))>;
712 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
713 (v4i64 (alignedload256 node:$ptr))>;
715 // 512-bit aligned load pattern fragments
716 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
717 (v16f32 (alignedload512 node:$ptr))>;
718 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
719 (v16i32 (alignedload512 node:$ptr))>;
720 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
721 (v8f64 (alignedload512 node:$ptr))>;
722 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
723 (v8i64 (alignedload512 node:$ptr))>;
725 // Like 'load', but uses special alignment checks suitable for use in
726 // memory operands in most SSE instructions, which are required to
727 // be naturally aligned on some targets but not on others. If the subtarget
728 // allows unaligned accesses, match any load, though this may require
729 // setting a feature bit in the processor (on startup, for example).
730 // Opteron 10h and later implement such a feature.
731 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
732 return Subtarget->hasSSEUnalignedMem()
733 || cast<LoadSDNode>(N)->getAlignment() >= 16;
736 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
737 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
739 // 128-bit memop pattern fragments
740 // NOTE: all 128-bit integer vector loads are promoted to v2i64
741 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
742 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
743 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
745 // These are needed to match a scalar memop that is used in a vector-only
746 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
747 // The memory operand is required to be a 128-bit load, so it must be converted
748 // from a vector to a scalar.
749 def memopfsf32_128 : PatFrag<(ops node:$ptr),
750 (f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
751 def memopfsf64_128 : PatFrag<(ops node:$ptr),
752 (f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;
755 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
757 // FIXME: 8 byte alignment for mmx reads is not required
758 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
759 return cast<LoadSDNode>(N)->getAlignment() >= 8;
762 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
764 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
765 (masked_gather node:$src1, node:$src2, node:$src3) , [{
766 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
767 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
768 Mgt->getBasePtr().getValueType() == MVT::v4i32);
772 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
773 (masked_gather node:$src1, node:$src2, node:$src3) , [{
774 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
775 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
776 Mgt->getBasePtr().getValueType() == MVT::v8i32);
780 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
781 (masked_gather node:$src1, node:$src2, node:$src3) , [{
782 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
783 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
784 Mgt->getBasePtr().getValueType() == MVT::v2i64);
787 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
788 (masked_gather node:$src1, node:$src2, node:$src3) , [{
789 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
790 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
791 Mgt->getBasePtr().getValueType() == MVT::v4i64);
794 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
795 (masked_gather node:$src1, node:$src2, node:$src3) , [{
796 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
797 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
798 Mgt->getBasePtr().getValueType() == MVT::v8i64);
801 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
802 (masked_gather node:$src1, node:$src2, node:$src3) , [{
803 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
804 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
805 Mgt->getBasePtr().getValueType() == MVT::v16i32);
809 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
810 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
811 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
812 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
813 Sc->getBasePtr().getValueType() == MVT::v2i64);
817 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
818 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
819 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
820 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
821 Sc->getBasePtr().getValueType() == MVT::v4i32);
825 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
826 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
827 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
828 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
829 Sc->getBasePtr().getValueType() == MVT::v4i64);
833 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
834 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
835 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
836 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
837 Sc->getBasePtr().getValueType() == MVT::v8i32);
841 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
842 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
843 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
844 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
845 Sc->getBasePtr().getValueType() == MVT::v8i64);
848 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
849 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
850 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
851 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
852 Sc->getBasePtr().getValueType() == MVT::v16i32);
856 // 128-bit bitconvert pattern fragments
857 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
858 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
859 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
860 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
861 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
862 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
864 // 256-bit bitconvert pattern fragments
865 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
866 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
867 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
868 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
869 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
871 // 512-bit bitconvert pattern fragments
872 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
873 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
874 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
875 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
877 def vzmovl_v2i64 : PatFrag<(ops node:$src),
878 (bitconvert (v2i64 (X86vzmovl
879 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
880 def vzmovl_v4i32 : PatFrag<(ops node:$src),
881 (bitconvert (v4i32 (X86vzmovl
882 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
884 def vzload_v2i64 : PatFrag<(ops node:$src),
885 (bitconvert (v2i64 (X86vzload node:$src)))>;
888 def fp32imm0 : PatLeaf<(f32 fpimm), [{
889 return N->isExactlyValue(+0.0);
892 def I8Imm : SDNodeXForm<imm, [{
893 // Transformation function: get the low 8 bits.
894 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
897 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
898 def FROUND_CURRENT : ImmLeaf<i32, [{
899 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
902 // BYTE_imm - Transform bit immediates into byte immediates.
903 def BYTE_imm : SDNodeXForm<imm, [{
904 // Transformation function: imm >> 3
905 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
908 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
909 // to VEXTRACTF128/VEXTRACTI128 imm.
910 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
911 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
914 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
915 // VINSERTF128/VINSERTI128 imm.
916 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
917 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
920 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
921 // to VEXTRACTF64x4 imm.
922 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
923 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
926 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
928 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
929 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
932 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
933 (extract_subvector node:$bigvec,
935 return X86::isVEXTRACT128Index(N);
936 }], EXTRACT_get_vextract128_imm>;
938 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
940 (insert_subvector node:$bigvec, node:$smallvec,
942 return X86::isVINSERT128Index(N);
943 }], INSERT_get_vinsert128_imm>;
946 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
947 (extract_subvector node:$bigvec,
949 return X86::isVEXTRACT256Index(N);
950 }], EXTRACT_get_vextract256_imm>;
952 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
954 (insert_subvector node:$bigvec, node:$smallvec,
956 return X86::isVINSERT256Index(N);
957 }], INSERT_get_vinsert256_imm>;
959 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
960 (masked_load node:$src1, node:$src2, node:$src3), [{
961 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
962 return Load->getAlignment() >= 16;
966 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
967 (masked_load node:$src1, node:$src2, node:$src3), [{
968 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
969 return Load->getAlignment() >= 32;
973 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
974 (masked_load node:$src1, node:$src2, node:$src3), [{
975 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
976 return Load->getAlignment() >= 64;
980 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
981 (masked_load node:$src1, node:$src2, node:$src3), [{
982 return isa<MaskedLoadSDNode>(N);
985 // masked store fragments.
986 // X86mstore can't be implemented in core DAG files because some targets
987 // doesn't support vector type ( llvm-tblgen will fail)
988 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
989 (masked_store node:$src1, node:$src2, node:$src3), [{
990 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
993 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
994 (X86mstore node:$src1, node:$src2, node:$src3), [{
995 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
996 return Store->getAlignment() >= 16;
1000 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1001 (X86mstore node:$src1, node:$src2, node:$src3), [{
1002 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
1003 return Store->getAlignment() >= 32;
1007 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1008 (X86mstore node:$src1, node:$src2, node:$src3), [{
1009 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
1010 return Store->getAlignment() >= 64;
1014 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1015 (X86mstore node:$src1, node:$src2, node:$src3), [{
1016 return isa<MaskedStoreSDNode>(N);
1019 // masked truncstore fragments
1020 // X86mtruncstore can't be implemented in core DAG files because some targets
1021 // doesn't support vector type ( llvm-tblgen will fail)
1022 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1023 (masked_store node:$src1, node:$src2, node:$src3), [{
1024 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1026 def masked_truncstorevi8 :
1027 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1028 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1029 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1031 def masked_truncstorevi16 :
1032 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1033 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1034 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1036 def masked_truncstorevi32 :
1037 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1038 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1039 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;