1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86andnp : SDNode<"X86ISD::ANDNP",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86psign : SDNode<"X86ISD::PSIGN",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86pextrb : SDNode<"X86ISD::PEXTRB",
89 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
90 def X86pextrw : SDNode<"X86ISD::PEXTRW",
91 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
92 def X86pinsrb : SDNode<"X86ISD::PINSRB",
93 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
94 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
95 def X86pinsrw : SDNode<"X86ISD::PINSRW",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98 def X86insertps : SDNode<"X86ISD::INSERTPS",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
101 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
102 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
104 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
105 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
107 def X86vzext : SDNode<"X86ISD::VZEXT",
108 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
109 SDTCisInt<0>, SDTCisInt<1>,
110 SDTCisOpSmallerThanOp<1, 0>]>>;
112 def X86vsext : SDNode<"X86ISD::VSEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
118 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
119 SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<0, 1>]>>;
121 def X86trunc : SDNode<"X86ISD::TRUNC",
122 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
123 SDTCisOpSmallerThanOp<0, 1>]>>;
125 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
126 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
127 SDTCisInt<0>, SDTCisInt<1>,
128 SDTCisVec<2>, SDTCisInt<2>,
129 SDTCisOpSmallerThanOp<0, 2>]>>;
130 def X86vfpext : SDNode<"X86ISD::VFPEXT",
131 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
132 SDTCisFP<0>, SDTCisFP<1>,
133 SDTCisOpSmallerThanOp<1, 0>]>>;
134 def X86vfpround: SDNode<"X86ISD::VFPROUND",
135 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
136 SDTCisFP<0>, SDTCisFP<1>,
137 SDTCisOpSmallerThanOp<0, 1>]>>;
139 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
140 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
141 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
142 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
143 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
145 def X86IntCmpMask : SDTypeProfile<1, 2,
146 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
147 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
148 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
151 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
152 SDTCisVec<1>, SDTCisSameAs<2, 1>,
153 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
154 def X86CmpMaskCCRound :
155 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
156 SDTCisVec<1>, SDTCisSameAs<2, 1>,
157 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
159 def X86CmpMaskCCScalar :
160 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
162 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
163 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
164 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
165 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
167 def X86vshl : SDNode<"X86ISD::VSHL",
168 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
170 def X86vsrl : SDNode<"X86ISD::VSRL",
171 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
173 def X86vsra : SDNode<"X86ISD::VSRA",
174 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
177 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
178 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
179 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
181 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
183 SDTCisSameAs<2, 1>]>;
184 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
185 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
186 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
187 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
188 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
189 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
190 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
191 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
192 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
193 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
194 SDTCisVec<1>, SDTCisSameAs<2, 1>,
195 SDTCVecEltisVT<0, i1>,
196 SDTCisSameNumEltsAs<0, 1>]>>;
197 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
198 SDTCisVec<1>, SDTCisSameAs<2, 1>,
199 SDTCVecEltisVT<0, i1>,
200 SDTCisSameNumEltsAs<0, 1>]>>;
201 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
203 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
204 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
205 SDTCisSameAs<1,2>]>>;
206 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
207 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
208 SDTCisSameAs<1,2>]>>;
210 def X86extrqi : SDNode<"X86ISD::EXTRQI",
211 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
212 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
213 def X86insertqi : SDNode<"X86ISD::INSERTQI",
214 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
215 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
218 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
219 // translated into one of the target nodes below during lowering.
220 // Note: this is a work in progress...
221 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
222 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
224 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
227 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
229 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
230 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
231 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
232 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
233 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
236 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
237 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
239 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
240 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
242 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
243 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
245 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
246 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
248 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
249 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
250 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
251 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
252 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
253 SDTCisVec<0>, SDTCisInt<2>]>;
254 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
255 SDTCisVec<0>, SDTCisInt<3>]>;
256 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
257 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
259 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
260 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
261 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
263 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
264 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
265 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
267 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
268 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
270 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
271 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
272 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
274 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
275 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
277 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
278 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
279 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
281 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
282 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
284 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
285 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
286 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
288 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
289 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
291 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
292 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
293 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
294 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
295 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
296 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
298 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
300 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
301 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
303 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
304 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
305 SDTCisSubVecOfVec<1, 0>]>, []>;
306 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
307 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
308 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
309 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
310 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
312 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
314 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
316 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
317 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
318 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
319 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
320 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
321 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
322 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
323 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
324 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
326 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
327 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
328 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
329 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
330 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
331 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
333 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
334 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
335 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
336 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
337 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
338 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
340 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
341 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
342 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
344 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
345 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
346 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
348 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
349 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
351 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
352 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
353 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
356 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
357 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
359 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
360 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
361 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
362 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
364 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
365 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
367 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
368 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
369 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
370 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
372 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
373 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
374 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
375 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
377 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
378 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
380 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
381 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
384 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
385 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
387 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
388 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
392 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
393 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
395 // Vector with rounding mode
397 // cvtt fp-to-int staff
398 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
399 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
400 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
401 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
403 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
404 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
405 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
406 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
408 // cvt fp-to-int staff
409 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
410 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
411 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
412 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
414 // Vector without rounding mode
415 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
416 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
417 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
418 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
420 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
421 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
422 SDTCisFP<0>, SDTCisFP<1>,
423 SDTCisOpSmallerThanOp<1, 0>,
425 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
426 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
427 SDTCisFP<0>, SDTCisFP<1>,
428 SDTCVecEltisVT<0, f32>,
429 SDTCVecEltisVT<1, f64>,
432 //===----------------------------------------------------------------------===//
433 // SSE Complex Patterns
434 //===----------------------------------------------------------------------===//
436 // These are 'extloads' from a scalar to the low element of a vector, zeroing
437 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
439 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
440 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
442 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
443 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
446 def ssmem : Operand<v4f32> {
447 let PrintMethod = "printf32mem";
448 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
449 let ParserMatchClass = X86Mem32AsmOperand;
450 let OperandType = "OPERAND_MEMORY";
452 def sdmem : Operand<v2f64> {
453 let PrintMethod = "printf64mem";
454 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
455 let ParserMatchClass = X86Mem64AsmOperand;
456 let OperandType = "OPERAND_MEMORY";
459 //===----------------------------------------------------------------------===//
460 // SSE pattern fragments
461 //===----------------------------------------------------------------------===//
463 // 128-bit load pattern fragments
464 // NOTE: all 128-bit integer vector loads are promoted to v2i64
465 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
466 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
467 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
469 // 256-bit load pattern fragments
470 // NOTE: all 256-bit integer vector loads are promoted to v4i64
471 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
472 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
473 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
475 // 512-bit load pattern fragments
476 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
477 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
478 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
479 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
480 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
481 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
483 // 128-/256-/512-bit extload pattern fragments
484 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
485 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
486 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
488 // These are needed to match a scalar load that is used in a vector-only
489 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
490 // The memory operand is required to be a 128-bit load, so it must be converted
491 // from a vector to a scalar.
492 def loadf32_128 : PatFrag<(ops node:$ptr),
493 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
494 def loadf64_128 : PatFrag<(ops node:$ptr),
495 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
497 // Like 'store', but always requires 128-bit vector alignment.
498 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
499 (store node:$val, node:$ptr), [{
500 return cast<StoreSDNode>(N)->getAlignment() >= 16;
503 // Like 'store', but always requires 256-bit vector alignment.
504 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
505 (store node:$val, node:$ptr), [{
506 return cast<StoreSDNode>(N)->getAlignment() >= 32;
509 // Like 'store', but always requires 512-bit vector alignment.
510 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
511 (store node:$val, node:$ptr), [{
512 return cast<StoreSDNode>(N)->getAlignment() >= 64;
515 // Like 'load', but always requires 128-bit vector alignment.
516 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
517 return cast<LoadSDNode>(N)->getAlignment() >= 16;
520 // Like 'X86vzload', but always requires 128-bit vector alignment.
521 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
522 return cast<MemSDNode>(N)->getAlignment() >= 16;
525 // Like 'load', but always requires 256-bit vector alignment.
526 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
527 return cast<LoadSDNode>(N)->getAlignment() >= 32;
530 // Like 'load', but always requires 512-bit vector alignment.
531 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
532 return cast<LoadSDNode>(N)->getAlignment() >= 64;
535 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
536 (f32 (alignedload node:$ptr))>;
537 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
538 (f64 (alignedload node:$ptr))>;
540 // 128-bit aligned load pattern fragments
541 // NOTE: all 128-bit integer vector loads are promoted to v2i64
542 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
543 (v4f32 (alignedload node:$ptr))>;
544 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
545 (v2f64 (alignedload node:$ptr))>;
546 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
547 (v2i64 (alignedload node:$ptr))>;
549 // 256-bit aligned load pattern fragments
550 // NOTE: all 256-bit integer vector loads are promoted to v4i64
551 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
552 (v8f32 (alignedload256 node:$ptr))>;
553 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
554 (v4f64 (alignedload256 node:$ptr))>;
555 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
556 (v4i64 (alignedload256 node:$ptr))>;
558 // 512-bit aligned load pattern fragments
559 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
560 (v16f32 (alignedload512 node:$ptr))>;
561 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
562 (v16i32 (alignedload512 node:$ptr))>;
563 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
564 (v8f64 (alignedload512 node:$ptr))>;
565 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
566 (v8i64 (alignedload512 node:$ptr))>;
568 // Like 'load', but uses special alignment checks suitable for use in
569 // memory operands in most SSE instructions, which are required to
570 // be naturally aligned on some targets but not on others. If the subtarget
571 // allows unaligned accesses, match any load, though this may require
572 // setting a feature bit in the processor (on startup, for example).
573 // Opteron 10h and later implement such a feature.
574 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
575 return Subtarget->hasSSEUnalignedMem()
576 || cast<LoadSDNode>(N)->getAlignment() >= 16;
579 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
580 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
582 // 128-bit memop pattern fragments
583 // NOTE: all 128-bit integer vector loads are promoted to v2i64
584 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
585 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
586 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
588 // These are needed to match a scalar memop that is used in a vector-only
589 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
590 // The memory operand is required to be a 128-bit load, so it must be converted
591 // from a vector to a scalar.
592 def memopfsf32_128 : PatFrag<(ops node:$ptr),
593 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
594 def memopfsf64_128 : PatFrag<(ops node:$ptr),
595 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
598 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
600 // FIXME: 8 byte alignment for mmx reads is not required
601 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
602 return cast<LoadSDNode>(N)->getAlignment() >= 8;
605 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
608 // Like 'store', but requires the non-temporal bit to be set
609 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
610 (st node:$val, node:$ptr), [{
611 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
612 return ST->isNonTemporal();
616 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
617 (st node:$val, node:$ptr), [{
618 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
619 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
620 ST->getAddressingMode() == ISD::UNINDEXED &&
621 ST->getAlignment() >= 16;
625 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
626 (st node:$val, node:$ptr), [{
627 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
628 return ST->isNonTemporal() &&
629 ST->getAlignment() < 16;
633 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
634 (masked_gather node:$src1, node:$src2, node:$src3) , [{
635 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
636 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
637 Mgt->getBasePtr().getValueType() == MVT::v4i32);
641 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
642 (masked_gather node:$src1, node:$src2, node:$src3) , [{
643 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
644 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
645 Mgt->getBasePtr().getValueType() == MVT::v8i32);
649 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
650 (masked_gather node:$src1, node:$src2, node:$src3) , [{
651 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
652 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
653 Mgt->getBasePtr().getValueType() == MVT::v2i64);
656 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
657 (masked_gather node:$src1, node:$src2, node:$src3) , [{
658 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
659 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
660 Mgt->getBasePtr().getValueType() == MVT::v4i64);
663 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
664 (masked_gather node:$src1, node:$src2, node:$src3) , [{
665 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
666 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
667 Mgt->getBasePtr().getValueType() == MVT::v8i64);
670 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
671 (masked_gather node:$src1, node:$src2, node:$src3) , [{
672 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
673 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
674 Mgt->getBasePtr().getValueType() == MVT::v16i32);
678 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
679 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
680 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
681 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
682 Sc->getBasePtr().getValueType() == MVT::v2i64);
686 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
687 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
688 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
689 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
690 Sc->getBasePtr().getValueType() == MVT::v4i32);
694 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
695 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
696 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
697 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
698 Sc->getBasePtr().getValueType() == MVT::v4i64);
702 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
703 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
704 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
705 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
706 Sc->getBasePtr().getValueType() == MVT::v8i32);
710 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
711 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
712 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
713 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
714 Sc->getBasePtr().getValueType() == MVT::v8i64);
717 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
718 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
719 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
720 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
721 Sc->getBasePtr().getValueType() == MVT::v16i32);
725 // 128-bit bitconvert pattern fragments
726 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
727 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
728 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
729 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
730 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
731 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
733 // 256-bit bitconvert pattern fragments
734 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
735 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
736 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
737 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
738 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
740 // 512-bit bitconvert pattern fragments
741 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
742 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
743 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
744 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
746 def vzmovl_v2i64 : PatFrag<(ops node:$src),
747 (bitconvert (v2i64 (X86vzmovl
748 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
749 def vzmovl_v4i32 : PatFrag<(ops node:$src),
750 (bitconvert (v4i32 (X86vzmovl
751 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
753 def vzload_v2i64 : PatFrag<(ops node:$src),
754 (bitconvert (v2i64 (X86vzload node:$src)))>;
757 def fp32imm0 : PatLeaf<(f32 fpimm), [{
758 return N->isExactlyValue(+0.0);
761 def I8Imm : SDNodeXForm<imm, [{
762 // Transformation function: get the low 8 bits.
763 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
766 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
767 def FROUND_CURRENT : ImmLeaf<i32, [{
768 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
771 // BYTE_imm - Transform bit immediates into byte immediates.
772 def BYTE_imm : SDNodeXForm<imm, [{
773 // Transformation function: imm >> 3
774 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
777 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
778 // to VEXTRACTF128/VEXTRACTI128 imm.
779 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
780 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
783 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
784 // VINSERTF128/VINSERTI128 imm.
785 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
786 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
789 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
790 // to VEXTRACTF64x4 imm.
791 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
792 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
795 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
797 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
798 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
801 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
802 (extract_subvector node:$bigvec,
804 return X86::isVEXTRACT128Index(N);
805 }], EXTRACT_get_vextract128_imm>;
807 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
809 (insert_subvector node:$bigvec, node:$smallvec,
811 return X86::isVINSERT128Index(N);
812 }], INSERT_get_vinsert128_imm>;
815 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
816 (extract_subvector node:$bigvec,
818 return X86::isVEXTRACT256Index(N);
819 }], EXTRACT_get_vextract256_imm>;
821 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
823 (insert_subvector node:$bigvec, node:$smallvec,
825 return X86::isVINSERT256Index(N);
826 }], INSERT_get_vinsert256_imm>;
828 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
829 (masked_load node:$src1, node:$src2, node:$src3), [{
830 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
831 return Load->getAlignment() >= 16;
835 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
836 (masked_load node:$src1, node:$src2, node:$src3), [{
837 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
838 return Load->getAlignment() >= 32;
842 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
843 (masked_load node:$src1, node:$src2, node:$src3), [{
844 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
845 return Load->getAlignment() >= 64;
849 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
850 (masked_load node:$src1, node:$src2, node:$src3), [{
851 return isa<MaskedLoadSDNode>(N);
854 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
855 (masked_store node:$src1, node:$src2, node:$src3), [{
856 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
857 return Store->getAlignment() >= 16;
861 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
862 (masked_store node:$src1, node:$src2, node:$src3), [{
863 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
864 return Store->getAlignment() >= 32;
868 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
869 (masked_store node:$src1, node:$src2, node:$src3), [{
870 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
871 return Store->getAlignment() >= 64;
875 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
876 (masked_store node:$src1, node:$src2, node:$src3), [{
877 return isa<MaskedStoreSDNode>(N);