1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86andnp : SDNode<"X86ISD::ANDNP",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86psign : SDNode<"X86ISD::PSIGN",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86pextrb : SDNode<"X86ISD::PEXTRB",
89 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
90 def X86pextrw : SDNode<"X86ISD::PEXTRW",
91 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
92 def X86pinsrb : SDNode<"X86ISD::PINSRB",
93 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
94 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
95 def X86pinsrw : SDNode<"X86ISD::PINSRW",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98 def X86insertps : SDNode<"X86ISD::INSERTPS",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
101 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
102 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
104 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
105 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
107 def X86vzext : SDNode<"X86ISD::VZEXT",
108 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
109 SDTCisInt<0>, SDTCisInt<1>,
110 SDTCisOpSmallerThanOp<1, 0>]>>;
112 def X86vsext : SDNode<"X86ISD::VSEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<0, 1>]>;
121 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
122 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
123 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
125 def X86trunc : SDNode<"X86ISD::TRUNC",
126 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
127 SDTCisOpSmallerThanOp<0, 1>]>>;
128 def X86vfpext : SDNode<"X86ISD::VFPEXT",
129 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
130 SDTCisFP<0>, SDTCisFP<1>,
131 SDTCisOpSmallerThanOp<1, 0>]>>;
132 def X86vfpround: SDNode<"X86ISD::VFPROUND",
133 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
134 SDTCisFP<0>, SDTCisFP<1>,
135 SDTCisOpSmallerThanOp<0, 1>]>>;
137 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
138 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
139 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
140 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
141 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
143 def X86IntCmpMask : SDTypeProfile<1, 2,
144 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
145 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
146 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
149 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
150 SDTCisVec<1>, SDTCisSameAs<2, 1>,
151 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
152 def X86CmpMaskCCRound :
153 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
154 SDTCisVec<1>, SDTCisSameAs<2, 1>,
155 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
157 def X86CmpMaskCCScalar :
158 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
160 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
161 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
162 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
163 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
165 def X86vshl : SDNode<"X86ISD::VSHL",
166 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
168 def X86vsrl : SDNode<"X86ISD::VSRL",
169 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
171 def X86vsra : SDNode<"X86ISD::VSRA",
172 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
175 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
176 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
177 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
179 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
181 SDTCisSameAs<2, 1>]>;
182 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
183 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
184 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
185 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
186 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
187 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
188 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
189 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
190 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
191 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
192 SDTCisVec<1>, SDTCisSameAs<2, 1>,
193 SDTCVecEltisVT<0, i1>,
194 SDTCisSameNumEltsAs<0, 1>]>>;
195 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
196 SDTCisVec<1>, SDTCisSameAs<2, 1>,
197 SDTCVecEltisVT<0, i1>,
198 SDTCisSameNumEltsAs<0, 1>]>>;
199 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
201 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
202 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
203 SDTCisSameAs<1,2>]>>;
204 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
206 SDTCisSameAs<1,2>]>>;
208 def X86extrqi : SDNode<"X86ISD::EXTRQI",
209 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
210 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
211 def X86insertqi : SDNode<"X86ISD::INSERTQI",
212 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
213 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
216 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
217 // translated into one of the target nodes below during lowering.
218 // Note: this is a work in progress...
219 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
220 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
222 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
223 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
225 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
228 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
229 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
230 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
231 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
232 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
233 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisInt<2>, SDTCisInt<3>]>;
236 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
237 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
239 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
240 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
242 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
243 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
245 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
246 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
248 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
249 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
250 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
251 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
252 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
253 SDTCisVec<0>, SDTCisInt<2>]>;
254 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
255 SDTCisVec<0>, SDTCisInt<3>]>;
256 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
257 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
259 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
260 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
261 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
263 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
264 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
265 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
267 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
268 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
270 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
271 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
272 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
274 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
275 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
277 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
278 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
279 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
281 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
282 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
284 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
285 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
286 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
288 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
289 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
291 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
292 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
294 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
295 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
296 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
297 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
298 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
299 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
301 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
303 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
304 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
305 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
306 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
308 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
309 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
310 SDTCisSubVecOfVec<1, 0>]>, []>;
311 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
312 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
313 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
314 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
315 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
317 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
319 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
321 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
322 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
323 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
324 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
325 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
326 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
327 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
328 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
329 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
331 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
332 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
333 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
334 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
335 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
336 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
338 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
339 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
340 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
341 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
342 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
343 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
345 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
346 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
347 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
349 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
350 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
351 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
352 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
354 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
355 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
357 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
358 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
359 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
362 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
363 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
365 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
366 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
367 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
368 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
370 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
371 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
373 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
374 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
375 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
376 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
378 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
379 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
380 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
381 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
383 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
384 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
386 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
387 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
390 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
391 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
393 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
394 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
398 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
399 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
401 // Vector with rounding mode
403 // cvtt fp-to-int staff
404 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
405 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
406 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
407 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
409 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
410 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
411 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
412 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
414 // cvt fp-to-int staff
415 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
416 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
417 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
418 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
420 // Vector without rounding mode
421 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
422 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
423 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
424 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
426 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
427 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
428 SDTCisFP<0>, SDTCisFP<1>,
429 SDTCisOpSmallerThanOp<1, 0>,
431 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
432 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
433 SDTCisFP<0>, SDTCisFP<1>,
434 SDTCVecEltisVT<0, f32>,
435 SDTCVecEltisVT<1, f64>,
438 //===----------------------------------------------------------------------===//
439 // SSE Complex Patterns
440 //===----------------------------------------------------------------------===//
442 // These are 'extloads' from a scalar to the low element of a vector, zeroing
443 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
445 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
446 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
448 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
449 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
452 def ssmem : Operand<v4f32> {
453 let PrintMethod = "printf32mem";
454 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
455 let ParserMatchClass = X86Mem32AsmOperand;
456 let OperandType = "OPERAND_MEMORY";
458 def sdmem : Operand<v2f64> {
459 let PrintMethod = "printf64mem";
460 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
461 let ParserMatchClass = X86Mem64AsmOperand;
462 let OperandType = "OPERAND_MEMORY";
465 //===----------------------------------------------------------------------===//
466 // SSE pattern fragments
467 //===----------------------------------------------------------------------===//
469 // 128-bit load pattern fragments
470 // NOTE: all 128-bit integer vector loads are promoted to v2i64
471 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
472 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
473 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
475 // 256-bit load pattern fragments
476 // NOTE: all 256-bit integer vector loads are promoted to v4i64
477 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
478 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
479 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
481 // 512-bit load pattern fragments
482 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
483 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
484 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
485 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
486 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
487 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
489 // 128-/256-/512-bit extload pattern fragments
490 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
491 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
492 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
494 // These are needed to match a scalar load that is used in a vector-only
495 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
496 // The memory operand is required to be a 128-bit load, so it must be converted
497 // from a vector to a scalar.
498 def loadf32_128 : PatFrag<(ops node:$ptr),
499 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
500 def loadf64_128 : PatFrag<(ops node:$ptr),
501 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
503 // Like 'store', but always requires 128-bit vector alignment.
504 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
505 (store node:$val, node:$ptr), [{
506 return cast<StoreSDNode>(N)->getAlignment() >= 16;
509 // Like 'store', but always requires 256-bit vector alignment.
510 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
511 (store node:$val, node:$ptr), [{
512 return cast<StoreSDNode>(N)->getAlignment() >= 32;
515 // Like 'store', but always requires 512-bit vector alignment.
516 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
517 (store node:$val, node:$ptr), [{
518 return cast<StoreSDNode>(N)->getAlignment() >= 64;
521 // Like 'load', but always requires 128-bit vector alignment.
522 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
523 return cast<LoadSDNode>(N)->getAlignment() >= 16;
526 // Like 'X86vzload', but always requires 128-bit vector alignment.
527 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
528 return cast<MemSDNode>(N)->getAlignment() >= 16;
531 // Like 'load', but always requires 256-bit vector alignment.
532 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
533 return cast<LoadSDNode>(N)->getAlignment() >= 32;
536 // Like 'load', but always requires 512-bit vector alignment.
537 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
538 return cast<LoadSDNode>(N)->getAlignment() >= 64;
541 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
542 (f32 (alignedload node:$ptr))>;
543 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
544 (f64 (alignedload node:$ptr))>;
546 // 128-bit aligned load pattern fragments
547 // NOTE: all 128-bit integer vector loads are promoted to v2i64
548 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
549 (v4f32 (alignedload node:$ptr))>;
550 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
551 (v2f64 (alignedload node:$ptr))>;
552 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
553 (v2i64 (alignedload node:$ptr))>;
555 // 256-bit aligned load pattern fragments
556 // NOTE: all 256-bit integer vector loads are promoted to v4i64
557 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
558 (v8f32 (alignedload256 node:$ptr))>;
559 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
560 (v4f64 (alignedload256 node:$ptr))>;
561 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
562 (v4i64 (alignedload256 node:$ptr))>;
564 // 512-bit aligned load pattern fragments
565 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
566 (v16f32 (alignedload512 node:$ptr))>;
567 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
568 (v16i32 (alignedload512 node:$ptr))>;
569 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
570 (v8f64 (alignedload512 node:$ptr))>;
571 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
572 (v8i64 (alignedload512 node:$ptr))>;
574 // Like 'load', but uses special alignment checks suitable for use in
575 // memory operands in most SSE instructions, which are required to
576 // be naturally aligned on some targets but not on others. If the subtarget
577 // allows unaligned accesses, match any load, though this may require
578 // setting a feature bit in the processor (on startup, for example).
579 // Opteron 10h and later implement such a feature.
580 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
581 return Subtarget->hasSSEUnalignedMem()
582 || cast<LoadSDNode>(N)->getAlignment() >= 16;
585 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
586 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
588 // 128-bit memop pattern fragments
589 // NOTE: all 128-bit integer vector loads are promoted to v2i64
590 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
591 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
592 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
594 // These are needed to match a scalar memop that is used in a vector-only
595 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
596 // The memory operand is required to be a 128-bit load, so it must be converted
597 // from a vector to a scalar.
598 def memopfsf32_128 : PatFrag<(ops node:$ptr),
599 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
600 def memopfsf64_128 : PatFrag<(ops node:$ptr),
601 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
604 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
606 // FIXME: 8 byte alignment for mmx reads is not required
607 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
608 return cast<LoadSDNode>(N)->getAlignment() >= 8;
611 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
614 // Like 'store', but requires the non-temporal bit to be set
615 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
616 (st node:$val, node:$ptr), [{
617 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
618 return ST->isNonTemporal();
622 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
623 (st node:$val, node:$ptr), [{
624 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
625 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
626 ST->getAddressingMode() == ISD::UNINDEXED &&
627 ST->getAlignment() >= 16;
631 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
632 (st node:$val, node:$ptr), [{
633 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
634 return ST->isNonTemporal() &&
635 ST->getAlignment() < 16;
639 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
640 (masked_gather node:$src1, node:$src2, node:$src3) , [{
641 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
642 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
643 Mgt->getBasePtr().getValueType() == MVT::v4i32);
647 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
648 (masked_gather node:$src1, node:$src2, node:$src3) , [{
649 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
650 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
651 Mgt->getBasePtr().getValueType() == MVT::v8i32);
655 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
656 (masked_gather node:$src1, node:$src2, node:$src3) , [{
657 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
658 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
659 Mgt->getBasePtr().getValueType() == MVT::v2i64);
662 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
663 (masked_gather node:$src1, node:$src2, node:$src3) , [{
664 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
665 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
666 Mgt->getBasePtr().getValueType() == MVT::v4i64);
669 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
670 (masked_gather node:$src1, node:$src2, node:$src3) , [{
671 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
672 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
673 Mgt->getBasePtr().getValueType() == MVT::v8i64);
676 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
677 (masked_gather node:$src1, node:$src2, node:$src3) , [{
678 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
679 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
680 Mgt->getBasePtr().getValueType() == MVT::v16i32);
684 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
685 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
686 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
687 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
688 Sc->getBasePtr().getValueType() == MVT::v2i64);
692 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
693 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
694 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
695 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
696 Sc->getBasePtr().getValueType() == MVT::v4i32);
700 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
701 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
702 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
703 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
704 Sc->getBasePtr().getValueType() == MVT::v4i64);
708 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
709 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
710 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
711 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
712 Sc->getBasePtr().getValueType() == MVT::v8i32);
716 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
717 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
718 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
719 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
720 Sc->getBasePtr().getValueType() == MVT::v8i64);
723 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
724 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
725 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
726 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
727 Sc->getBasePtr().getValueType() == MVT::v16i32);
731 // 128-bit bitconvert pattern fragments
732 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
733 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
734 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
735 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
736 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
737 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
739 // 256-bit bitconvert pattern fragments
740 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
741 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
742 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
743 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
744 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
746 // 512-bit bitconvert pattern fragments
747 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
748 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
749 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
750 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
752 def vzmovl_v2i64 : PatFrag<(ops node:$src),
753 (bitconvert (v2i64 (X86vzmovl
754 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
755 def vzmovl_v4i32 : PatFrag<(ops node:$src),
756 (bitconvert (v4i32 (X86vzmovl
757 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
759 def vzload_v2i64 : PatFrag<(ops node:$src),
760 (bitconvert (v2i64 (X86vzload node:$src)))>;
763 def fp32imm0 : PatLeaf<(f32 fpimm), [{
764 return N->isExactlyValue(+0.0);
767 def I8Imm : SDNodeXForm<imm, [{
768 // Transformation function: get the low 8 bits.
769 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
772 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
773 def FROUND_CURRENT : ImmLeaf<i32, [{
774 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
777 // BYTE_imm - Transform bit immediates into byte immediates.
778 def BYTE_imm : SDNodeXForm<imm, [{
779 // Transformation function: imm >> 3
780 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
783 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
784 // to VEXTRACTF128/VEXTRACTI128 imm.
785 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
786 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
789 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
790 // VINSERTF128/VINSERTI128 imm.
791 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
792 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
795 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
796 // to VEXTRACTF64x4 imm.
797 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
798 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
801 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
803 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
804 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
807 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
808 (extract_subvector node:$bigvec,
810 return X86::isVEXTRACT128Index(N);
811 }], EXTRACT_get_vextract128_imm>;
813 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
815 (insert_subvector node:$bigvec, node:$smallvec,
817 return X86::isVINSERT128Index(N);
818 }], INSERT_get_vinsert128_imm>;
821 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
822 (extract_subvector node:$bigvec,
824 return X86::isVEXTRACT256Index(N);
825 }], EXTRACT_get_vextract256_imm>;
827 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
829 (insert_subvector node:$bigvec, node:$smallvec,
831 return X86::isVINSERT256Index(N);
832 }], INSERT_get_vinsert256_imm>;
834 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
835 (masked_load node:$src1, node:$src2, node:$src3), [{
836 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
837 return Load->getAlignment() >= 16;
841 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
842 (masked_load node:$src1, node:$src2, node:$src3), [{
843 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
844 return Load->getAlignment() >= 32;
848 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
849 (masked_load node:$src1, node:$src2, node:$src3), [{
850 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
851 return Load->getAlignment() >= 64;
855 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
856 (masked_load node:$src1, node:$src2, node:$src3), [{
857 return isa<MaskedLoadSDNode>(N);
860 // masked store fragments.
861 // X86mstore can't be implemented in core DAG files because some targets
862 // doesn't support vector type ( llvm-tblgen will fail)
863 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
864 (masked_store node:$src1, node:$src2, node:$src3), [{
865 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
868 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
869 (X86mstore node:$src1, node:$src2, node:$src3), [{
870 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
871 return Store->getAlignment() >= 16;
875 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
876 (X86mstore node:$src1, node:$src2, node:$src3), [{
877 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
878 return Store->getAlignment() >= 32;
882 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
883 (X86mstore node:$src1, node:$src2, node:$src3), [{
884 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
885 return Store->getAlignment() >= 64;
889 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
890 (X86mstore node:$src1, node:$src2, node:$src3), [{
891 return isa<MaskedStoreSDNode>(N);
894 // masked truncstore fragments
895 // X86mtruncstore can't be implemented in core DAG files because some targets
896 // doesn't support vector type ( llvm-tblgen will fail)
897 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
898 (masked_store node:$src1, node:$src2, node:$src3), [{
899 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
901 def masked_truncstorevi8 :
902 PatFrag<(ops node:$src1, node:$src2, node:$src3),
903 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
904 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
906 def masked_truncstorevi16 :
907 PatFrag<(ops node:$src1, node:$src2, node:$src3),
908 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
909 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
911 def masked_truncstorevi32 :
912 PatFrag<(ops node:$src1, node:$src2, node:$src3),
913 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
914 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;