1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
39 SDTCisFP<0>, SDTCisInt<2> ]>;
40 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
41 SDTCisFP<1>, SDTCisVT<3, i8>,
44 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
45 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
46 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
47 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
49 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
50 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
52 // Commutative and Associative FMIN and FMAX.
53 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
58 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
65 [SDNPCommutative, SDNPAssociative]>;
66 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
67 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
68 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
69 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
70 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
71 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
72 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
73 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
74 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
75 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
76 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
77 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86andnp : SDNode<"X86ISD::ANDNP",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86psign : SDNode<"X86ISD::PSIGN",
85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def X86pextrb : SDNode<"X86ISD::PEXTRB",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89 def X86pextrw : SDNode<"X86ISD::PEXTRW",
90 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
91 def X86pinsrb : SDNode<"X86ISD::PINSRB",
92 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
93 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
94 def X86pinsrw : SDNode<"X86ISD::PINSRW",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86insertps : SDNode<"X86ISD::INSERTPS",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
100 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
101 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
103 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
104 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
106 def X86vzext : SDNode<"X86ISD::VZEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
111 def X86vsext : SDNode<"X86ISD::VSEXT",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<1, 0>]>>;
116 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<0, 1>]>>;
120 def X86trunc : SDNode<"X86ISD::TRUNC",
121 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
124 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
125 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
126 SDTCisInt<0>, SDTCisInt<1>,
127 SDTCisVec<2>, SDTCisInt<2>,
128 SDTCisOpSmallerThanOp<0, 2>]>>;
129 def X86vfpext : SDNode<"X86ISD::VFPEXT",
130 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
131 SDTCisFP<0>, SDTCisFP<1>,
132 SDTCisOpSmallerThanOp<1, 0>]>>;
133 def X86vfpround: SDNode<"X86ISD::VFPROUND",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<0, 1>]>>;
138 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
139 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
140 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
141 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
142 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
144 def X86IntCmpMask : SDTypeProfile<1, 2,
145 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
146 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
147 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
150 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
151 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
152 def X86CmpMaskCCScalar :
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
155 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
156 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
157 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
159 def X86vshl : SDNode<"X86ISD::VSHL",
160 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
162 def X86vsrl : SDNode<"X86ISD::VSRL",
163 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
165 def X86vsra : SDNode<"X86ISD::VSRA",
166 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
169 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
170 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
171 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
173 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
175 SDTCisSameAs<2, 1>]>;
176 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
177 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
178 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
179 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
180 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
182 SDTCisSameAs<2, 1>]>>;
183 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
185 SDTCisSameAs<2, 1>]>>;
186 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
188 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
189 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
190 SDTCisSameAs<1,2>]>>;
191 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
192 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
193 SDTCisSameAs<1,2>]>>;
195 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
196 // translated into one of the target nodes below during lowering.
197 // Note: this is a work in progress...
198 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
199 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
201 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
202 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
204 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
206 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
207 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
208 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
209 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
211 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
212 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
214 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
215 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
217 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
218 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
220 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
221 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
222 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
223 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
224 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
225 SDTCisVec<0>, SDTCisInt<2>]>;
226 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
227 SDTCisVec<0>, SDTCisInt<3>]>;
228 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
229 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
231 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
232 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
234 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
235 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
236 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
238 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
240 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
241 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
242 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
244 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
245 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
247 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
248 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
249 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
251 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
252 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
254 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
255 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
256 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
258 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
259 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
261 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
262 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
263 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
264 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
265 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
266 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
268 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
270 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
271 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
272 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
273 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
274 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
275 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
277 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
279 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
281 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
282 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
283 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
284 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
286 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
287 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
288 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
289 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
290 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
291 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
293 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
294 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
295 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
296 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
297 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
298 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
300 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
301 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
302 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
304 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
305 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
306 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
308 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
309 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
311 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
312 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
313 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
316 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
317 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
319 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
320 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
321 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
322 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
324 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
326 //===----------------------------------------------------------------------===//
327 // SSE Complex Patterns
328 //===----------------------------------------------------------------------===//
330 // These are 'extloads' from a scalar to the low element of a vector, zeroing
331 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
333 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
334 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
336 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
337 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
340 def ssmem : Operand<v4f32> {
341 let PrintMethod = "printf32mem";
342 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
343 let ParserMatchClass = X86Mem32AsmOperand;
344 let OperandType = "OPERAND_MEMORY";
346 def sdmem : Operand<v2f64> {
347 let PrintMethod = "printf64mem";
348 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
349 let ParserMatchClass = X86Mem64AsmOperand;
350 let OperandType = "OPERAND_MEMORY";
353 //===----------------------------------------------------------------------===//
354 // SSE pattern fragments
355 //===----------------------------------------------------------------------===//
357 // 128-bit load pattern fragments
358 // NOTE: all 128-bit integer vector loads are promoted to v2i64
359 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
360 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
361 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
363 // 256-bit load pattern fragments
364 // NOTE: all 256-bit integer vector loads are promoted to v4i64
365 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
366 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
367 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
369 // 512-bit load pattern fragments
370 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
371 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
372 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
373 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
374 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
375 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
377 // 128-/256-/512-bit extload pattern fragments
378 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
379 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
380 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
382 // These are needed to match a scalar load that is used in a vector-only
383 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
384 // The memory operand is required to be a 128-bit load, so it must be converted
385 // from a vector to a scalar.
386 def loadf32_128 : PatFrag<(ops node:$ptr),
387 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
388 def loadf64_128 : PatFrag<(ops node:$ptr),
389 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
391 // Like 'store', but always requires 128-bit vector alignment.
392 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
393 (store node:$val, node:$ptr), [{
394 return cast<StoreSDNode>(N)->getAlignment() >= 16;
397 // Like 'store', but always requires 256-bit vector alignment.
398 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
399 (store node:$val, node:$ptr), [{
400 return cast<StoreSDNode>(N)->getAlignment() >= 32;
403 // Like 'store', but always requires 512-bit vector alignment.
404 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 64;
409 // Like 'load', but always requires 128-bit vector alignment.
410 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
411 return cast<LoadSDNode>(N)->getAlignment() >= 16;
414 // Like 'X86vzload', but always requires 128-bit vector alignment.
415 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
416 return cast<MemSDNode>(N)->getAlignment() >= 16;
419 // Like 'load', but always requires 256-bit vector alignment.
420 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
421 return cast<LoadSDNode>(N)->getAlignment() >= 32;
424 // Like 'load', but always requires 512-bit vector alignment.
425 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 return cast<LoadSDNode>(N)->getAlignment() >= 64;
429 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
430 (f32 (alignedload node:$ptr))>;
431 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
432 (f64 (alignedload node:$ptr))>;
434 // 128-bit aligned load pattern fragments
435 // NOTE: all 128-bit integer vector loads are promoted to v2i64
436 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
437 (v4f32 (alignedload node:$ptr))>;
438 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
439 (v2f64 (alignedload node:$ptr))>;
440 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
441 (v2i64 (alignedload node:$ptr))>;
443 // 256-bit aligned load pattern fragments
444 // NOTE: all 256-bit integer vector loads are promoted to v4i64
445 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
446 (v8f32 (alignedload256 node:$ptr))>;
447 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
448 (v4f64 (alignedload256 node:$ptr))>;
449 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
450 (v4i64 (alignedload256 node:$ptr))>;
452 // 512-bit aligned load pattern fragments
453 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
454 (v16f32 (alignedload512 node:$ptr))>;
455 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
456 (v16i32 (alignedload512 node:$ptr))>;
457 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
458 (v8f64 (alignedload512 node:$ptr))>;
459 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
460 (v8i64 (alignedload512 node:$ptr))>;
462 // Like 'load', but uses special alignment checks suitable for use in
463 // memory operands in most SSE instructions, which are required to
464 // be naturally aligned on some targets but not on others. If the subtarget
465 // allows unaligned accesses, match any load, though this may require
466 // setting a feature bit in the processor (on startup, for example).
467 // Opteron 10h and later implement such a feature.
468 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
469 return Subtarget->hasSSEUnalignedMem()
470 || cast<LoadSDNode>(N)->getAlignment() >= 16;
473 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
474 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
476 // 128-bit memop pattern fragments
477 // NOTE: all 128-bit integer vector loads are promoted to v2i64
478 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
479 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
480 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
482 // These are needed to match a scalar memop that is used in a vector-only
483 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
484 // The memory operand is required to be a 128-bit load, so it must be converted
485 // from a vector to a scalar.
486 def memopfsf32_128 : PatFrag<(ops node:$ptr),
487 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
488 def memopfsf64_128 : PatFrag<(ops node:$ptr),
489 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
492 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
494 // FIXME: 8 byte alignment for mmx reads is not required
495 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
496 return cast<LoadSDNode>(N)->getAlignment() >= 8;
499 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
502 // Like 'store', but requires the non-temporal bit to be set
503 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
504 (st node:$val, node:$ptr), [{
505 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
506 return ST->isNonTemporal();
510 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
511 (st node:$val, node:$ptr), [{
512 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
513 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
514 ST->getAddressingMode() == ISD::UNINDEXED &&
515 ST->getAlignment() >= 16;
519 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
520 (st node:$val, node:$ptr), [{
521 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
522 return ST->isNonTemporal() &&
523 ST->getAlignment() < 16;
527 // 128-bit bitconvert pattern fragments
528 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
529 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
530 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
531 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
532 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
533 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
535 // 256-bit bitconvert pattern fragments
536 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
537 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
538 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
539 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
540 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
542 // 512-bit bitconvert pattern fragments
543 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
544 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
545 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
546 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
548 def vzmovl_v2i64 : PatFrag<(ops node:$src),
549 (bitconvert (v2i64 (X86vzmovl
550 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
551 def vzmovl_v4i32 : PatFrag<(ops node:$src),
552 (bitconvert (v4i32 (X86vzmovl
553 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
555 def vzload_v2i64 : PatFrag<(ops node:$src),
556 (bitconvert (v2i64 (X86vzload node:$src)))>;
559 def fp32imm0 : PatLeaf<(f32 fpimm), [{
560 return N->isExactlyValue(+0.0);
563 def I8Imm : SDNodeXForm<imm, [{
564 // Transformation function: get the low 8 bits.
565 return getI8Imm((uint8_t)N->getZExtValue());
568 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
569 def FROUND_CURRENT : ImmLeaf<i32, [{
570 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
573 // BYTE_imm - Transform bit immediates into byte immediates.
574 def BYTE_imm : SDNodeXForm<imm, [{
575 // Transformation function: imm >> 3
576 return getI32Imm(N->getZExtValue() >> 3);
579 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
580 // to VEXTRACTF128/VEXTRACTI128 imm.
581 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
582 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
585 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
586 // VINSERTF128/VINSERTI128 imm.
587 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
588 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
591 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
592 // to VEXTRACTF64x4 imm.
593 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
594 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
597 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
599 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
600 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
603 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
604 (extract_subvector node:$bigvec,
606 return X86::isVEXTRACT128Index(N);
607 }], EXTRACT_get_vextract128_imm>;
609 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
611 (insert_subvector node:$bigvec, node:$smallvec,
613 return X86::isVINSERT128Index(N);
614 }], INSERT_get_vinsert128_imm>;
617 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
618 (extract_subvector node:$bigvec,
620 return X86::isVEXTRACT256Index(N);
621 }], EXTRACT_get_vextract256_imm>;
623 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
625 (insert_subvector node:$bigvec, node:$smallvec,
627 return X86::isVINSERT256Index(N);
628 }], INSERT_get_vinsert256_imm>;