1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
43 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
44 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
45 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
47 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
48 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
50 // Commutative and Associative FMIN and FMAX.
51 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
56 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
57 [SDNPCommutative, SDNPAssociative]>;
58 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
65 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
66 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
67 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
68 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
69 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
70 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
71 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
72 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
73 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
74 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
75 def X86pshufb : SDNode<"X86ISD::PSHUFB",
76 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 def X86psadbw : SDNode<"X86ISD::PSADBW",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86andnp : SDNode<"X86ISD::ANDNP",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86psign : SDNode<"X86ISD::PSIGN",
85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def X86pextrb : SDNode<"X86ISD::PEXTRB",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89 def X86pextrw : SDNode<"X86ISD::PEXTRW",
90 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
91 def X86pinsrb : SDNode<"X86ISD::PINSRB",
92 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
93 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
94 def X86pinsrw : SDNode<"X86ISD::PINSRW",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86insertps : SDNode<"X86ISD::INSERTPS",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
100 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
101 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
103 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
104 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
106 def X86vzext : SDNode<"X86ISD::VZEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
111 def X86vsext : SDNode<"X86ISD::VSEXT",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<1, 0>]>>;
116 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<0, 1>]>>;
120 def X86trunc : SDNode<"X86ISD::TRUNC",
121 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
124 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
125 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
126 SDTCisInt<0>, SDTCisInt<1>,
127 SDTCisVec<2>, SDTCisInt<2>,
128 SDTCisOpSmallerThanOp<0, 2>]>>;
129 def X86vfpext : SDNode<"X86ISD::VFPEXT",
130 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
131 SDTCisFP<0>, SDTCisFP<1>,
132 SDTCisOpSmallerThanOp<1, 0>]>>;
133 def X86vfpround: SDNode<"X86ISD::VFPROUND",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<0, 1>]>>;
138 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
139 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
140 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
141 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
142 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
144 def X86IntCmpMask : SDTypeProfile<1, 2,
145 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
146 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
147 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
150 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
151 SDTCisVec<1>, SDTCisSameAs<2, 1>,
152 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
153 def X86CmpMaskCCRound :
154 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
155 SDTCisVec<1>, SDTCisSameAs<2, 1>,
156 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
158 def X86CmpMaskCCScalar :
159 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
161 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
162 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
163 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
164 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
166 def X86vshl : SDNode<"X86ISD::VSHL",
167 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
169 def X86vsrl : SDNode<"X86ISD::VSRL",
170 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
172 def X86vsra : SDNode<"X86ISD::VSRA",
173 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
176 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
177 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
178 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
180 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
182 SDTCisSameAs<2, 1>]>;
183 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
184 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
185 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
186 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
187 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
188 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
189 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
190 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
191 SDTCisVec<1>, SDTCisSameAs<2, 1>,
192 SDTCVecEltisVT<0, i1>,
193 SDTCisSameNumEltsAs<0, 1>]>>;
194 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
195 SDTCisVec<1>, SDTCisSameAs<2, 1>,
196 SDTCVecEltisVT<0, i1>,
197 SDTCisSameNumEltsAs<0, 1>]>>;
198 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
200 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
201 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
202 SDTCisSameAs<1,2>]>>;
203 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
204 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
205 SDTCisSameAs<1,2>]>>;
207 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
208 // translated into one of the target nodes below during lowering.
209 // Note: this is a work in progress...
210 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
211 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
213 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
216 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
218 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
219 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
220 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
222 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
223 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
225 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
226 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
228 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
229 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
231 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
232 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
234 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
235 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
237 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
238 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
239 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
240 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
241 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
242 SDTCisVec<0>, SDTCisInt<2>]>;
243 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
244 SDTCisVec<0>, SDTCisInt<3>]>;
245 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
246 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
248 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
249 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
251 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
252 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
253 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
255 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
256 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
258 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
259 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
260 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
262 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
263 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
265 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
266 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
267 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
269 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
270 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
272 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
273 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
274 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
276 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
277 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
279 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
280 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
281 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
282 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
283 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
284 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
286 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
288 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
289 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
291 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
292 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
293 SDTCisSubVecOfVec<1, 0>]>, []>;
294 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
295 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
296 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
297 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
298 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
300 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
302 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
304 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
305 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
306 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
307 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
308 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
309 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
310 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
311 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
313 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
314 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
315 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
316 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
317 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
318 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
320 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
321 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
322 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
323 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
324 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
325 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
327 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
328 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
329 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
331 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
332 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
333 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
335 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
336 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
338 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
339 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
340 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
343 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
344 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
346 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
347 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
348 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
349 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
351 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
353 //===----------------------------------------------------------------------===//
354 // SSE Complex Patterns
355 //===----------------------------------------------------------------------===//
357 // These are 'extloads' from a scalar to the low element of a vector, zeroing
358 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
360 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
361 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
363 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
364 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
367 def ssmem : Operand<v4f32> {
368 let PrintMethod = "printf32mem";
369 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
370 let ParserMatchClass = X86Mem32AsmOperand;
371 let OperandType = "OPERAND_MEMORY";
373 def sdmem : Operand<v2f64> {
374 let PrintMethod = "printf64mem";
375 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
376 let ParserMatchClass = X86Mem64AsmOperand;
377 let OperandType = "OPERAND_MEMORY";
380 //===----------------------------------------------------------------------===//
381 // SSE pattern fragments
382 //===----------------------------------------------------------------------===//
384 // 128-bit load pattern fragments
385 // NOTE: all 128-bit integer vector loads are promoted to v2i64
386 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
387 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
388 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
390 // 256-bit load pattern fragments
391 // NOTE: all 256-bit integer vector loads are promoted to v4i64
392 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
393 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
394 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
396 // 512-bit load pattern fragments
397 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
398 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
399 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
400 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
401 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
402 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
404 // 128-/256-/512-bit extload pattern fragments
405 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
406 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
407 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
409 // These are needed to match a scalar load that is used in a vector-only
410 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
411 // The memory operand is required to be a 128-bit load, so it must be converted
412 // from a vector to a scalar.
413 def loadf32_128 : PatFrag<(ops node:$ptr),
414 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
415 def loadf64_128 : PatFrag<(ops node:$ptr),
416 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
418 // Like 'store', but always requires 128-bit vector alignment.
419 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
420 (store node:$val, node:$ptr), [{
421 return cast<StoreSDNode>(N)->getAlignment() >= 16;
424 // Like 'store', but always requires 256-bit vector alignment.
425 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() >= 32;
430 // Like 'store', but always requires 512-bit vector alignment.
431 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
432 (store node:$val, node:$ptr), [{
433 return cast<StoreSDNode>(N)->getAlignment() >= 64;
436 // Like 'load', but always requires 128-bit vector alignment.
437 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
438 return cast<LoadSDNode>(N)->getAlignment() >= 16;
441 // Like 'X86vzload', but always requires 128-bit vector alignment.
442 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
443 return cast<MemSDNode>(N)->getAlignment() >= 16;
446 // Like 'load', but always requires 256-bit vector alignment.
447 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
448 return cast<LoadSDNode>(N)->getAlignment() >= 32;
451 // Like 'load', but always requires 512-bit vector alignment.
452 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
453 return cast<LoadSDNode>(N)->getAlignment() >= 64;
456 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
457 (f32 (alignedload node:$ptr))>;
458 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
459 (f64 (alignedload node:$ptr))>;
461 // 128-bit aligned load pattern fragments
462 // NOTE: all 128-bit integer vector loads are promoted to v2i64
463 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
464 (v4f32 (alignedload node:$ptr))>;
465 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
466 (v2f64 (alignedload node:$ptr))>;
467 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
468 (v2i64 (alignedload node:$ptr))>;
470 // 256-bit aligned load pattern fragments
471 // NOTE: all 256-bit integer vector loads are promoted to v4i64
472 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
473 (v8f32 (alignedload256 node:$ptr))>;
474 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
475 (v4f64 (alignedload256 node:$ptr))>;
476 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
477 (v4i64 (alignedload256 node:$ptr))>;
479 // 512-bit aligned load pattern fragments
480 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
481 (v16f32 (alignedload512 node:$ptr))>;
482 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
483 (v16i32 (alignedload512 node:$ptr))>;
484 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
485 (v8f64 (alignedload512 node:$ptr))>;
486 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
487 (v8i64 (alignedload512 node:$ptr))>;
489 // Like 'load', but uses special alignment checks suitable for use in
490 // memory operands in most SSE instructions, which are required to
491 // be naturally aligned on some targets but not on others. If the subtarget
492 // allows unaligned accesses, match any load, though this may require
493 // setting a feature bit in the processor (on startup, for example).
494 // Opteron 10h and later implement such a feature.
495 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
496 return Subtarget->hasSSEUnalignedMem()
497 || cast<LoadSDNode>(N)->getAlignment() >= 16;
500 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
501 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
503 // 128-bit memop pattern fragments
504 // NOTE: all 128-bit integer vector loads are promoted to v2i64
505 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
506 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
507 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
509 // These are needed to match a scalar memop that is used in a vector-only
510 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
511 // The memory operand is required to be a 128-bit load, so it must be converted
512 // from a vector to a scalar.
513 def memopfsf32_128 : PatFrag<(ops node:$ptr),
514 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
515 def memopfsf64_128 : PatFrag<(ops node:$ptr),
516 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
519 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
521 // FIXME: 8 byte alignment for mmx reads is not required
522 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
523 return cast<LoadSDNode>(N)->getAlignment() >= 8;
526 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
529 // Like 'store', but requires the non-temporal bit to be set
530 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
531 (st node:$val, node:$ptr), [{
532 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
533 return ST->isNonTemporal();
537 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
538 (st node:$val, node:$ptr), [{
539 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
540 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
541 ST->getAddressingMode() == ISD::UNINDEXED &&
542 ST->getAlignment() >= 16;
546 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
547 (st node:$val, node:$ptr), [{
548 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
549 return ST->isNonTemporal() &&
550 ST->getAlignment() < 16;
554 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
555 (masked_gather node:$src1, node:$src2, node:$src3) , [{
556 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
557 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
558 Mgt->getBasePtr().getValueType() == MVT::v8i32);
562 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
563 (masked_gather node:$src1, node:$src2, node:$src3) , [{
564 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
565 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
566 Mgt->getBasePtr().getValueType() == MVT::v8i64);
569 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
570 (masked_gather node:$src1, node:$src2, node:$src3) , [{
571 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
572 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
573 Mgt->getBasePtr().getValueType() == MVT::v16i32);
577 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
578 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
579 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
580 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
581 Sc->getBasePtr().getValueType() == MVT::v8i32);
585 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
586 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
587 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
588 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
589 Sc->getBasePtr().getValueType() == MVT::v8i64);
592 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
593 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
594 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
595 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
596 Sc->getBasePtr().getValueType() == MVT::v16i32);
600 // 128-bit bitconvert pattern fragments
601 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
602 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
603 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
604 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
605 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
606 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
608 // 256-bit bitconvert pattern fragments
609 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
610 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
611 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
612 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
613 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
615 // 512-bit bitconvert pattern fragments
616 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
617 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
618 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
619 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
621 def vzmovl_v2i64 : PatFrag<(ops node:$src),
622 (bitconvert (v2i64 (X86vzmovl
623 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
624 def vzmovl_v4i32 : PatFrag<(ops node:$src),
625 (bitconvert (v4i32 (X86vzmovl
626 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
628 def vzload_v2i64 : PatFrag<(ops node:$src),
629 (bitconvert (v2i64 (X86vzload node:$src)))>;
632 def fp32imm0 : PatLeaf<(f32 fpimm), [{
633 return N->isExactlyValue(+0.0);
636 def I8Imm : SDNodeXForm<imm, [{
637 // Transformation function: get the low 8 bits.
638 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
641 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
642 def FROUND_CURRENT : ImmLeaf<i32, [{
643 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
646 // BYTE_imm - Transform bit immediates into byte immediates.
647 def BYTE_imm : SDNodeXForm<imm, [{
648 // Transformation function: imm >> 3
649 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
652 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
653 // to VEXTRACTF128/VEXTRACTI128 imm.
654 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
655 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
658 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
659 // VINSERTF128/VINSERTI128 imm.
660 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
661 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
664 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
665 // to VEXTRACTF64x4 imm.
666 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
667 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
670 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
672 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
673 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
676 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
677 (extract_subvector node:$bigvec,
679 return X86::isVEXTRACT128Index(N);
680 }], EXTRACT_get_vextract128_imm>;
682 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
684 (insert_subvector node:$bigvec, node:$smallvec,
686 return X86::isVINSERT128Index(N);
687 }], INSERT_get_vinsert128_imm>;
690 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
691 (extract_subvector node:$bigvec,
693 return X86::isVEXTRACT256Index(N);
694 }], EXTRACT_get_vextract256_imm>;
696 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
698 (insert_subvector node:$bigvec, node:$smallvec,
700 return X86::isVINSERT256Index(N);
701 }], INSERT_get_vinsert256_imm>;
703 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
704 (masked_load node:$src1, node:$src2, node:$src3), [{
705 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
706 return Load->getAlignment() >= 16;
710 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
711 (masked_load node:$src1, node:$src2, node:$src3), [{
712 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
713 return Load->getAlignment() >= 32;
717 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
718 (masked_load node:$src1, node:$src2, node:$src3), [{
719 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
720 return Load->getAlignment() >= 64;
724 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
725 (masked_load node:$src1, node:$src2, node:$src3), [{
726 return isa<MaskedLoadSDNode>(N);
729 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
730 (masked_store node:$src1, node:$src2, node:$src3), [{
731 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
732 return Store->getAlignment() >= 16;
736 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
737 (masked_store node:$src1, node:$src2, node:$src3), [{
738 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
739 return Store->getAlignment() >= 32;
743 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
744 (masked_store node:$src1, node:$src2, node:$src3), [{
745 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
746 return Store->getAlignment() >= 64;
750 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
751 (masked_store node:$src1, node:$src2, node:$src3), [{
752 return isa<MaskedStoreSDNode>(N);