1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
33 // Commutative and Associative FMIN and FMAX.
34 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
39 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
46 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
47 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
48 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
49 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
50 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
51 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
52 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
53 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
54 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
55 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
56 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
57 def X86pshufb : SDNode<"X86ISD::PSHUFB",
58 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
60 def X86andnp : SDNode<"X86ISD::ANDNP",
61 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 def X86psign : SDNode<"X86ISD::PSIGN",
64 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 def X86pextrb : SDNode<"X86ISD::PEXTRB",
67 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
68 def X86pextrw : SDNode<"X86ISD::PEXTRW",
69 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
70 def X86pinsrb : SDNode<"X86ISD::PINSRB",
71 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
72 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
73 def X86pinsrw : SDNode<"X86ISD::PINSRW",
74 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
75 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
76 def X86insrtps : SDNode<"X86ISD::INSERTPS",
77 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
78 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
79 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
80 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
82 def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL",
83 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisOpSmallerThanOp<1, 0> ]>>;
86 def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
88 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
90 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
93 def X86vfpext : SDNode<"X86ISD::VFPEXT",
94 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
95 SDTCisFP<0>, SDTCisFP<1>]>>;
97 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
98 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
99 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
100 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
101 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
103 def X86vshl : SDNode<"X86ISD::VSHL",
104 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
106 def X86vsrl : SDNode<"X86ISD::VSRL",
107 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
109 def X86vsra : SDNode<"X86ISD::VSRA",
110 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
113 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
114 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
115 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
117 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
119 SDTCisSameAs<2, 1>]>;
120 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
121 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
123 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
124 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
125 SDTCisSameAs<1,2>]>>;
127 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
128 // translated into one of the target nodes below during lowering.
129 // Note: this is a work in progress...
130 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
131 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
134 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
135 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
136 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
137 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
139 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
140 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
141 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
143 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
144 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
146 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
148 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
149 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
150 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
152 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
154 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
155 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
156 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
158 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
159 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
161 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
162 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
163 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
165 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
166 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
168 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
169 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
171 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
172 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
173 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
175 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
177 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
179 def X86Blendpw : SDNode<"X86ISD::BLENDPW", SDTBlend>;
180 def X86Blendps : SDNode<"X86ISD::BLENDPS", SDTBlend>;
181 def X86Blendpd : SDNode<"X86ISD::BLENDPD", SDTBlend>;
182 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
183 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
184 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
185 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
186 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
187 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
189 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
190 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
192 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
193 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
194 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
197 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
198 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
200 //===----------------------------------------------------------------------===//
201 // SSE Complex Patterns
202 //===----------------------------------------------------------------------===//
204 // These are 'extloads' from a scalar to the low element of a vector, zeroing
205 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
207 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
208 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
210 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
211 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
214 def ssmem : Operand<v4f32> {
215 let PrintMethod = "printf32mem";
216 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
217 let ParserMatchClass = X86MemAsmOperand;
218 let OperandType = "OPERAND_MEMORY";
220 def sdmem : Operand<v2f64> {
221 let PrintMethod = "printf64mem";
222 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
223 let ParserMatchClass = X86MemAsmOperand;
224 let OperandType = "OPERAND_MEMORY";
227 //===----------------------------------------------------------------------===//
228 // SSE pattern fragments
229 //===----------------------------------------------------------------------===//
231 // 128-bit load pattern fragments
232 // NOTE: all 128-bit integer vector loads are promoted to v2i64
233 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
234 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
235 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
237 // 256-bit load pattern fragments
238 // NOTE: all 256-bit integer vector loads are promoted to v4i64
239 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
240 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
241 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
243 // Like 'store', but always requires 128-bit vector alignment.
244 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
245 (store node:$val, node:$ptr), [{
246 return cast<StoreSDNode>(N)->getAlignment() >= 16;
249 // Like 'store', but always requires 256-bit vector alignment.
250 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
251 (store node:$val, node:$ptr), [{
252 return cast<StoreSDNode>(N)->getAlignment() >= 32;
255 // Like 'load', but always requires 128-bit vector alignment.
256 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
257 return cast<LoadSDNode>(N)->getAlignment() >= 16;
260 // Like 'X86vzload', but always requires 128-bit vector alignment.
261 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
262 return cast<MemSDNode>(N)->getAlignment() >= 16;
265 // Like 'load', but always requires 256-bit vector alignment.
266 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
267 return cast<LoadSDNode>(N)->getAlignment() >= 32;
270 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
271 (f32 (alignedload node:$ptr))>;
272 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
273 (f64 (alignedload node:$ptr))>;
275 // 128-bit aligned load pattern fragments
276 // NOTE: all 128-bit integer vector loads are promoted to v2i64
277 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
278 (v4f32 (alignedload node:$ptr))>;
279 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
280 (v2f64 (alignedload node:$ptr))>;
281 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
282 (v2i64 (alignedload node:$ptr))>;
284 // 256-bit aligned load pattern fragments
285 // NOTE: all 256-bit integer vector loads are promoted to v4i64
286 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
287 (v8f32 (alignedload256 node:$ptr))>;
288 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
289 (v4f64 (alignedload256 node:$ptr))>;
290 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
291 (v4i64 (alignedload256 node:$ptr))>;
293 // Like 'load', but uses special alignment checks suitable for use in
294 // memory operands in most SSE instructions, which are required to
295 // be naturally aligned on some targets but not on others. If the subtarget
296 // allows unaligned accesses, match any load, though this may require
297 // setting a feature bit in the processor (on startup, for example).
298 // Opteron 10h and later implement such a feature.
299 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
300 return Subtarget->hasVectorUAMem()
301 || cast<LoadSDNode>(N)->getAlignment() >= 16;
304 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
305 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
307 // 128-bit memop pattern fragments
308 // NOTE: all 128-bit integer vector loads are promoted to v2i64
309 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
310 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
311 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
313 // 256-bit memop pattern fragments
314 // NOTE: all 256-bit integer vector loads are promoted to v4i64
315 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
316 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
317 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
319 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
321 // FIXME: 8 byte alignment for mmx reads is not required
322 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
323 return cast<LoadSDNode>(N)->getAlignment() >= 8;
326 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
329 // Like 'store', but requires the non-temporal bit to be set
330 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
331 (st node:$val, node:$ptr), [{
332 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
333 return ST->isNonTemporal();
337 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
338 (st node:$val, node:$ptr), [{
339 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
340 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
341 ST->getAddressingMode() == ISD::UNINDEXED &&
342 ST->getAlignment() >= 16;
346 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
347 (st node:$val, node:$ptr), [{
348 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
349 return ST->isNonTemporal() &&
350 ST->getAlignment() < 16;
354 // 128-bit bitconvert pattern fragments
355 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
356 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
357 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
358 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
359 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
360 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
362 // 256-bit bitconvert pattern fragments
363 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
364 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
365 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
366 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
368 def vzmovl_v2i64 : PatFrag<(ops node:$src),
369 (bitconvert (v2i64 (X86vzmovl
370 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
371 def vzmovl_v4i32 : PatFrag<(ops node:$src),
372 (bitconvert (v4i32 (X86vzmovl
373 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
375 def vzload_v2i64 : PatFrag<(ops node:$src),
376 (bitconvert (v2i64 (X86vzload node:$src)))>;
379 def fp32imm0 : PatLeaf<(f32 fpimm), [{
380 return N->isExactlyValue(+0.0);
383 // BYTE_imm - Transform bit immediates into byte immediates.
384 def BYTE_imm : SDNodeXForm<imm, [{
385 // Transformation function: imm >> 3
386 return getI32Imm(N->getZExtValue() >> 3);
389 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
390 // to VEXTRACTF128 imm.
391 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
392 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
395 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
397 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
398 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
401 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
402 (extract_subvector node:$bigvec,
404 return X86::isVEXTRACTF128Index(N);
405 }], EXTRACT_get_vextractf128_imm>;
407 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
409 (insert_subvector node:$bigvec, node:$smallvec,
411 return X86::isVINSERTF128Index(N);
412 }], INSERT_get_vinsertf128_imm>;