1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
43 #define DEBUG_TYPE "x86-instr-info"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
49 NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
52 PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
57 ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
62 // Select which memory operand is being unfolded.
63 // (stored in bits 0 - 3)
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
94 struct X86MemoryFoldTableEntry {
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
105 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
107 : X86::ADJCALLSTACKUP32),
109 Subtarget(STI), RI(STI.getTargetTriple()) {
111 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
112 { X86::ADC32ri, X86::ADC32mi, 0 },
113 { X86::ADC32ri8, X86::ADC32mi8, 0 },
114 { X86::ADC32rr, X86::ADC32mr, 0 },
115 { X86::ADC64ri32, X86::ADC64mi32, 0 },
116 { X86::ADC64ri8, X86::ADC64mi8, 0 },
117 { X86::ADC64rr, X86::ADC64mr, 0 },
118 { X86::ADD16ri, X86::ADD16mi, 0 },
119 { X86::ADD16ri8, X86::ADD16mi8, 0 },
120 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
121 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
122 { X86::ADD16rr, X86::ADD16mr, 0 },
123 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
124 { X86::ADD32ri, X86::ADD32mi, 0 },
125 { X86::ADD32ri8, X86::ADD32mi8, 0 },
126 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
127 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
128 { X86::ADD32rr, X86::ADD32mr, 0 },
129 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
130 { X86::ADD64ri32, X86::ADD64mi32, 0 },
131 { X86::ADD64ri8, X86::ADD64mi8, 0 },
132 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
133 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
134 { X86::ADD64rr, X86::ADD64mr, 0 },
135 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
136 { X86::ADD8ri, X86::ADD8mi, 0 },
137 { X86::ADD8rr, X86::ADD8mr, 0 },
138 { X86::AND16ri, X86::AND16mi, 0 },
139 { X86::AND16ri8, X86::AND16mi8, 0 },
140 { X86::AND16rr, X86::AND16mr, 0 },
141 { X86::AND32ri, X86::AND32mi, 0 },
142 { X86::AND32ri8, X86::AND32mi8, 0 },
143 { X86::AND32rr, X86::AND32mr, 0 },
144 { X86::AND64ri32, X86::AND64mi32, 0 },
145 { X86::AND64ri8, X86::AND64mi8, 0 },
146 { X86::AND64rr, X86::AND64mr, 0 },
147 { X86::AND8ri, X86::AND8mi, 0 },
148 { X86::AND8rr, X86::AND8mr, 0 },
149 { X86::DEC16r, X86::DEC16m, 0 },
150 { X86::DEC32r, X86::DEC32m, 0 },
151 { X86::DEC64r, X86::DEC64m, 0 },
152 { X86::DEC8r, X86::DEC8m, 0 },
153 { X86::INC16r, X86::INC16m, 0 },
154 { X86::INC32r, X86::INC32m, 0 },
155 { X86::INC64r, X86::INC64m, 0 },
156 { X86::INC8r, X86::INC8m, 0 },
157 { X86::NEG16r, X86::NEG16m, 0 },
158 { X86::NEG32r, X86::NEG32m, 0 },
159 { X86::NEG64r, X86::NEG64m, 0 },
160 { X86::NEG8r, X86::NEG8m, 0 },
161 { X86::NOT16r, X86::NOT16m, 0 },
162 { X86::NOT32r, X86::NOT32m, 0 },
163 { X86::NOT64r, X86::NOT64m, 0 },
164 { X86::NOT8r, X86::NOT8m, 0 },
165 { X86::OR16ri, X86::OR16mi, 0 },
166 { X86::OR16ri8, X86::OR16mi8, 0 },
167 { X86::OR16rr, X86::OR16mr, 0 },
168 { X86::OR32ri, X86::OR32mi, 0 },
169 { X86::OR32ri8, X86::OR32mi8, 0 },
170 { X86::OR32rr, X86::OR32mr, 0 },
171 { X86::OR64ri32, X86::OR64mi32, 0 },
172 { X86::OR64ri8, X86::OR64mi8, 0 },
173 { X86::OR64rr, X86::OR64mr, 0 },
174 { X86::OR8ri, X86::OR8mi, 0 },
175 { X86::OR8rr, X86::OR8mr, 0 },
176 { X86::ROL16r1, X86::ROL16m1, 0 },
177 { X86::ROL16rCL, X86::ROL16mCL, 0 },
178 { X86::ROL16ri, X86::ROL16mi, 0 },
179 { X86::ROL32r1, X86::ROL32m1, 0 },
180 { X86::ROL32rCL, X86::ROL32mCL, 0 },
181 { X86::ROL32ri, X86::ROL32mi, 0 },
182 { X86::ROL64r1, X86::ROL64m1, 0 },
183 { X86::ROL64rCL, X86::ROL64mCL, 0 },
184 { X86::ROL64ri, X86::ROL64mi, 0 },
185 { X86::ROL8r1, X86::ROL8m1, 0 },
186 { X86::ROL8rCL, X86::ROL8mCL, 0 },
187 { X86::ROL8ri, X86::ROL8mi, 0 },
188 { X86::ROR16r1, X86::ROR16m1, 0 },
189 { X86::ROR16rCL, X86::ROR16mCL, 0 },
190 { X86::ROR16ri, X86::ROR16mi, 0 },
191 { X86::ROR32r1, X86::ROR32m1, 0 },
192 { X86::ROR32rCL, X86::ROR32mCL, 0 },
193 { X86::ROR32ri, X86::ROR32mi, 0 },
194 { X86::ROR64r1, X86::ROR64m1, 0 },
195 { X86::ROR64rCL, X86::ROR64mCL, 0 },
196 { X86::ROR64ri, X86::ROR64mi, 0 },
197 { X86::ROR8r1, X86::ROR8m1, 0 },
198 { X86::ROR8rCL, X86::ROR8mCL, 0 },
199 { X86::ROR8ri, X86::ROR8mi, 0 },
200 { X86::SAR16r1, X86::SAR16m1, 0 },
201 { X86::SAR16rCL, X86::SAR16mCL, 0 },
202 { X86::SAR16ri, X86::SAR16mi, 0 },
203 { X86::SAR32r1, X86::SAR32m1, 0 },
204 { X86::SAR32rCL, X86::SAR32mCL, 0 },
205 { X86::SAR32ri, X86::SAR32mi, 0 },
206 { X86::SAR64r1, X86::SAR64m1, 0 },
207 { X86::SAR64rCL, X86::SAR64mCL, 0 },
208 { X86::SAR64ri, X86::SAR64mi, 0 },
209 { X86::SAR8r1, X86::SAR8m1, 0 },
210 { X86::SAR8rCL, X86::SAR8mCL, 0 },
211 { X86::SAR8ri, X86::SAR8mi, 0 },
212 { X86::SBB32ri, X86::SBB32mi, 0 },
213 { X86::SBB32ri8, X86::SBB32mi8, 0 },
214 { X86::SBB32rr, X86::SBB32mr, 0 },
215 { X86::SBB64ri32, X86::SBB64mi32, 0 },
216 { X86::SBB64ri8, X86::SBB64mi8, 0 },
217 { X86::SBB64rr, X86::SBB64mr, 0 },
218 { X86::SHL16rCL, X86::SHL16mCL, 0 },
219 { X86::SHL16ri, X86::SHL16mi, 0 },
220 { X86::SHL32rCL, X86::SHL32mCL, 0 },
221 { X86::SHL32ri, X86::SHL32mi, 0 },
222 { X86::SHL64rCL, X86::SHL64mCL, 0 },
223 { X86::SHL64ri, X86::SHL64mi, 0 },
224 { X86::SHL8rCL, X86::SHL8mCL, 0 },
225 { X86::SHL8ri, X86::SHL8mi, 0 },
226 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
227 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
228 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
229 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
230 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
231 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
232 { X86::SHR16r1, X86::SHR16m1, 0 },
233 { X86::SHR16rCL, X86::SHR16mCL, 0 },
234 { X86::SHR16ri, X86::SHR16mi, 0 },
235 { X86::SHR32r1, X86::SHR32m1, 0 },
236 { X86::SHR32rCL, X86::SHR32mCL, 0 },
237 { X86::SHR32ri, X86::SHR32mi, 0 },
238 { X86::SHR64r1, X86::SHR64m1, 0 },
239 { X86::SHR64rCL, X86::SHR64mCL, 0 },
240 { X86::SHR64ri, X86::SHR64mi, 0 },
241 { X86::SHR8r1, X86::SHR8m1, 0 },
242 { X86::SHR8rCL, X86::SHR8mCL, 0 },
243 { X86::SHR8ri, X86::SHR8mi, 0 },
244 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
245 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
246 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
247 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
248 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
249 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
250 { X86::SUB16ri, X86::SUB16mi, 0 },
251 { X86::SUB16ri8, X86::SUB16mi8, 0 },
252 { X86::SUB16rr, X86::SUB16mr, 0 },
253 { X86::SUB32ri, X86::SUB32mi, 0 },
254 { X86::SUB32ri8, X86::SUB32mi8, 0 },
255 { X86::SUB32rr, X86::SUB32mr, 0 },
256 { X86::SUB64ri32, X86::SUB64mi32, 0 },
257 { X86::SUB64ri8, X86::SUB64mi8, 0 },
258 { X86::SUB64rr, X86::SUB64mr, 0 },
259 { X86::SUB8ri, X86::SUB8mi, 0 },
260 { X86::SUB8rr, X86::SUB8mr, 0 },
261 { X86::XOR16ri, X86::XOR16mi, 0 },
262 { X86::XOR16ri8, X86::XOR16mi8, 0 },
263 { X86::XOR16rr, X86::XOR16mr, 0 },
264 { X86::XOR32ri, X86::XOR32mi, 0 },
265 { X86::XOR32ri8, X86::XOR32mi8, 0 },
266 { X86::XOR32rr, X86::XOR32mr, 0 },
267 { X86::XOR64ri32, X86::XOR64mi32, 0 },
268 { X86::XOR64ri8, X86::XOR64mi8, 0 },
269 { X86::XOR64rr, X86::XOR64mr, 0 },
270 { X86::XOR8ri, X86::XOR8mi, 0 },
271 { X86::XOR8rr, X86::XOR8mr, 0 }
274 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
275 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
276 Entry.RegOp, Entry.MemOp,
277 // Index 0, folded load and store, no alignment requirement.
278 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
281 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
282 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
283 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
284 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
285 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
286 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
287 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
288 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
289 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
290 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
291 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
292 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
293 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
294 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
295 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
296 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
297 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
298 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
299 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
300 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
301 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
302 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
335 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
336 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
337 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
338 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
339 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
340 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
341 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
342 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
343 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
344 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
345 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
346 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
347 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
348 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
349 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
350 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
351 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
352 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
353 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
354 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
355 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
356 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
357 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
358 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
359 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
360 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
361 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
362 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
364 // AVX 128-bit versions of foldable instructions
365 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
366 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
369 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
370 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
371 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
372 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
373 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
374 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
375 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
376 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
377 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
379 // AVX 256-bit foldable instructions
380 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
382 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
383 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
384 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
385 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
387 // AVX-512 foldable instructions
388 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
389 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
390 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
392 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
393 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
394 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
395 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
396 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
397 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
398 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
400 // AVX-512 foldable instructions (256-bit versions)
401 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
404 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
405 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
406 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
407 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
409 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
410 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
412 // AVX-512 foldable instructions (128-bit versions)
413 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
414 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
416 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
417 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
418 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
424 // F16C foldable instructions
425 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
426 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
429 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
430 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
431 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
434 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
435 { X86::BSF16rr, X86::BSF16rm, 0 },
436 { X86::BSF32rr, X86::BSF32rm, 0 },
437 { X86::BSF64rr, X86::BSF64rm, 0 },
438 { X86::BSR16rr, X86::BSR16rm, 0 },
439 { X86::BSR32rr, X86::BSR32rm, 0 },
440 { X86::BSR64rr, X86::BSR64rm, 0 },
441 { X86::CMP16rr, X86::CMP16rm, 0 },
442 { X86::CMP32rr, X86::CMP32rm, 0 },
443 { X86::CMP64rr, X86::CMP64rm, 0 },
444 { X86::CMP8rr, X86::CMP8rm, 0 },
445 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
446 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
447 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
448 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
449 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
450 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
451 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
452 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
453 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
454 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
455 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
456 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
457 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
458 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
459 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
460 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
461 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
462 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
463 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
464 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
465 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
466 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
467 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
468 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
469 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
470 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
471 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
472 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
473 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
474 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
475 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
476 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
477 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
478 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
479 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
480 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
481 { X86::MOV16rr, X86::MOV16rm, 0 },
482 { X86::MOV32rr, X86::MOV32rm, 0 },
483 { X86::MOV64rr, X86::MOV64rm, 0 },
484 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
485 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
486 { X86::MOV8rr, X86::MOV8rm, 0 },
487 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
488 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
489 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
490 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
491 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
492 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
493 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
494 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
495 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
496 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
497 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
498 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
499 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
500 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
501 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
502 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
503 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
504 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
505 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
506 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
507 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
508 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
509 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
510 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
511 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
512 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
513 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
514 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
515 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
516 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
517 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
518 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
519 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
520 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
521 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
522 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
523 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
524 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
525 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
526 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
527 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
528 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
529 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
530 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
531 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
532 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
533 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
534 { X86::RCPSSr, X86::RCPSSm, 0 },
535 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
536 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
537 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
538 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
539 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
540 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
541 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
542 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
543 { X86::SQRTSDr, X86::SQRTSDm, 0 },
544 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
545 { X86::SQRTSSr, X86::SQRTSSm, 0 },
546 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
547 { X86::TEST16rr, X86::TEST16rm, 0 },
548 { X86::TEST32rr, X86::TEST32rm, 0 },
549 { X86::TEST64rr, X86::TEST64rm, 0 },
550 { X86::TEST8rr, X86::TEST8rm, 0 },
551 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
552 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
553 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
555 // MMX version of foldable instructions
556 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
557 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
558 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
559 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
560 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
561 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
562 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
563 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
564 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
565 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
567 // 3DNow! version of foldable instructions
568 { X86::PF2IDrr, X86::PF2IDrm, 0 },
569 { X86::PF2IWrr, X86::PF2IWrm, 0 },
570 { X86::PFRCPrr, X86::PFRCPrm, 0 },
571 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
572 { X86::PI2FDrr, X86::PI2FDrm, 0 },
573 { X86::PI2FWrr, X86::PI2FWrm, 0 },
574 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
576 // AVX 128-bit versions of foldable instructions
577 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
578 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
579 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
580 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
581 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
582 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
583 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
584 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
585 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
586 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
588 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
589 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
590 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
591 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
592 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
593 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
594 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
595 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
596 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
597 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
598 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
599 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
600 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
601 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
602 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
603 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
604 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
605 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
606 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
607 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
608 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
609 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
610 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
611 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
612 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
613 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
614 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
615 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
616 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
617 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
618 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
619 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
620 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
621 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
622 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
623 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
624 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
625 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
626 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
627 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
628 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
629 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
630 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
631 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
632 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
633 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
634 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
635 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
636 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
637 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
638 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
639 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
640 { X86::VPTESTrr, X86::VPTESTrm, 0 },
641 { X86::VRCPPSr, X86::VRCPPSm, 0 },
642 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
643 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
644 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
645 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
646 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
647 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
648 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
649 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
650 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
652 // AVX 256-bit foldable instructions
653 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
654 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
655 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
656 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
657 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
658 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
659 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
660 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
661 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
662 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
663 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
664 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
665 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
666 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
667 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
668 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
669 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
670 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
671 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
672 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
673 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
674 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
675 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
676 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
677 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
678 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
679 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
681 // AVX2 foldable instructions
683 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
684 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
685 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
686 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
687 // so they don't need an equivalent limitation.
688 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
689 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
690 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
691 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
692 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
693 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
694 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
695 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
696 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
697 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
698 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
699 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
700 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
701 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
702 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
703 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
704 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
705 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
706 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
707 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
708 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
709 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
710 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
711 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
712 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
713 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
714 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
715 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
716 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
717 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
718 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
720 // XOP foldable instructions
721 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
722 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
723 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
724 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
725 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
726 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
727 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
728 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
729 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
730 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
731 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
732 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
733 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
734 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
735 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
736 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
737 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
738 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
739 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
740 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
741 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
742 { X86::VPROTBri, X86::VPROTBmi, 0 },
743 { X86::VPROTBrr, X86::VPROTBmr, 0 },
744 { X86::VPROTDri, X86::VPROTDmi, 0 },
745 { X86::VPROTDrr, X86::VPROTDmr, 0 },
746 { X86::VPROTQri, X86::VPROTQmi, 0 },
747 { X86::VPROTQrr, X86::VPROTQmr, 0 },
748 { X86::VPROTWri, X86::VPROTWmi, 0 },
749 { X86::VPROTWrr, X86::VPROTWmr, 0 },
750 { X86::VPSHABrr, X86::VPSHABmr, 0 },
751 { X86::VPSHADrr, X86::VPSHADmr, 0 },
752 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
753 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
754 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
755 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
756 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
757 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
759 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
760 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
761 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
762 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
763 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
764 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
765 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
766 { X86::BLCI32rr, X86::BLCI32rm, 0 },
767 { X86::BLCI64rr, X86::BLCI64rm, 0 },
768 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
769 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
770 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
771 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
772 { X86::BLCS32rr, X86::BLCS32rm, 0 },
773 { X86::BLCS64rr, X86::BLCS64rm, 0 },
774 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
775 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
776 { X86::BLSI32rr, X86::BLSI32rm, 0 },
777 { X86::BLSI64rr, X86::BLSI64rm, 0 },
778 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
779 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
780 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
781 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
782 { X86::BLSR32rr, X86::BLSR32rm, 0 },
783 { X86::BLSR64rr, X86::BLSR64rm, 0 },
784 { X86::BZHI32rr, X86::BZHI32rm, 0 },
785 { X86::BZHI64rr, X86::BZHI64rm, 0 },
786 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
787 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
788 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
789 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
790 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
791 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
792 { X86::RORX32ri, X86::RORX32mi, 0 },
793 { X86::RORX64ri, X86::RORX64mi, 0 },
794 { X86::SARX32rr, X86::SARX32rm, 0 },
795 { X86::SARX64rr, X86::SARX64rm, 0 },
796 { X86::SHRX32rr, X86::SHRX32rm, 0 },
797 { X86::SHRX64rr, X86::SHRX64rm, 0 },
798 { X86::SHLX32rr, X86::SHLX32rm, 0 },
799 { X86::SHLX64rr, X86::SHLX64rm, 0 },
800 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
801 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
802 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
803 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
804 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
805 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
806 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
808 // AVX-512 foldable instructions
809 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
810 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
811 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
812 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
813 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
814 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
815 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
816 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
817 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
818 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
819 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
820 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
821 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
822 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
823 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
824 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
826 // AVX-512 foldable instructions (256-bit versions)
827 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
828 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
829 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
830 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
831 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
832 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
833 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
834 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
835 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
836 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
837 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
838 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
840 // AVX-512 foldable instructions (256-bit versions)
841 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
842 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
843 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
844 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
845 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
846 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
847 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
848 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
849 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
850 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
851 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
853 // F16C foldable instructions
854 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
855 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
857 // AES foldable instructions
858 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
859 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
860 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
861 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
864 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
865 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
866 Entry.RegOp, Entry.MemOp,
867 // Index 1, folded load
868 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
871 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
872 { X86::ADC32rr, X86::ADC32rm, 0 },
873 { X86::ADC64rr, X86::ADC64rm, 0 },
874 { X86::ADD16rr, X86::ADD16rm, 0 },
875 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
876 { X86::ADD32rr, X86::ADD32rm, 0 },
877 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
878 { X86::ADD64rr, X86::ADD64rm, 0 },
879 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
880 { X86::ADD8rr, X86::ADD8rm, 0 },
881 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
882 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
883 { X86::ADDSDrr, X86::ADDSDrm, 0 },
884 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
885 { X86::ADDSSrr, X86::ADDSSrm, 0 },
886 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
887 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
888 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
889 { X86::AND16rr, X86::AND16rm, 0 },
890 { X86::AND32rr, X86::AND32rm, 0 },
891 { X86::AND64rr, X86::AND64rm, 0 },
892 { X86::AND8rr, X86::AND8rm, 0 },
893 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
894 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
895 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
896 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
897 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
898 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
899 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
900 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
901 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
902 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
903 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
904 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
905 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
906 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
907 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
908 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
909 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
910 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
911 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
912 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
913 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
914 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
915 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
916 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
917 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
918 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
919 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
920 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
921 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
922 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
923 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
924 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
925 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
926 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
927 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
928 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
929 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
930 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
931 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
932 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
933 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
934 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
935 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
936 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
937 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
938 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
939 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
940 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
941 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
942 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
943 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
944 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
945 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
946 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
947 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
948 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
949 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
950 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
951 { X86::CMPSDrr, X86::CMPSDrm, 0 },
952 { X86::CMPSSrr, X86::CMPSSrm, 0 },
953 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
954 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
955 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
956 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
957 { X86::DIVSDrr, X86::DIVSDrm, 0 },
958 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
959 { X86::DIVSSrr, X86::DIVSSrm, 0 },
960 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
961 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
962 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
964 // Do not fold Fs* scalar logical op loads because there are no scalar
965 // load variants for these instructions. When folded, the load is required
966 // to be 128-bits, so the load size would not match.
968 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
969 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
970 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
971 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
972 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
973 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
974 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
975 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
976 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
977 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
978 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
979 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
980 { X86::IMUL16rr, X86::IMUL16rm, 0 },
981 { X86::IMUL32rr, X86::IMUL32rm, 0 },
982 { X86::IMUL64rr, X86::IMUL64rm, 0 },
983 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
984 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
985 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
986 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
987 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
988 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
989 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
990 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
991 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
992 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
993 { X86::MAXSDrr, X86::MAXSDrm, 0 },
994 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
995 { X86::MAXSSrr, X86::MAXSSrm, 0 },
996 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
997 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
998 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
999 { X86::MINSDrr, X86::MINSDrm, 0 },
1000 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
1001 { X86::MINSSrr, X86::MINSSrm, 0 },
1002 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
1003 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
1004 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1005 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1006 { X86::MULSDrr, X86::MULSDrm, 0 },
1007 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
1008 { X86::MULSSrr, X86::MULSSrm, 0 },
1009 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
1010 { X86::OR16rr, X86::OR16rm, 0 },
1011 { X86::OR32rr, X86::OR32rm, 0 },
1012 { X86::OR64rr, X86::OR64rm, 0 },
1013 { X86::OR8rr, X86::OR8rm, 0 },
1014 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1015 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1016 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1017 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
1018 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
1019 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1020 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1021 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1022 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1023 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1024 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
1025 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1026 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
1027 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
1028 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
1029 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1030 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1031 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1032 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
1033 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
1034 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
1035 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
1036 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1037 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
1038 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
1039 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1040 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1041 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
1042 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
1043 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
1044 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1045 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
1046 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
1047 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
1048 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
1049 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
1050 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1051 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1052 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1053 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1054 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
1055 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1056 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1057 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1058 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1059 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
1060 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1061 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1062 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1063 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1064 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1065 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1066 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1067 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
1068 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
1069 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
1070 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1071 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1072 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1073 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1074 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1075 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1076 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
1077 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1078 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1079 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1080 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
1081 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1082 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1083 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1084 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1085 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1086 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1087 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1088 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1089 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1090 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
1091 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
1092 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1093 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
1094 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1095 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
1096 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1097 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1098 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1099 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1100 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1101 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1102 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1103 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1104 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1105 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1106 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1107 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
1108 { X86::SBB32rr, X86::SBB32rm, 0 },
1109 { X86::SBB64rr, X86::SBB64rm, 0 },
1110 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1111 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1112 { X86::SUB16rr, X86::SUB16rm, 0 },
1113 { X86::SUB32rr, X86::SUB32rm, 0 },
1114 { X86::SUB64rr, X86::SUB64rm, 0 },
1115 { X86::SUB8rr, X86::SUB8rm, 0 },
1116 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1117 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1118 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1119 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
1120 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1121 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
1122 // FIXME: TEST*rr -> swapped operand of TEST*mr.
1123 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1124 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1125 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1126 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1127 { X86::XOR16rr, X86::XOR16rm, 0 },
1128 { X86::XOR32rr, X86::XOR32rm, 0 },
1129 { X86::XOR64rr, X86::XOR64rm, 0 },
1130 { X86::XOR8rr, X86::XOR8rm, 0 },
1131 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
1132 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
1134 // MMX version of foldable instructions
1135 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1136 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1137 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1138 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1139 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1140 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1141 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1142 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1143 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1144 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1145 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1146 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1147 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1148 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1149 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1150 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1151 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1152 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1153 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1154 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1155 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1156 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1157 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1158 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1159 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1160 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1161 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1162 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1163 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1164 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1165 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1166 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1167 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1168 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1169 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1170 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1171 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1172 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1173 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1174 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1175 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1176 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1177 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1178 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1179 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1180 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1181 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1182 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1183 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1184 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1185 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1186 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1187 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1188 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1189 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1190 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1191 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1192 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1193 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1194 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1195 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1196 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1197 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1198 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1199 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1200 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1201 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1202 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1203 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1204 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1206 // 3DNow! version of foldable instructions
1207 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1208 { X86::PFACCrr, X86::PFACCrm, 0 },
1209 { X86::PFADDrr, X86::PFADDrm, 0 },
1210 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1211 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1212 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1213 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1214 { X86::PFMINrr, X86::PFMINrm, 0 },
1215 { X86::PFMULrr, X86::PFMULrm, 0 },
1216 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1217 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1218 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1219 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1220 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1221 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1222 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1223 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1225 // AVX 128-bit versions of foldable instructions
1226 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1227 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1228 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1229 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1230 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1231 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1232 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1233 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1234 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1235 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1236 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1237 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
1238 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1239 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
1240 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1241 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
1242 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1243 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
1244 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1245 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
1246 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1247 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1248 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1249 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
1250 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1251 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
1252 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1253 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1254 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1255 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1256 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1257 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1258 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1259 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1260 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1261 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1262 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1263 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1264 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1265 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1266 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1267 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1268 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1269 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
1270 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1271 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1272 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1273 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1274 // Do not fold VFs* loads because there are no scalar load variants for
1275 // these instructions. When folded, the load is required to be 128-bits, so
1276 // the load size would not match.
1277 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1278 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1279 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1280 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1281 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1282 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1283 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1284 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
1285 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1286 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1287 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1288 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1289 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1290 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
1291 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1292 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1293 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1294 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
1295 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1296 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
1297 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1298 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1299 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1300 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
1301 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1302 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
1303 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1304 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1305 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1306 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1307 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
1308 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1309 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
1310 { X86::VORPDrr, X86::VORPDrm, 0 },
1311 { X86::VORPSrr, X86::VORPSrm, 0 },
1312 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1313 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1314 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1315 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1316 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1317 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1318 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1319 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1320 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1321 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1322 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1323 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1324 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1325 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1326 { X86::VPANDrr, X86::VPANDrm, 0 },
1327 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1328 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1329 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1330 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1331 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1332 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1333 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1334 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1335 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1336 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1337 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1338 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1339 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1340 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1341 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1342 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1343 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1344 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1345 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1346 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1347 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1348 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1349 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1350 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1351 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1352 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1353 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1354 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1355 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1356 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1357 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1358 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1359 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1360 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1361 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1362 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1363 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1364 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1365 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1366 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1367 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1368 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1369 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1370 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1371 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1372 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1373 { X86::VPORrr, X86::VPORrm, 0 },
1374 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1375 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1376 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1377 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1378 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1379 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1380 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1381 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1382 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1383 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1384 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1385 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1386 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1387 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1388 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1389 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1390 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1391 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1392 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1393 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1394 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1395 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1396 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1397 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1398 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1399 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1400 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1401 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1402 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1403 { X86::VPXORrr, X86::VPXORrm, 0 },
1404 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1405 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
1406 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1407 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1408 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1409 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1410 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1411 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
1412 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1413 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
1414 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1415 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1416 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1417 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1418 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1419 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1421 // AVX 256-bit foldable instructions
1422 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1423 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1424 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1425 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1426 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1427 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1428 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1429 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1430 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1431 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1432 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1433 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1434 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1435 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1436 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1437 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1438 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1439 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1440 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1441 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1442 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1443 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1444 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1445 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1446 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1447 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1448 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1449 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1450 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1451 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1452 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1453 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1454 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1455 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1456 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1457 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1458 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1459 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1460 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1461 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1462 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1463 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1464 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1466 // AVX2 foldable instructions
1467 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1468 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1469 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1470 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1471 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1472 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1473 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1474 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1475 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1476 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1477 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1478 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1479 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1480 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1481 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1482 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1483 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1484 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1485 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1486 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1487 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1488 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1489 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1490 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1491 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1492 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1493 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1494 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1495 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1496 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1497 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1498 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1499 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1500 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1501 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1502 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1503 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1504 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1505 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1506 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1507 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1508 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1509 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1510 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1511 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1512 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1513 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1514 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1515 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1516 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1517 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1518 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1519 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1520 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1521 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1522 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1523 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1524 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1525 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1526 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1527 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1528 { X86::VPORYrr, X86::VPORYrm, 0 },
1529 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1530 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1531 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1532 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1533 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1534 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1535 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1536 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1537 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1538 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1539 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1540 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1541 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1542 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1543 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1544 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1545 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1546 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1547 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1548 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1549 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1550 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1551 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1552 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1553 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1554 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1555 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1556 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1557 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1558 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1559 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1560 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1561 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1562 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1563 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1564 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1565 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1566 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1567 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1568 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1570 // FMA4 foldable patterns
1571 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1572 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1573 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1574 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1575 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1576 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1577 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1578 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1579 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1580 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1581 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1582 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1583 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1584 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1585 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1586 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1587 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1588 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1589 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1590 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1591 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1592 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1593 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1594 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1595 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1596 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1597 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1598 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1599 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1600 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1601 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1602 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
1604 // XOP foldable instructions
1605 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1606 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1607 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1608 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1609 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1610 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1611 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1612 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1613 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1614 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1615 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1616 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1617 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1618 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1619 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1620 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1621 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1622 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1623 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1624 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1625 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1626 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1627 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1628 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1629 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1630 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1631 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1632 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1633 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1634 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1635 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1636 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1637 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1638 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1639 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1640 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1641 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1642 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1643 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1645 // BMI/BMI2 foldable instructions
1646 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1647 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1648 { X86::MULX32rr, X86::MULX32rm, 0 },
1649 { X86::MULX64rr, X86::MULX64rm, 0 },
1650 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1651 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1652 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1653 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1655 // AVX-512 foldable instructions
1656 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1657 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1658 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1659 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1660 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1661 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1662 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1663 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1664 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1665 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1666 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1667 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1668 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1669 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1670 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1671 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1672 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1673 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1674 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1675 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1676 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1677 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1678 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1679 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1680 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1681 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1682 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1683 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1684 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1685 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1686 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1687 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1688 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1689 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1690 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1691 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1692 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1693 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1694 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1696 // AVX-512{F,VL} foldable instructions
1697 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1698 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1699 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
1701 // AVX-512{F,VL} foldable instructions
1702 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1703 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1704 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1705 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1707 // AES foldable instructions
1708 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1709 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1710 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1711 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1712 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1713 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1714 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1715 { X86::VAESENCrr, X86::VAESENCrm, 0 },
1717 // SHA foldable instructions
1718 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1719 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1720 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1721 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1722 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1723 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1724 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
1727 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1728 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1729 Entry.RegOp, Entry.MemOp,
1730 // Index 2, folded load
1731 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1734 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1735 // FMA foldable instructions
1736 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1737 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1738 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1739 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1740 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1741 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1743 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1744 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1745 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1746 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1747 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1748 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1749 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1750 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1751 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1752 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1753 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1754 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1756 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1757 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1758 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1759 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1760 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1761 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1763 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1764 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1765 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1766 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1767 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1768 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1769 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1770 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1771 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1772 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1773 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1774 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1776 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1777 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1778 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1779 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1780 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1781 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1783 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1784 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1785 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1786 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1787 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1788 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1789 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1790 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1791 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1792 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1793 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1794 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1796 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1797 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1798 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1799 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1800 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1801 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1803 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1804 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1805 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1806 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1807 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1808 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1809 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1810 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1811 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1812 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1813 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1814 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1816 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1817 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1818 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1819 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1820 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1821 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1822 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1823 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1824 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1825 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1826 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1827 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1829 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1830 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1831 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1832 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1833 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1834 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1835 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1836 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1837 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1838 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1839 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1840 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1842 // FMA4 foldable patterns
1843 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1844 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1845 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1846 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1847 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1848 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1849 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1850 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1851 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1852 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1853 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1854 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1855 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1856 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1857 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1858 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1859 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1860 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1861 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1862 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1863 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1864 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1865 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1866 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1867 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1868 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1869 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1870 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1871 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1872 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1873 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1874 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
1876 // XOP foldable instructions
1877 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1878 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1879 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1880 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1881 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1882 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1883 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1885 // AVX-512 VPERMI instructions with 3 source operands.
1886 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1887 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1888 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1889 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1890 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1891 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1892 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1893 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1894 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1895 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1896 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1897 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
1898 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1899 // AVX-512 arithmetic instructions
1900 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1901 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1902 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1903 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1904 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1905 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1906 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1907 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1908 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1909 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1910 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1911 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1912 // AVX-512{F,VL} arithmetic instructions 256-bit
1913 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1914 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1915 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1916 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1917 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1918 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1919 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1920 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1921 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1922 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1923 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1924 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1925 // AVX-512{F,VL} arithmetic instructions 128-bit
1926 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1927 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1928 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1929 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1930 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1931 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1932 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1933 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1934 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1935 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1936 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1937 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
1940 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1941 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1942 Entry.RegOp, Entry.MemOp,
1943 // Index 3, folded load
1944 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1947 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1948 // AVX-512 foldable instructions
1949 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1950 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1951 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1952 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1953 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1954 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1955 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1956 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1957 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1958 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1959 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1960 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1961 // AVX-512{F,VL} foldable instructions 256-bit
1962 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1963 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1964 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1965 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1966 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1967 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1968 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1969 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1970 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1971 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1972 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1973 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1974 // AVX-512{F,VL} foldable instructions 128-bit
1975 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1976 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1977 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1978 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1979 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1980 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1981 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1982 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1983 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1984 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1985 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1986 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1989 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
1990 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1991 Entry.RegOp, Entry.MemOp,
1992 // Index 4, folded load
1993 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1998 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1999 MemOp2RegOpTableType &M2RTable,
2000 unsigned RegOp, unsigned MemOp, unsigned Flags) {
2001 if ((Flags & TB_NO_FORWARD) == 0) {
2002 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2003 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2005 if ((Flags & TB_NO_REVERSE) == 0) {
2006 assert(!M2RTable.count(MemOp) &&
2007 "Duplicated entries in unfolding maps?");
2008 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2013 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2014 unsigned &SrcReg, unsigned &DstReg,
2015 unsigned &SubIdx) const {
2016 switch (MI.getOpcode()) {
2018 case X86::MOVSX16rr8:
2019 case X86::MOVZX16rr8:
2020 case X86::MOVSX32rr8:
2021 case X86::MOVZX32rr8:
2022 case X86::MOVSX64rr8:
2023 if (!Subtarget.is64Bit())
2024 // It's not always legal to reference the low 8-bit of the larger
2025 // register in 32-bit mode.
2027 case X86::MOVSX32rr16:
2028 case X86::MOVZX32rr16:
2029 case X86::MOVSX64rr16:
2030 case X86::MOVSX64rr32: {
2031 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2034 SrcReg = MI.getOperand(1).getReg();
2035 DstReg = MI.getOperand(0).getReg();
2036 switch (MI.getOpcode()) {
2037 default: llvm_unreachable("Unreachable!");
2038 case X86::MOVSX16rr8:
2039 case X86::MOVZX16rr8:
2040 case X86::MOVSX32rr8:
2041 case X86::MOVZX32rr8:
2042 case X86::MOVSX64rr8:
2043 SubIdx = X86::sub_8bit;
2045 case X86::MOVSX32rr16:
2046 case X86::MOVZX32rr16:
2047 case X86::MOVSX64rr16:
2048 SubIdx = X86::sub_16bit;
2050 case X86::MOVSX64rr32:
2051 SubIdx = X86::sub_32bit;
2060 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2061 const MachineFunction *MF = MI->getParent()->getParent();
2062 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2064 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2065 MI->getOpcode() == getCallFrameDestroyOpcode()) {
2066 unsigned StackAlign = TFI->getStackAlignment();
2067 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2070 SPAdj -= MI->getOperand(1).getImm();
2072 if (MI->getOpcode() == getCallFrameSetupOpcode())
2078 // To know whether a call adjusts the stack, we need information
2079 // that is bound to the following ADJCALLSTACKUP pseudo.
2080 // Look for the next ADJCALLSTACKUP that follows the call.
2082 const MachineBasicBlock* MBB = MI->getParent();
2083 auto I = ++MachineBasicBlock::const_iterator(MI);
2084 for (auto E = MBB->end(); I != E; ++I) {
2085 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2090 // If we could not find a frame destroy opcode, then it has already
2091 // been simplified, so we don't care.
2092 if (I->getOpcode() != getCallFrameDestroyOpcode())
2095 return -(I->getOperand(1).getImm());
2098 // Currently handle only PUSHes we can reasonably expect to see
2099 // in call sequences
2100 switch (MI->getOpcode()) {
2105 case X86::PUSH32rmm:
2106 case X86::PUSH32rmr:
2112 /// Return true and the FrameIndex if the specified
2113 /// operand and follow operands form a reference to the stack frame.
2114 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2115 int &FrameIndex) const {
2116 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2117 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2118 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2119 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2120 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2121 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2122 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2123 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2129 static bool isFrameLoadOpcode(int Opcode) {
2145 case X86::VMOVAPSrm:
2146 case X86::VMOVAPDrm:
2147 case X86::VMOVDQArm:
2148 case X86::VMOVUPSYrm:
2149 case X86::VMOVAPSYrm:
2150 case X86::VMOVUPDYrm:
2151 case X86::VMOVAPDYrm:
2152 case X86::VMOVDQUYrm:
2153 case X86::VMOVDQAYrm:
2154 case X86::MMX_MOVD64rm:
2155 case X86::MMX_MOVQ64rm:
2156 case X86::VMOVAPSZrm:
2157 case X86::VMOVUPSZrm:
2162 static bool isFrameStoreOpcode(int Opcode) {
2169 case X86::ST_FpP64m:
2177 case X86::VMOVAPSmr:
2178 case X86::VMOVAPDmr:
2179 case X86::VMOVDQAmr:
2180 case X86::VMOVUPSYmr:
2181 case X86::VMOVAPSYmr:
2182 case X86::VMOVUPDYmr:
2183 case X86::VMOVAPDYmr:
2184 case X86::VMOVDQUYmr:
2185 case X86::VMOVDQAYmr:
2186 case X86::VMOVUPSZmr:
2187 case X86::VMOVAPSZmr:
2188 case X86::MMX_MOVD64mr:
2189 case X86::MMX_MOVQ64mr:
2190 case X86::MMX_MOVNTQmr:
2196 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2197 int &FrameIndex) const {
2198 if (isFrameLoadOpcode(MI->getOpcode()))
2199 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2200 return MI->getOperand(0).getReg();
2204 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2205 int &FrameIndex) const {
2206 if (isFrameLoadOpcode(MI->getOpcode())) {
2208 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2210 // Check for post-frame index elimination operations
2211 const MachineMemOperand *Dummy;
2212 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2217 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2218 int &FrameIndex) const {
2219 if (isFrameStoreOpcode(MI->getOpcode()))
2220 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2221 isFrameOperand(MI, 0, FrameIndex))
2222 return MI->getOperand(X86::AddrNumOperands).getReg();
2226 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2227 int &FrameIndex) const {
2228 if (isFrameStoreOpcode(MI->getOpcode())) {
2230 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2232 // Check for post-frame index elimination operations
2233 const MachineMemOperand *Dummy;
2234 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2239 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2240 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2241 // Don't waste compile time scanning use-def chains of physregs.
2242 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2244 bool isPICBase = false;
2245 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2246 E = MRI.def_instr_end(); I != E; ++I) {
2247 MachineInstr *DefMI = &*I;
2248 if (DefMI->getOpcode() != X86::MOVPC32r)
2250 assert(!isPICBase && "More than one PIC base?");
2257 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2258 AliasAnalysis *AA) const {
2259 switch (MI->getOpcode()) {
2275 case X86::VMOVAPSrm:
2276 case X86::VMOVUPSrm:
2277 case X86::VMOVAPDrm:
2278 case X86::VMOVDQArm:
2279 case X86::VMOVDQUrm:
2280 case X86::VMOVAPSYrm:
2281 case X86::VMOVUPSYrm:
2282 case X86::VMOVAPDYrm:
2283 case X86::VMOVDQAYrm:
2284 case X86::VMOVDQUYrm:
2285 case X86::MMX_MOVD64rm:
2286 case X86::MMX_MOVQ64rm:
2287 case X86::FsVMOVAPSrm:
2288 case X86::FsVMOVAPDrm:
2289 case X86::FsMOVAPSrm:
2290 case X86::FsMOVAPDrm:
2292 case X86::VMOVAPDZ128rm:
2293 case X86::VMOVAPDZ256rm:
2294 case X86::VMOVAPDZrm:
2295 case X86::VMOVAPSZ128rm:
2296 case X86::VMOVAPSZ256rm:
2297 case X86::VMOVAPSZrm:
2298 case X86::VMOVDQA32Z128rm:
2299 case X86::VMOVDQA32Z256rm:
2300 case X86::VMOVDQA32Zrm:
2301 case X86::VMOVDQA64Z128rm:
2302 case X86::VMOVDQA64Z256rm:
2303 case X86::VMOVDQA64Zrm:
2304 case X86::VMOVDQU16Z128rm:
2305 case X86::VMOVDQU16Z256rm:
2306 case X86::VMOVDQU16Zrm:
2307 case X86::VMOVDQU32Z128rm:
2308 case X86::VMOVDQU32Z256rm:
2309 case X86::VMOVDQU32Zrm:
2310 case X86::VMOVDQU64Z128rm:
2311 case X86::VMOVDQU64Z256rm:
2312 case X86::VMOVDQU64Zrm:
2313 case X86::VMOVDQU8Z128rm:
2314 case X86::VMOVDQU8Z256rm:
2315 case X86::VMOVDQU8Zrm:
2316 case X86::VMOVUPSZ128rm:
2317 case X86::VMOVUPSZ256rm:
2318 case X86::VMOVUPSZrm: {
2319 // Loads from constant pools are trivially rematerializable.
2320 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2321 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2322 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2323 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2324 MI->isInvariantLoad(AA)) {
2325 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2326 if (BaseReg == 0 || BaseReg == X86::RIP)
2328 // Allow re-materialization of PIC load.
2329 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2331 const MachineFunction &MF = *MI->getParent()->getParent();
2332 const MachineRegisterInfo &MRI = MF.getRegInfo();
2333 return regIsPICBase(BaseReg, MRI);
2340 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2341 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2342 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2343 !MI->getOperand(1+X86::AddrDisp).isReg()) {
2344 // lea fi#, lea GV, etc. are all rematerializable.
2345 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2347 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2350 // Allow re-materialization of lea PICBase + x.
2351 const MachineFunction &MF = *MI->getParent()->getParent();
2352 const MachineRegisterInfo &MRI = MF.getRegInfo();
2353 return regIsPICBase(BaseReg, MRI);
2359 // All other instructions marked M_REMATERIALIZABLE are always trivially
2360 // rematerializable.
2364 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2365 MachineBasicBlock::iterator I) const {
2366 MachineBasicBlock::iterator E = MBB.end();
2368 // For compile time consideration, if we are not able to determine the
2369 // safety after visiting 4 instructions in each direction, we will assume
2371 MachineBasicBlock::iterator Iter = I;
2372 for (unsigned i = 0; Iter != E && i < 4; ++i) {
2373 bool SeenDef = false;
2374 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2375 MachineOperand &MO = Iter->getOperand(j);
2376 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2380 if (MO.getReg() == X86::EFLAGS) {
2388 // This instruction defines EFLAGS, no need to look any further.
2391 // Skip over DBG_VALUE.
2392 while (Iter != E && Iter->isDebugValue())
2396 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2399 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2400 SE = MBB.succ_end(); SI != SE; ++SI)
2401 if ((*SI)->isLiveIn(X86::EFLAGS))
2406 MachineBasicBlock::iterator B = MBB.begin();
2408 for (unsigned i = 0; i < 4; ++i) {
2409 // If we make it to the beginning of the block, it's safe to clobber
2410 // EFLAGS iff EFLAGS is not live-in.
2412 return !MBB.isLiveIn(X86::EFLAGS);
2415 // Skip over DBG_VALUE.
2416 while (Iter != B && Iter->isDebugValue())
2419 bool SawKill = false;
2420 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2421 MachineOperand &MO = Iter->getOperand(j);
2422 // A register mask may clobber EFLAGS, but we should still look for a
2424 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2426 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2427 if (MO.isDef()) return MO.isDead();
2428 if (MO.isKill()) SawKill = true;
2433 // This instruction kills EFLAGS and doesn't redefine it, so
2434 // there's no need to look further.
2438 // Conservative answer.
2442 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2443 MachineBasicBlock::iterator I,
2444 unsigned DestReg, unsigned SubIdx,
2445 const MachineInstr *Orig,
2446 const TargetRegisterInfo &TRI) const {
2447 // MOV32r0 is implemented with a xor which clobbers condition code.
2448 // Re-materialize it as movri instructions to avoid side effects.
2449 unsigned Opc = Orig->getOpcode();
2450 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2451 DebugLoc DL = Orig->getDebugLoc();
2452 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2455 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2459 MachineInstr *NewMI = std::prev(I);
2460 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2463 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2464 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2465 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2466 MachineOperand &MO = MI->getOperand(i);
2467 if (MO.isReg() && MO.isDef() &&
2468 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2475 /// Check whether the shift count for a machine operand is non-zero.
2476 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2477 unsigned ShiftAmtOperandIdx) {
2478 // The shift count is six bits with the REX.W prefix and five bits without.
2479 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2480 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2481 return Imm & ShiftCountMask;
2484 /// Check whether the given shift count is appropriate
2485 /// can be represented by a LEA instruction.
2486 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2487 // Left shift instructions can be transformed into load-effective-address
2488 // instructions if we can encode them appropriately.
2489 // A LEA instruction utilizes a SIB byte to encode its scale factor.
2490 // The SIB.scale field is two bits wide which means that we can encode any
2491 // shift amount less than 4.
2492 return ShAmt < 4 && ShAmt > 0;
2495 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2496 unsigned Opc, bool AllowSP,
2497 unsigned &NewSrc, bool &isKill, bool &isUndef,
2498 MachineOperand &ImplicitOp) const {
2499 MachineFunction &MF = *MI->getParent()->getParent();
2500 const TargetRegisterClass *RC;
2502 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2504 RC = Opc != X86::LEA32r ?
2505 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2507 unsigned SrcReg = Src.getReg();
2509 // For both LEA64 and LEA32 the register already has essentially the right
2510 // type (32-bit or 64-bit) we may just need to forbid SP.
2511 if (Opc != X86::LEA64_32r) {
2513 isKill = Src.isKill();
2514 isUndef = Src.isUndef();
2516 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2517 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2523 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2524 // another we need to add 64-bit registers to the final MI.
2525 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2527 ImplicitOp.setImplicit();
2529 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2530 MachineBasicBlock::LivenessQueryResult LQR =
2531 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2534 case MachineBasicBlock::LQR_Unknown:
2535 // We can't give sane liveness flags to the instruction, abandon LEA
2538 case MachineBasicBlock::LQR_Live:
2539 isKill = MI->killsRegister(SrcReg);
2543 // The physreg itself is dead, so we have to use it as an <undef>.
2549 // Virtual register of the wrong class, we have to create a temporary 64-bit
2550 // vreg to feed into the LEA.
2551 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2552 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2553 get(TargetOpcode::COPY))
2554 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2557 // Which is obviously going to be dead after we're done with it.
2562 // We've set all the parameters without issue.
2566 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2567 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2568 /// truncating back down to a 16-bit subregister.
2570 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2571 MachineFunction::iterator &MFI,
2572 MachineBasicBlock::iterator &MBBI,
2573 LiveVariables *LV) const {
2574 MachineInstr *MI = MBBI;
2575 unsigned Dest = MI->getOperand(0).getReg();
2576 unsigned Src = MI->getOperand(1).getReg();
2577 bool isDead = MI->getOperand(0).isDead();
2578 bool isKill = MI->getOperand(1).isKill();
2580 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2581 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2582 unsigned Opc, leaInReg;
2583 if (Subtarget.is64Bit()) {
2584 Opc = X86::LEA64_32r;
2585 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2588 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2591 // Build and insert into an implicit UNDEF value. This is OK because
2592 // well be shifting and then extracting the lower 16-bits.
2593 // This has the potential to cause partial register stall. e.g.
2594 // movw (%rbp,%rcx,2), %dx
2595 // leal -65(%rdx), %esi
2596 // But testing has shown this *does* help performance in 64-bit mode (at
2597 // least on modern x86 machines).
2598 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2599 MachineInstr *InsMI =
2600 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2601 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2602 .addReg(Src, getKillRegState(isKill));
2604 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2605 get(Opc), leaOutReg);
2607 default: llvm_unreachable("Unreachable!");
2608 case X86::SHL16ri: {
2609 unsigned ShAmt = MI->getOperand(2).getImm();
2610 MIB.addReg(0).addImm(1 << ShAmt)
2611 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2615 addRegOffset(MIB, leaInReg, true, 1);
2618 addRegOffset(MIB, leaInReg, true, -1);
2622 case X86::ADD16ri_DB:
2623 case X86::ADD16ri8_DB:
2624 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2627 case X86::ADD16rr_DB: {
2628 unsigned Src2 = MI->getOperand(2).getReg();
2629 bool isKill2 = MI->getOperand(2).isKill();
2630 unsigned leaInReg2 = 0;
2631 MachineInstr *InsMI2 = nullptr;
2633 // ADD16rr %reg1028<kill>, %reg1028
2634 // just a single insert_subreg.
2635 addRegReg(MIB, leaInReg, true, leaInReg, false);
2637 if (Subtarget.is64Bit())
2638 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2640 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2641 // Build and insert into an implicit UNDEF value. This is OK because
2642 // well be shifting and then extracting the lower 16-bits.
2643 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2645 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2646 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2647 .addReg(Src2, getKillRegState(isKill2));
2648 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2650 if (LV && isKill2 && InsMI2)
2651 LV->replaceKillInstruction(Src2, MI, InsMI2);
2656 MachineInstr *NewMI = MIB;
2657 MachineInstr *ExtMI =
2658 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2659 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2660 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2663 // Update live variables
2664 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2665 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2667 LV->replaceKillInstruction(Src, MI, InsMI);
2669 LV->replaceKillInstruction(Dest, MI, ExtMI);
2675 /// This method must be implemented by targets that
2676 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2677 /// may be able to convert a two-address instruction into a true
2678 /// three-address instruction on demand. This allows the X86 target (for
2679 /// example) to convert ADD and SHL instructions into LEA instructions if they
2680 /// would require register copies due to two-addressness.
2682 /// This method returns a null pointer if the transformation cannot be
2683 /// performed, otherwise it returns the new instruction.
2686 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2687 MachineBasicBlock::iterator &MBBI,
2688 LiveVariables *LV) const {
2689 MachineInstr *MI = MBBI;
2691 // The following opcodes also sets the condition code register(s). Only
2692 // convert them to equivalent lea if the condition code register def's
2694 if (hasLiveCondCodeDef(MI))
2697 MachineFunction &MF = *MI->getParent()->getParent();
2698 // All instructions input are two-addr instructions. Get the known operands.
2699 const MachineOperand &Dest = MI->getOperand(0);
2700 const MachineOperand &Src = MI->getOperand(1);
2702 MachineInstr *NewMI = nullptr;
2703 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2704 // we have better subtarget support, enable the 16-bit LEA generation here.
2705 // 16-bit LEA is also slow on Core2.
2706 bool DisableLEA16 = true;
2707 bool is64Bit = Subtarget.is64Bit();
2709 unsigned MIOpc = MI->getOpcode();
2711 default: return nullptr;
2712 case X86::SHL64ri: {
2713 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2714 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2715 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2717 // LEA can't handle RSP.
2718 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2719 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2720 &X86::GR64_NOSPRegClass))
2723 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2725 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2728 case X86::SHL32ri: {
2729 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2730 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2731 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2733 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2735 // LEA can't handle ESP.
2736 bool isKill, isUndef;
2738 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2739 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2740 SrcReg, isKill, isUndef, ImplicitOp))
2743 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2745 .addReg(0).addImm(1 << ShAmt)
2746 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2747 .addImm(0).addReg(0);
2748 if (ImplicitOp.getReg() != 0)
2749 MIB.addOperand(ImplicitOp);
2754 case X86::SHL16ri: {
2755 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2756 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2757 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2760 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2761 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2763 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2768 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2769 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2770 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2771 bool isKill, isUndef;
2773 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2774 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2775 SrcReg, isKill, isUndef, ImplicitOp))
2778 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2780 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2781 if (ImplicitOp.getReg() != 0)
2782 MIB.addOperand(ImplicitOp);
2784 NewMI = addOffset(MIB, 1);
2789 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2791 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2792 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2793 .addOperand(Dest).addOperand(Src), 1);
2797 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2798 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2799 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2801 bool isKill, isUndef;
2803 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2804 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2805 SrcReg, isKill, isUndef, ImplicitOp))
2808 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2810 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2811 if (ImplicitOp.getReg() != 0)
2812 MIB.addOperand(ImplicitOp);
2814 NewMI = addOffset(MIB, -1);
2820 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2822 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2823 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2824 .addOperand(Dest).addOperand(Src), -1);
2827 case X86::ADD64rr_DB:
2829 case X86::ADD32rr_DB: {
2830 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2832 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2835 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2837 bool isKill, isUndef;
2839 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2840 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2841 SrcReg, isKill, isUndef, ImplicitOp))
2844 const MachineOperand &Src2 = MI->getOperand(2);
2845 bool isKill2, isUndef2;
2847 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2848 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2849 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2852 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2854 if (ImplicitOp.getReg() != 0)
2855 MIB.addOperand(ImplicitOp);
2856 if (ImplicitOp2.getReg() != 0)
2857 MIB.addOperand(ImplicitOp2);
2859 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2861 // Preserve undefness of the operands.
2862 NewMI->getOperand(1).setIsUndef(isUndef);
2863 NewMI->getOperand(3).setIsUndef(isUndef2);
2865 if (LV && Src2.isKill())
2866 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2870 case X86::ADD16rr_DB: {
2872 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2874 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2875 unsigned Src2 = MI->getOperand(2).getReg();
2876 bool isKill2 = MI->getOperand(2).isKill();
2877 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2879 Src.getReg(), Src.isKill(), Src2, isKill2);
2881 // Preserve undefness of the operands.
2882 bool isUndef = MI->getOperand(1).isUndef();
2883 bool isUndef2 = MI->getOperand(2).isUndef();
2884 NewMI->getOperand(1).setIsUndef(isUndef);
2885 NewMI->getOperand(3).setIsUndef(isUndef2);
2888 LV->replaceKillInstruction(Src2, MI, NewMI);
2891 case X86::ADD64ri32:
2893 case X86::ADD64ri32_DB:
2894 case X86::ADD64ri8_DB:
2895 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2896 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2897 .addOperand(Dest).addOperand(Src),
2898 MI->getOperand(2).getImm());
2902 case X86::ADD32ri_DB:
2903 case X86::ADD32ri8_DB: {
2904 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2905 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2907 bool isKill, isUndef;
2909 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2910 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2911 SrcReg, isKill, isUndef, ImplicitOp))
2914 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2916 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2917 if (ImplicitOp.getReg() != 0)
2918 MIB.addOperand(ImplicitOp);
2920 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2925 case X86::ADD16ri_DB:
2926 case X86::ADD16ri8_DB:
2928 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2930 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2931 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2932 .addOperand(Dest).addOperand(Src),
2933 MI->getOperand(2).getImm());
2937 if (!NewMI) return nullptr;
2939 if (LV) { // Update live variables
2941 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2943 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2946 MFI->insert(MBBI, NewMI); // Insert the new inst
2950 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
2953 unsigned OpIdx2) const {
2954 switch (MI->getOpcode()) {
2955 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2956 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2957 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2958 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2959 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2960 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2963 switch (MI->getOpcode()) {
2964 default: llvm_unreachable("Unreachable!");
2965 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2966 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2967 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2968 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2969 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2970 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2972 unsigned Amt = MI->getOperand(3).getImm();
2974 MachineFunction &MF = *MI->getParent()->getParent();
2975 MI = MF.CloneMachineInstr(MI);
2978 MI->setDesc(get(Opc));
2979 MI->getOperand(3).setImm(Size-Amt);
2980 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2982 case X86::BLENDPDrri:
2983 case X86::BLENDPSrri:
2984 case X86::PBLENDWrri:
2985 case X86::VBLENDPDrri:
2986 case X86::VBLENDPSrri:
2987 case X86::VBLENDPDYrri:
2988 case X86::VBLENDPSYrri:
2989 case X86::VPBLENDDrri:
2990 case X86::VPBLENDWrri:
2991 case X86::VPBLENDDYrri:
2992 case X86::VPBLENDWYrri:{
2994 switch (MI->getOpcode()) {
2995 default: llvm_unreachable("Unreachable!");
2996 case X86::BLENDPDrri: Mask = 0x03; break;
2997 case X86::BLENDPSrri: Mask = 0x0F; break;
2998 case X86::PBLENDWrri: Mask = 0xFF; break;
2999 case X86::VBLENDPDrri: Mask = 0x03; break;
3000 case X86::VBLENDPSrri: Mask = 0x0F; break;
3001 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3002 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3003 case X86::VPBLENDDrri: Mask = 0x0F; break;
3004 case X86::VPBLENDWrri: Mask = 0xFF; break;
3005 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3006 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3008 // Only the least significant bits of Imm are used.
3009 unsigned Imm = MI->getOperand(3).getImm() & Mask;
3011 MachineFunction &MF = *MI->getParent()->getParent();
3012 MI = MF.CloneMachineInstr(MI);
3015 MI->getOperand(3).setImm(Mask ^ Imm);
3016 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3018 case X86::PCLMULQDQrr:
3019 case X86::VPCLMULQDQrr:{
3020 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3021 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3022 unsigned Imm = MI->getOperand(3).getImm();
3023 unsigned Src1Hi = Imm & 0x01;
3024 unsigned Src2Hi = Imm & 0x10;
3026 MachineFunction &MF = *MI->getParent()->getParent();
3027 MI = MF.CloneMachineInstr(MI);
3030 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3031 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3035 case X86::VCMPPDrri:
3036 case X86::VCMPPSrri:
3037 case X86::VCMPPDYrri:
3038 case X86::VCMPPSYrri: {
3039 // Float comparison can be safely commuted for
3040 // Ordered/Unordered/Equal/NotEqual tests
3041 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3044 case 0x03: // UNORDERED
3045 case 0x04: // NOT EQUAL
3046 case 0x07: // ORDERED
3048 MachineFunction &MF = *MI->getParent()->getParent();
3049 MI = MF.CloneMachineInstr(MI);
3052 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3057 case X86::VPCOMBri: case X86::VPCOMUBri:
3058 case X86::VPCOMDri: case X86::VPCOMUDri:
3059 case X86::VPCOMQri: case X86::VPCOMUQri:
3060 case X86::VPCOMWri: case X86::VPCOMUWri: {
3061 // Flip comparison mode immediate (if necessary).
3062 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3064 case 0x00: Imm = 0x02; break; // LT -> GT
3065 case 0x01: Imm = 0x03; break; // LE -> GE
3066 case 0x02: Imm = 0x00; break; // GT -> LT
3067 case 0x03: Imm = 0x01; break; // GE -> LE
3076 MachineFunction &MF = *MI->getParent()->getParent();
3077 MI = MF.CloneMachineInstr(MI);
3080 MI->getOperand(3).setImm(Imm);
3081 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3083 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3084 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3085 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3086 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3087 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3088 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3089 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3090 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3091 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3092 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3093 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3094 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3095 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3096 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3097 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3098 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3100 switch (MI->getOpcode()) {
3101 default: llvm_unreachable("Unreachable!");
3102 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3103 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3104 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3105 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3106 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3107 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3108 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3109 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3110 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3111 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3112 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3113 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3114 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3115 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3116 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3117 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3118 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3119 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
3120 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3121 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3122 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3123 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3124 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3125 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3126 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3127 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3128 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3129 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3130 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3131 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3132 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3133 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
3134 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
3135 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3136 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3137 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3138 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3139 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
3140 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
3141 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3142 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3143 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3144 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3145 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
3146 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
3147 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3148 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3149 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3152 MachineFunction &MF = *MI->getParent()->getParent();
3153 MI = MF.CloneMachineInstr(MI);
3156 MI->setDesc(get(Opc));
3157 // Fallthrough intended.
3160 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3164 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3165 unsigned &SrcOpIdx1,
3166 unsigned &SrcOpIdx2) const {
3167 switch (MI->getOpcode()) {
3170 case X86::VCMPPDrri:
3171 case X86::VCMPPSrri:
3172 case X86::VCMPPDYrri:
3173 case X86::VCMPPSYrri: {
3174 // Float comparison can be safely commuted for
3175 // Ordered/Unordered/Equal/NotEqual tests
3176 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3179 case 0x03: // UNORDERED
3180 case 0x04: // NOT EQUAL
3181 case 0x07: // ORDERED
3182 // The indices of the commutable operands are 1 and 2.
3183 // Assign them to the returned operand indices here.
3184 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3188 case X86::VFMADDPDr231r:
3189 case X86::VFMADDPSr231r:
3190 case X86::VFMADDSDr231r:
3191 case X86::VFMADDSSr231r:
3192 case X86::VFMSUBPDr231r:
3193 case X86::VFMSUBPSr231r:
3194 case X86::VFMSUBSDr231r:
3195 case X86::VFMSUBSSr231r:
3196 case X86::VFNMADDPDr231r:
3197 case X86::VFNMADDPSr231r:
3198 case X86::VFNMADDSDr231r:
3199 case X86::VFNMADDSSr231r:
3200 case X86::VFNMSUBPDr231r:
3201 case X86::VFNMSUBPSr231r:
3202 case X86::VFNMSUBSDr231r:
3203 case X86::VFNMSUBSSr231r:
3204 case X86::VFMADDPDr231rY:
3205 case X86::VFMADDPSr231rY:
3206 case X86::VFMSUBPDr231rY:
3207 case X86::VFMSUBPSr231rY:
3208 case X86::VFNMADDPDr231rY:
3209 case X86::VFNMADDPSr231rY:
3210 case X86::VFNMSUBPDr231rY:
3211 case X86::VFNMSUBPSr231rY:
3212 // The indices of the commutable operands are 2 and 3.
3213 // Assign them to the returned operand indices here.
3214 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
3216 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3221 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3223 default: return X86::COND_INVALID;
3224 case X86::JE_1: return X86::COND_E;
3225 case X86::JNE_1: return X86::COND_NE;
3226 case X86::JL_1: return X86::COND_L;
3227 case X86::JLE_1: return X86::COND_LE;
3228 case X86::JG_1: return X86::COND_G;
3229 case X86::JGE_1: return X86::COND_GE;
3230 case X86::JB_1: return X86::COND_B;
3231 case X86::JBE_1: return X86::COND_BE;
3232 case X86::JA_1: return X86::COND_A;
3233 case X86::JAE_1: return X86::COND_AE;
3234 case X86::JS_1: return X86::COND_S;
3235 case X86::JNS_1: return X86::COND_NS;
3236 case X86::JP_1: return X86::COND_P;
3237 case X86::JNP_1: return X86::COND_NP;
3238 case X86::JO_1: return X86::COND_O;
3239 case X86::JNO_1: return X86::COND_NO;
3243 /// Return condition code of a SET opcode.
3244 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3246 default: return X86::COND_INVALID;
3247 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3248 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3249 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3250 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3251 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3252 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3253 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3254 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3255 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3256 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3257 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3258 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3259 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3260 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3261 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3262 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3266 /// Return condition code of a CMov opcode.
3267 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3269 default: return X86::COND_INVALID;
3270 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3271 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3273 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3274 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3275 return X86::COND_AE;
3276 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3277 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3279 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3280 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3281 return X86::COND_BE;
3282 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3283 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3285 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3286 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3288 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3289 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3290 return X86::COND_GE;
3291 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3292 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3294 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3295 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3296 return X86::COND_LE;
3297 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3298 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3299 return X86::COND_NE;
3300 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3301 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3302 return X86::COND_NO;
3303 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3304 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3305 return X86::COND_NP;
3306 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3307 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3308 return X86::COND_NS;
3309 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3310 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3312 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3313 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3315 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3316 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3321 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3323 default: llvm_unreachable("Illegal condition code!");
3324 case X86::COND_E: return X86::JE_1;
3325 case X86::COND_NE: return X86::JNE_1;
3326 case X86::COND_L: return X86::JL_1;
3327 case X86::COND_LE: return X86::JLE_1;
3328 case X86::COND_G: return X86::JG_1;
3329 case X86::COND_GE: return X86::JGE_1;
3330 case X86::COND_B: return X86::JB_1;
3331 case X86::COND_BE: return X86::JBE_1;
3332 case X86::COND_A: return X86::JA_1;
3333 case X86::COND_AE: return X86::JAE_1;
3334 case X86::COND_S: return X86::JS_1;
3335 case X86::COND_NS: return X86::JNS_1;
3336 case X86::COND_P: return X86::JP_1;
3337 case X86::COND_NP: return X86::JNP_1;
3338 case X86::COND_O: return X86::JO_1;
3339 case X86::COND_NO: return X86::JNO_1;
3343 /// Return the inverse of the specified condition,
3344 /// e.g. turning COND_E to COND_NE.
3345 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3347 default: llvm_unreachable("Illegal condition code!");
3348 case X86::COND_E: return X86::COND_NE;
3349 case X86::COND_NE: return X86::COND_E;
3350 case X86::COND_L: return X86::COND_GE;
3351 case X86::COND_LE: return X86::COND_G;
3352 case X86::COND_G: return X86::COND_LE;
3353 case X86::COND_GE: return X86::COND_L;
3354 case X86::COND_B: return X86::COND_AE;
3355 case X86::COND_BE: return X86::COND_A;
3356 case X86::COND_A: return X86::COND_BE;
3357 case X86::COND_AE: return X86::COND_B;
3358 case X86::COND_S: return X86::COND_NS;
3359 case X86::COND_NS: return X86::COND_S;
3360 case X86::COND_P: return X86::COND_NP;
3361 case X86::COND_NP: return X86::COND_P;
3362 case X86::COND_O: return X86::COND_NO;
3363 case X86::COND_NO: return X86::COND_O;
3367 /// Assuming the flags are set by MI(a,b), return the condition code if we
3368 /// modify the instructions such that flags are set by MI(b,a).
3369 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3371 default: return X86::COND_INVALID;
3372 case X86::COND_E: return X86::COND_E;
3373 case X86::COND_NE: return X86::COND_NE;
3374 case X86::COND_L: return X86::COND_G;
3375 case X86::COND_LE: return X86::COND_GE;
3376 case X86::COND_G: return X86::COND_L;
3377 case X86::COND_GE: return X86::COND_LE;
3378 case X86::COND_B: return X86::COND_A;
3379 case X86::COND_BE: return X86::COND_AE;
3380 case X86::COND_A: return X86::COND_B;
3381 case X86::COND_AE: return X86::COND_BE;
3385 /// Return a set opcode for the given condition and
3386 /// whether it has memory operand.
3387 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3388 static const uint16_t Opc[16][2] = {
3389 { X86::SETAr, X86::SETAm },
3390 { X86::SETAEr, X86::SETAEm },
3391 { X86::SETBr, X86::SETBm },
3392 { X86::SETBEr, X86::SETBEm },
3393 { X86::SETEr, X86::SETEm },
3394 { X86::SETGr, X86::SETGm },
3395 { X86::SETGEr, X86::SETGEm },
3396 { X86::SETLr, X86::SETLm },
3397 { X86::SETLEr, X86::SETLEm },
3398 { X86::SETNEr, X86::SETNEm },
3399 { X86::SETNOr, X86::SETNOm },
3400 { X86::SETNPr, X86::SETNPm },
3401 { X86::SETNSr, X86::SETNSm },
3402 { X86::SETOr, X86::SETOm },
3403 { X86::SETPr, X86::SETPm },
3404 { X86::SETSr, X86::SETSm }
3407 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3408 return Opc[CC][HasMemoryOperand ? 1 : 0];
3411 /// Return a cmov opcode for the given condition,
3412 /// register size in bytes, and operand type.
3413 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3414 bool HasMemoryOperand) {
3415 static const uint16_t Opc[32][3] = {
3416 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3417 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3418 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3419 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3420 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3421 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3422 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3423 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3424 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3425 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3426 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3427 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3428 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3429 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3430 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
3431 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3432 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3433 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3434 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3435 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3436 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3437 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3438 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3439 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3440 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3441 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3442 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3443 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3444 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3445 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3446 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3447 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
3450 assert(CC < 16 && "Can only handle standard cond codes");
3451 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3453 default: llvm_unreachable("Illegal register size!");
3454 case 2: return Opc[Idx][0];
3455 case 4: return Opc[Idx][1];
3456 case 8: return Opc[Idx][2];
3460 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3461 if (!MI->isTerminator()) return false;
3463 // Conditional branch is a special case.
3464 if (MI->isBranch() && !MI->isBarrier())
3466 if (!MI->isPredicable())
3468 return !isPredicated(MI);
3471 bool X86InstrInfo::AnalyzeBranchImpl(
3472 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3473 SmallVectorImpl<MachineOperand> &Cond,
3474 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3476 // Start from the bottom of the block and work up, examining the
3477 // terminator instructions.
3478 MachineBasicBlock::iterator I = MBB.end();
3479 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3480 while (I != MBB.begin()) {
3482 if (I->isDebugValue())
3485 // Working from the bottom, when we see a non-terminator instruction, we're
3487 if (!isUnpredicatedTerminator(I))
3490 // A terminator that isn't a branch can't easily be handled by this
3495 // Handle unconditional branches.
3496 if (I->getOpcode() == X86::JMP_1) {
3500 TBB = I->getOperand(0).getMBB();
3504 // If the block has any instructions after a JMP, delete them.
3505 while (std::next(I) != MBB.end())
3506 std::next(I)->eraseFromParent();
3511 // Delete the JMP if it's equivalent to a fall-through.
3512 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3514 I->eraseFromParent();
3516 UnCondBrIter = MBB.end();
3520 // TBB is used to indicate the unconditional destination.
3521 TBB = I->getOperand(0).getMBB();
3525 // Handle conditional branches.
3526 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3527 if (BranchCode == X86::COND_INVALID)
3528 return true; // Can't handle indirect branch.
3530 // Working from the bottom, handle the first conditional branch.
3532 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3533 if (AllowModify && UnCondBrIter != MBB.end() &&
3534 MBB.isLayoutSuccessor(TargetBB)) {
3535 // If we can modify the code and it ends in something like:
3543 // Then we can change this to:
3550 // Which is a bit more efficient.
3551 // We conditionally jump to the fall-through block.
3552 BranchCode = GetOppositeBranchCondition(BranchCode);
3553 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3554 MachineBasicBlock::iterator OldInst = I;
3556 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3557 .addMBB(UnCondBrIter->getOperand(0).getMBB());
3558 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3561 OldInst->eraseFromParent();
3562 UnCondBrIter->eraseFromParent();
3564 // Restart the analysis.
3565 UnCondBrIter = MBB.end();
3571 TBB = I->getOperand(0).getMBB();
3572 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3573 CondBranches.push_back(I);
3577 // Handle subsequent conditional branches. Only handle the case where all
3578 // conditional branches branch to the same destination and their condition
3579 // opcodes fit one of the special multi-branch idioms.
3580 assert(Cond.size() == 1);
3583 // Only handle the case where all conditional branches branch to the same
3585 if (TBB != I->getOperand(0).getMBB())
3588 // If the conditions are the same, we can leave them alone.
3589 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3590 if (OldBranchCode == BranchCode)
3593 // If they differ, see if they fit one of the known patterns. Theoretically,
3594 // we could handle more patterns here, but we shouldn't expect to see them
3595 // if instruction selection has done a reasonable job.
3596 if ((OldBranchCode == X86::COND_NP &&
3597 BranchCode == X86::COND_E) ||
3598 (OldBranchCode == X86::COND_E &&
3599 BranchCode == X86::COND_NP))
3600 BranchCode = X86::COND_NP_OR_E;
3601 else if ((OldBranchCode == X86::COND_P &&
3602 BranchCode == X86::COND_NE) ||
3603 (OldBranchCode == X86::COND_NE &&
3604 BranchCode == X86::COND_P))
3605 BranchCode = X86::COND_NE_OR_P;
3609 // Update the MachineOperand.
3610 Cond[0].setImm(BranchCode);
3611 CondBranches.push_back(I);
3617 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3618 MachineBasicBlock *&TBB,
3619 MachineBasicBlock *&FBB,
3620 SmallVectorImpl<MachineOperand> &Cond,
3621 bool AllowModify) const {
3622 SmallVector<MachineInstr *, 4> CondBranches;
3623 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3626 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
3627 MachineBranchPredicate &MBP,
3628 bool AllowModify) const {
3629 using namespace std::placeholders;
3631 SmallVector<MachineOperand, 4> Cond;
3632 SmallVector<MachineInstr *, 4> CondBranches;
3633 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3637 if (Cond.size() != 1)
3640 assert(MBP.TrueDest && "expected!");
3643 MBP.FalseDest = MBB.getNextNode();
3645 const TargetRegisterInfo *TRI = &getRegisterInfo();
3647 MachineInstr *ConditionDef = nullptr;
3648 bool SingleUseCondition = true;
3650 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3651 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3656 if (I->readsRegister(X86::EFLAGS, TRI))
3657 SingleUseCondition = false;
3663 if (SingleUseCondition) {
3664 for (auto *Succ : MBB.successors())
3665 if (Succ->isLiveIn(X86::EFLAGS))
3666 SingleUseCondition = false;
3669 MBP.ConditionDef = ConditionDef;
3670 MBP.SingleUseCondition = SingleUseCondition;
3672 // Currently we only recognize the simple pattern:
3677 const unsigned TestOpcode =
3678 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3680 if (ConditionDef->getOpcode() == TestOpcode &&
3681 ConditionDef->getNumOperands() == 3 &&
3682 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3683 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3684 MBP.LHS = ConditionDef->getOperand(0);
3685 MBP.RHS = MachineOperand::CreateImm(0);
3686 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3687 ? MachineBranchPredicate::PRED_NE
3688 : MachineBranchPredicate::PRED_EQ;
3695 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3696 MachineBasicBlock::iterator I = MBB.end();
3699 while (I != MBB.begin()) {
3701 if (I->isDebugValue())
3703 if (I->getOpcode() != X86::JMP_1 &&
3704 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3706 // Remove the branch.
3707 I->eraseFromParent();
3716 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3717 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
3718 DebugLoc DL) const {
3719 // Shouldn't be a fall through.
3720 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3721 assert((Cond.size() == 1 || Cond.size() == 0) &&
3722 "X86 branch conditions have one component!");
3725 // Unconditional branch?
3726 assert(!FBB && "Unconditional branch with multiple successors!");
3727 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3731 // Conditional branch.
3733 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3735 case X86::COND_NP_OR_E:
3736 // Synthesize NP_OR_E with two branches.
3737 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3739 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3742 case X86::COND_NE_OR_P:
3743 // Synthesize NE_OR_P with two branches.
3744 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3746 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3750 unsigned Opc = GetCondBranchFromCond(CC);
3751 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3756 // Two-way Conditional branch. Insert the second branch.
3757 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3764 canInsertSelect(const MachineBasicBlock &MBB,
3765 ArrayRef<MachineOperand> Cond,
3766 unsigned TrueReg, unsigned FalseReg,
3767 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3768 // Not all subtargets have cmov instructions.
3769 if (!Subtarget.hasCMov())
3771 if (Cond.size() != 1)
3773 // We cannot do the composite conditions, at least not in SSA form.
3774 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3777 // Check register classes.
3778 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3779 const TargetRegisterClass *RC =
3780 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3784 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3785 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3786 X86::GR32RegClass.hasSubClassEq(RC) ||
3787 X86::GR64RegClass.hasSubClassEq(RC)) {
3788 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3789 // Bridge. Probably Ivy Bridge as well.
3796 // Can't do vectors.
3800 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3801 MachineBasicBlock::iterator I, DebugLoc DL,
3802 unsigned DstReg, ArrayRef<MachineOperand> Cond,
3803 unsigned TrueReg, unsigned FalseReg) const {
3804 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3805 assert(Cond.size() == 1 && "Invalid Cond array");
3806 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3807 MRI.getRegClass(DstReg)->getSize(),
3808 false/*HasMemoryOperand*/);
3809 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3812 /// Test if the given register is a physical h register.
3813 static bool isHReg(unsigned Reg) {
3814 return X86::GR8_ABCD_HRegClass.contains(Reg);
3817 // Try and copy between VR128/VR64 and GR64 registers.
3818 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3819 const X86Subtarget &Subtarget) {
3821 // SrcReg(VR128) -> DestReg(GR64)
3822 // SrcReg(VR64) -> DestReg(GR64)
3823 // SrcReg(GR64) -> DestReg(VR128)
3824 // SrcReg(GR64) -> DestReg(VR64)
3826 bool HasAVX = Subtarget.hasAVX();
3827 bool HasAVX512 = Subtarget.hasAVX512();
3828 if (X86::GR64RegClass.contains(DestReg)) {
3829 if (X86::VR128XRegClass.contains(SrcReg))
3830 // Copy from a VR128 register to a GR64 register.
3831 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3833 if (X86::VR64RegClass.contains(SrcReg))
3834 // Copy from a VR64 register to a GR64 register.
3835 return X86::MMX_MOVD64from64rr;
3836 } else if (X86::GR64RegClass.contains(SrcReg)) {
3837 // Copy from a GR64 register to a VR128 register.
3838 if (X86::VR128XRegClass.contains(DestReg))
3839 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3841 // Copy from a GR64 register to a VR64 register.
3842 if (X86::VR64RegClass.contains(DestReg))
3843 return X86::MMX_MOVD64to64rr;
3846 // SrcReg(FR32) -> DestReg(GR32)
3847 // SrcReg(GR32) -> DestReg(FR32)
3849 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3850 // Copy from a FR32 register to a GR32 register.
3851 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3853 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3854 // Copy from a GR32 register to a FR32 register.
3855 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3859 inline static bool MaskRegClassContains(unsigned Reg) {
3860 return X86::VK8RegClass.contains(Reg) ||
3861 X86::VK16RegClass.contains(Reg) ||
3862 X86::VK32RegClass.contains(Reg) ||
3863 X86::VK64RegClass.contains(Reg) ||
3864 X86::VK1RegClass.contains(Reg);
3867 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3868 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3869 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3870 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3871 DestReg = get512BitSuperRegister(DestReg);
3872 SrcReg = get512BitSuperRegister(SrcReg);
3873 return X86::VMOVAPSZrr;
3875 if (MaskRegClassContains(DestReg) &&
3876 MaskRegClassContains(SrcReg))
3877 return X86::KMOVWkk;
3878 if (MaskRegClassContains(DestReg) &&
3879 (X86::GR32RegClass.contains(SrcReg) ||
3880 X86::GR16RegClass.contains(SrcReg) ||
3881 X86::GR8RegClass.contains(SrcReg))) {
3882 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3883 return X86::KMOVWkr;
3885 if ((X86::GR32RegClass.contains(DestReg) ||
3886 X86::GR16RegClass.contains(DestReg) ||
3887 X86::GR8RegClass.contains(DestReg)) &&
3888 MaskRegClassContains(SrcReg)) {
3889 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3890 return X86::KMOVWrk;
3895 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3896 MachineBasicBlock::iterator MI, DebugLoc DL,
3897 unsigned DestReg, unsigned SrcReg,
3898 bool KillSrc) const {
3899 // First deal with the normal symmetric copies.
3900 bool HasAVX = Subtarget.hasAVX();
3901 bool HasAVX512 = Subtarget.hasAVX512();
3903 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3905 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3907 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3909 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3910 // Copying to or from a physical H register on x86-64 requires a NOREX
3911 // move. Otherwise use a normal move.
3912 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3913 Subtarget.is64Bit()) {
3914 Opc = X86::MOV8rr_NOREX;
3915 // Both operands must be encodable without an REX prefix.
3916 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3917 "8-bit H register can not be copied outside GR8_NOREX");
3921 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3922 Opc = X86::MMX_MOVQ64rr;
3924 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3925 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3926 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3927 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3928 Opc = X86::VMOVAPSYrr;
3930 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3933 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3934 .addReg(SrcReg, getKillRegState(KillSrc));
3938 bool FromEFLAGS = SrcReg == X86::EFLAGS;
3939 bool ToEFLAGS = DestReg == X86::EFLAGS;
3940 int Reg = FromEFLAGS ? DestReg : SrcReg;
3941 bool is32 = X86::GR32RegClass.contains(Reg);
3942 bool is64 = X86::GR64RegClass.contains(Reg);
3943 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
3944 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
3945 // inefficient. Instead:
3946 // - Save the overflow flag OF into AL using SETO, and restore it using a
3947 // signed 8-bit addition of AL and INT8_MAX.
3948 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
3950 // - When RAX/EAX is live and isn't the destination register, make sure it
3951 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
3953 // This approach is ~2.25x faster than using PUSHF/POPF.
3955 // This is still somewhat inefficient because we don't know which flags are
3956 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
3957 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
3959 // PUSHF/POPF is also potentially incorrect because it affects other flags
3960 // such as TF/IF/DF, which LLVM doesn't model.
3962 // Notice that we have to adjust the stack if we don't want to clobber the
3963 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3965 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
3966 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
3967 int Pop = is64 ? X86::POP64r : X86::POP32r;
3968 int AX = is64 ? X86::RAX : X86::EAX;
3970 bool AXDead = (Reg == AX) ||
3971 (MachineBasicBlock::LQR_Dead ==
3972 MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
3975 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
3977 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
3978 BuildMI(MBB, MI, DL, get(X86::LAHF));
3979 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
3982 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
3983 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
3986 BuildMI(MBB, MI, DL, get(X86::SAHF));
3989 BuildMI(MBB, MI, DL, get(Pop), AX);
3993 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3994 << " to " << RI.getName(DestReg) << '\n');
3995 llvm_unreachable("Cannot emit physreg copy instruction");
3998 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3999 const TargetRegisterClass *RC,
4000 bool isStackAligned,
4001 const X86Subtarget &STI,
4003 if (STI.hasAVX512()) {
4004 if (X86::VK8RegClass.hasSubClassEq(RC) ||
4005 X86::VK16RegClass.hasSubClassEq(RC))
4006 return load ? X86::KMOVWkm : X86::KMOVWmk;
4007 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4008 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4009 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4010 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4011 if (X86::VR512RegClass.hasSubClassEq(RC))
4012 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4015 bool HasAVX = STI.hasAVX();
4016 switch (RC->getSize()) {
4018 llvm_unreachable("Unknown spill size");
4020 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4022 // Copying to or from a physical H register on x86-64 requires a NOREX
4023 // move. Otherwise use a normal move.
4024 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4025 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4026 return load ? X86::MOV8rm : X86::MOV8mr;
4028 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4029 return load ? X86::MOV16rm : X86::MOV16mr;
4031 if (X86::GR32RegClass.hasSubClassEq(RC))
4032 return load ? X86::MOV32rm : X86::MOV32mr;
4033 if (X86::FR32RegClass.hasSubClassEq(RC))
4035 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4036 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4037 if (X86::RFP32RegClass.hasSubClassEq(RC))
4038 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4039 llvm_unreachable("Unknown 4-byte regclass");
4041 if (X86::GR64RegClass.hasSubClassEq(RC))
4042 return load ? X86::MOV64rm : X86::MOV64mr;
4043 if (X86::FR64RegClass.hasSubClassEq(RC))
4045 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4046 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4047 if (X86::VR64RegClass.hasSubClassEq(RC))
4048 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4049 if (X86::RFP64RegClass.hasSubClassEq(RC))
4050 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4051 llvm_unreachable("Unknown 8-byte regclass");
4053 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4054 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4056 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4057 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4058 // If stack is realigned we can use aligned stores.
4061 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4062 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4065 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4066 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4069 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4070 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4071 // If stack is realigned we can use aligned stores.
4073 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4075 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4077 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4079 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4081 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4085 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4087 const TargetRegisterInfo *TRI) const {
4088 const MCInstrDesc &Desc = MemOp->getDesc();
4089 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
4090 if (MemRefBegin < 0)
4093 MemRefBegin += X86II::getOperandBias(Desc);
4095 BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
4096 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4099 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4103 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4105 // Displacement can be symbolic
4106 if (!DispMO.isImm())
4109 Offset = DispMO.getImm();
4111 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4115 static unsigned getStoreRegOpcode(unsigned SrcReg,
4116 const TargetRegisterClass *RC,
4117 bool isStackAligned,
4118 const X86Subtarget &STI) {
4119 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4123 static unsigned getLoadRegOpcode(unsigned DestReg,
4124 const TargetRegisterClass *RC,
4125 bool isStackAligned,
4126 const X86Subtarget &STI) {
4127 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4130 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4131 MachineBasicBlock::iterator MI,
4132 unsigned SrcReg, bool isKill, int FrameIdx,
4133 const TargetRegisterClass *RC,
4134 const TargetRegisterInfo *TRI) const {
4135 const MachineFunction &MF = *MBB.getParent();
4136 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4137 "Stack slot too small for store");
4138 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4140 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4141 RI.canRealignStack(MF);
4142 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4143 DebugLoc DL = MBB.findDebugLoc(MI);
4144 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4145 .addReg(SrcReg, getKillRegState(isKill));
4148 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4150 SmallVectorImpl<MachineOperand> &Addr,
4151 const TargetRegisterClass *RC,
4152 MachineInstr::mmo_iterator MMOBegin,
4153 MachineInstr::mmo_iterator MMOEnd,
4154 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4155 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4156 bool isAligned = MMOBegin != MMOEnd &&
4157 (*MMOBegin)->getAlignment() >= Alignment;
4158 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4160 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4161 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4162 MIB.addOperand(Addr[i]);
4163 MIB.addReg(SrcReg, getKillRegState(isKill));
4164 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4165 NewMIs.push_back(MIB);
4169 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4170 MachineBasicBlock::iterator MI,
4171 unsigned DestReg, int FrameIdx,
4172 const TargetRegisterClass *RC,
4173 const TargetRegisterInfo *TRI) const {
4174 const MachineFunction &MF = *MBB.getParent();
4175 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4177 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4178 RI.canRealignStack(MF);
4179 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4180 DebugLoc DL = MBB.findDebugLoc(MI);
4181 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4184 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4185 SmallVectorImpl<MachineOperand> &Addr,
4186 const TargetRegisterClass *RC,
4187 MachineInstr::mmo_iterator MMOBegin,
4188 MachineInstr::mmo_iterator MMOEnd,
4189 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4190 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4191 bool isAligned = MMOBegin != MMOEnd &&
4192 (*MMOBegin)->getAlignment() >= Alignment;
4193 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4195 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4196 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4197 MIB.addOperand(Addr[i]);
4198 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4199 NewMIs.push_back(MIB);
4203 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4204 int &CmpMask, int &CmpValue) const {
4205 switch (MI->getOpcode()) {
4207 case X86::CMP64ri32:
4214 SrcReg = MI->getOperand(0).getReg();
4217 CmpValue = MI->getOperand(1).getImm();
4219 // A SUB can be used to perform comparison.
4224 SrcReg = MI->getOperand(1).getReg();
4233 SrcReg = MI->getOperand(1).getReg();
4234 SrcReg2 = MI->getOperand(2).getReg();
4238 case X86::SUB64ri32:
4245 SrcReg = MI->getOperand(1).getReg();
4248 CmpValue = MI->getOperand(2).getImm();
4254 SrcReg = MI->getOperand(0).getReg();
4255 SrcReg2 = MI->getOperand(1).getReg();
4263 SrcReg = MI->getOperand(0).getReg();
4264 if (MI->getOperand(1).getReg() != SrcReg) return false;
4265 // Compare against zero.
4274 /// Check whether the first instruction, whose only
4275 /// purpose is to update flags, can be made redundant.
4276 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4277 /// This function can be extended later on.
4278 /// SrcReg, SrcRegs: register operands for FlagI.
4279 /// ImmValue: immediate for FlagI if it takes an immediate.
4280 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4281 unsigned SrcReg2, int ImmValue,
4283 if (((FlagI->getOpcode() == X86::CMP64rr &&
4284 OI->getOpcode() == X86::SUB64rr) ||
4285 (FlagI->getOpcode() == X86::CMP32rr &&
4286 OI->getOpcode() == X86::SUB32rr)||
4287 (FlagI->getOpcode() == X86::CMP16rr &&
4288 OI->getOpcode() == X86::SUB16rr)||
4289 (FlagI->getOpcode() == X86::CMP8rr &&
4290 OI->getOpcode() == X86::SUB8rr)) &&
4291 ((OI->getOperand(1).getReg() == SrcReg &&
4292 OI->getOperand(2).getReg() == SrcReg2) ||
4293 (OI->getOperand(1).getReg() == SrcReg2 &&
4294 OI->getOperand(2).getReg() == SrcReg)))
4297 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4298 OI->getOpcode() == X86::SUB64ri32) ||
4299 (FlagI->getOpcode() == X86::CMP64ri8 &&
4300 OI->getOpcode() == X86::SUB64ri8) ||
4301 (FlagI->getOpcode() == X86::CMP32ri &&
4302 OI->getOpcode() == X86::SUB32ri) ||
4303 (FlagI->getOpcode() == X86::CMP32ri8 &&
4304 OI->getOpcode() == X86::SUB32ri8) ||
4305 (FlagI->getOpcode() == X86::CMP16ri &&
4306 OI->getOpcode() == X86::SUB16ri) ||
4307 (FlagI->getOpcode() == X86::CMP16ri8 &&
4308 OI->getOpcode() == X86::SUB16ri8) ||
4309 (FlagI->getOpcode() == X86::CMP8ri &&
4310 OI->getOpcode() == X86::SUB8ri)) &&
4311 OI->getOperand(1).getReg() == SrcReg &&
4312 OI->getOperand(2).getImm() == ImmValue)
4317 /// Check whether the definition can be converted
4318 /// to remove a comparison against zero.
4319 inline static bool isDefConvertible(MachineInstr *MI) {
4320 switch (MI->getOpcode()) {
4321 default: return false;
4323 // The shift instructions only modify ZF if their shift count is non-zero.
4324 // N.B.: The processor truncates the shift count depending on the encoding.
4325 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4326 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4327 return getTruncatedShiftCount(MI, 2) != 0;
4329 // Some left shift instructions can be turned into LEA instructions but only
4330 // if their flags aren't used. Avoid transforming such instructions.
4331 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4332 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4333 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4337 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4338 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4339 return getTruncatedShiftCount(MI, 3) != 0;
4341 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4342 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4343 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4344 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4345 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
4346 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
4347 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4348 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4349 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4350 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4351 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
4352 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4353 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4354 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4355 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4356 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4357 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4358 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4359 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4360 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4361 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4362 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4363 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4364 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4365 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4366 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4367 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
4368 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4369 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4370 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4371 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4372 case X86::ADC32ri: case X86::ADC32ri8:
4373 case X86::ADC32rr: case X86::ADC64ri32:
4374 case X86::ADC64ri8: case X86::ADC64rr:
4375 case X86::SBB32ri: case X86::SBB32ri8:
4376 case X86::SBB32rr: case X86::SBB64ri32:
4377 case X86::SBB64ri8: case X86::SBB64rr:
4378 case X86::ANDN32rr: case X86::ANDN32rm:
4379 case X86::ANDN64rr: case X86::ANDN64rm:
4380 case X86::BEXTR32rr: case X86::BEXTR64rr:
4381 case X86::BEXTR32rm: case X86::BEXTR64rm:
4382 case X86::BLSI32rr: case X86::BLSI32rm:
4383 case X86::BLSI64rr: case X86::BLSI64rm:
4384 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4385 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4386 case X86::BLSR32rr: case X86::BLSR32rm:
4387 case X86::BLSR64rr: case X86::BLSR64rm:
4388 case X86::BZHI32rr: case X86::BZHI32rm:
4389 case X86::BZHI64rr: case X86::BZHI64rm:
4390 case X86::LZCNT16rr: case X86::LZCNT16rm:
4391 case X86::LZCNT32rr: case X86::LZCNT32rm:
4392 case X86::LZCNT64rr: case X86::LZCNT64rm:
4393 case X86::POPCNT16rr:case X86::POPCNT16rm:
4394 case X86::POPCNT32rr:case X86::POPCNT32rm:
4395 case X86::POPCNT64rr:case X86::POPCNT64rm:
4396 case X86::TZCNT16rr: case X86::TZCNT16rm:
4397 case X86::TZCNT32rr: case X86::TZCNT32rm:
4398 case X86::TZCNT64rr: case X86::TZCNT64rm:
4403 /// Check whether the use can be converted to remove a comparison against zero.
4404 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4405 switch (MI->getOpcode()) {
4406 default: return X86::COND_INVALID;
4407 case X86::LZCNT16rr: case X86::LZCNT16rm:
4408 case X86::LZCNT32rr: case X86::LZCNT32rm:
4409 case X86::LZCNT64rr: case X86::LZCNT64rm:
4411 case X86::POPCNT16rr:case X86::POPCNT16rm:
4412 case X86::POPCNT32rr:case X86::POPCNT32rm:
4413 case X86::POPCNT64rr:case X86::POPCNT64rm:
4415 case X86::TZCNT16rr: case X86::TZCNT16rm:
4416 case X86::TZCNT32rr: case X86::TZCNT32rm:
4417 case X86::TZCNT64rr: case X86::TZCNT64rm:
4422 /// Check if there exists an earlier instruction that
4423 /// operates on the same source operands and sets flags in the same way as
4424 /// Compare; remove Compare if possible.
4426 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4427 int CmpMask, int CmpValue,
4428 const MachineRegisterInfo *MRI) const {
4429 // Check whether we can replace SUB with CMP.
4430 unsigned NewOpcode = 0;
4431 switch (CmpInstr->getOpcode()) {
4433 case X86::SUB64ri32:
4448 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4450 // There is no use of the destination register, we can replace SUB with CMP.
4451 switch (CmpInstr->getOpcode()) {
4452 default: llvm_unreachable("Unreachable!");
4453 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4454 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4455 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4456 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4457 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4458 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4459 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4460 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4461 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4462 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4463 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4464 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4465 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4466 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4467 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4469 CmpInstr->setDesc(get(NewOpcode));
4470 CmpInstr->RemoveOperand(0);
4471 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4472 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4473 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4478 // Get the unique definition of SrcReg.
4479 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4480 if (!MI) return false;
4482 // CmpInstr is the first instruction of the BB.
4483 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4485 // If we are comparing against zero, check whether we can use MI to update
4486 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4487 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4488 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
4491 // If we have a use of the source register between the def and our compare
4492 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4494 bool ShouldUpdateCC = false;
4495 X86::CondCode NewCC = X86::COND_INVALID;
4496 if (IsCmpZero && !isDefConvertible(MI)) {
4497 // Scan forward from the use until we hit the use we're looking for or the
4498 // compare instruction.
4499 for (MachineBasicBlock::iterator J = MI;; ++J) {
4500 // Do we have a convertible instruction?
4501 NewCC = isUseDefConvertible(J);
4502 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4503 J->getOperand(1).getReg() == SrcReg) {
4504 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4505 ShouldUpdateCC = true; // Update CC later on.
4506 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4507 // with the new def.
4517 // We are searching for an earlier instruction that can make CmpInstr
4518 // redundant and that instruction will be saved in Sub.
4519 MachineInstr *Sub = nullptr;
4520 const TargetRegisterInfo *TRI = &getRegisterInfo();
4522 // We iterate backward, starting from the instruction before CmpInstr and
4523 // stop when reaching the definition of a source register or done with the BB.
4524 // RI points to the instruction before CmpInstr.
4525 // If the definition is in this basic block, RE points to the definition;
4526 // otherwise, RE is the rend of the basic block.
4527 MachineBasicBlock::reverse_iterator
4528 RI = MachineBasicBlock::reverse_iterator(I),
4529 RE = CmpInstr->getParent() == MI->getParent() ?
4530 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4531 CmpInstr->getParent()->rend();
4532 MachineInstr *Movr0Inst = nullptr;
4533 for (; RI != RE; ++RI) {
4534 MachineInstr *Instr = &*RI;
4535 // Check whether CmpInstr can be made redundant by the current instruction.
4537 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
4542 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
4543 Instr->readsRegister(X86::EFLAGS, TRI)) {
4544 // This instruction modifies or uses EFLAGS.
4546 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4547 // They are safe to move up, if the definition to EFLAGS is dead and
4548 // earlier instructions do not read or write EFLAGS.
4549 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
4550 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4555 // We can't remove CmpInstr.
4560 // Return false if no candidates exist.
4561 if (!IsCmpZero && !Sub)
4564 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4565 Sub->getOperand(2).getReg() == SrcReg);
4567 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4568 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4569 // If we are done with the basic block, we need to check whether EFLAGS is
4571 bool IsSafe = false;
4572 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4573 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4574 for (++I; I != E; ++I) {
4575 const MachineInstr &Instr = *I;
4576 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4577 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4578 // We should check the usage if this instruction uses and updates EFLAGS.
4579 if (!UseEFLAGS && ModifyEFLAGS) {
4580 // It is safe to remove CmpInstr if EFLAGS is updated again.
4584 if (!UseEFLAGS && !ModifyEFLAGS)
4587 // EFLAGS is used by this instruction.
4588 X86::CondCode OldCC = X86::COND_INVALID;
4589 bool OpcIsSET = false;
4590 if (IsCmpZero || IsSwapped) {
4591 // We decode the condition code from opcode.
4592 if (Instr.isBranch())
4593 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4595 OldCC = getCondFromSETOpc(Instr.getOpcode());
4596 if (OldCC != X86::COND_INVALID)
4599 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4601 if (OldCC == X86::COND_INVALID) return false;
4606 case X86::COND_A: case X86::COND_AE:
4607 case X86::COND_B: case X86::COND_BE:
4608 case X86::COND_G: case X86::COND_GE:
4609 case X86::COND_L: case X86::COND_LE:
4610 case X86::COND_O: case X86::COND_NO:
4611 // CF and OF are used, we can't perform this optimization.
4615 // If we're updating the condition code check if we have to reverse the
4624 NewCC = GetOppositeBranchCondition(NewCC);
4627 } else if (IsSwapped) {
4628 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4629 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4630 // We swap the condition code and synthesize the new opcode.
4631 NewCC = getSwappedCondition(OldCC);
4632 if (NewCC == X86::COND_INVALID) return false;
4635 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4636 // Synthesize the new opcode.
4637 bool HasMemoryOperand = Instr.hasOneMemOperand();
4639 if (Instr.isBranch())
4640 NewOpc = GetCondBranchFromCond(NewCC);
4642 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4644 unsigned DstReg = Instr.getOperand(0).getReg();
4645 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4649 // Push the MachineInstr to OpsToUpdate.
4650 // If it is safe to remove CmpInstr, the condition code of these
4651 // instructions will be modified.
4652 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4654 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4655 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4661 // If EFLAGS is not killed nor re-defined, we should check whether it is
4662 // live-out. If it is live-out, do not optimize.
4663 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4664 MachineBasicBlock *MBB = CmpInstr->getParent();
4665 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4666 SE = MBB->succ_end(); SI != SE; ++SI)
4667 if ((*SI)->isLiveIn(X86::EFLAGS))
4671 // The instruction to be updated is either Sub or MI.
4672 Sub = IsCmpZero ? MI : Sub;
4673 // Move Movr0Inst to the appropriate place before Sub.
4675 // Look backwards until we find a def that doesn't use the current EFLAGS.
4677 MachineBasicBlock::reverse_iterator
4678 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4679 InsertE = Sub->getParent()->rend();
4680 for (; InsertI != InsertE; ++InsertI) {
4681 MachineInstr *Instr = &*InsertI;
4682 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4683 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4684 Sub->getParent()->remove(Movr0Inst);
4685 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4690 if (InsertI == InsertE)
4694 // Make sure Sub instruction defines EFLAGS and mark the def live.
4695 unsigned i = 0, e = Sub->getNumOperands();
4696 for (; i != e; ++i) {
4697 MachineOperand &MO = Sub->getOperand(i);
4698 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4699 MO.setIsDead(false);
4703 assert(i != e && "Unable to locate a def EFLAGS operand");
4705 CmpInstr->eraseFromParent();
4707 // Modify the condition code of instructions in OpsToUpdate.
4708 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4709 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4713 /// Try to remove the load by folding it to a register
4714 /// operand at the use. We fold the load instructions if load defines a virtual
4715 /// register, the virtual register is used once in the same BB, and the
4716 /// instructions in-between do not load or store, and have no side effects.
4717 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4718 const MachineRegisterInfo *MRI,
4719 unsigned &FoldAsLoadDefReg,
4720 MachineInstr *&DefMI) const {
4721 if (FoldAsLoadDefReg == 0)
4723 // To be conservative, if there exists another load, clear the load candidate.
4724 if (MI->mayLoad()) {
4725 FoldAsLoadDefReg = 0;
4729 // Check whether we can move DefMI here.
4730 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4732 bool SawStore = false;
4733 if (!DefMI->isSafeToMove(nullptr, SawStore))
4736 // Collect information about virtual register operands of MI.
4737 unsigned SrcOperandId = 0;
4738 bool FoundSrcOperand = false;
4739 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4740 MachineOperand &MO = MI->getOperand(i);
4743 unsigned Reg = MO.getReg();
4744 if (Reg != FoldAsLoadDefReg)
4746 // Do not fold if we have a subreg use or a def or multiple uses.
4747 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4751 FoundSrcOperand = true;
4753 if (!FoundSrcOperand)
4756 // Check whether we can fold the def into SrcOperandId.
4757 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
4759 FoldAsLoadDefReg = 0;
4766 /// Expand a single-def pseudo instruction to a two-addr
4767 /// instruction with two undef reads of the register being defined.
4768 /// This is used for mapping:
4771 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4773 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4774 const MCInstrDesc &Desc) {
4775 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4776 unsigned Reg = MIB->getOperand(0).getReg();
4779 // MachineInstr::addOperand() will insert explicit operands before any
4780 // implicit operands.
4781 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4782 // But we don't trust that.
4783 assert(MIB->getOperand(1).getReg() == Reg &&
4784 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4788 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4789 // code sequence is needed for other targets.
4790 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4791 const TargetInstrInfo &TII) {
4792 MachineBasicBlock &MBB = *MIB->getParent();
4793 DebugLoc DL = MIB->getDebugLoc();
4794 unsigned Reg = MIB->getOperand(0).getReg();
4795 const GlobalValue *GV =
4796 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4797 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4798 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4799 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
4800 MachineBasicBlock::iterator I = MIB.getInstr();
4802 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4803 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4804 .addMemOperand(MMO);
4805 MIB->setDebugLoc(DL);
4806 MIB->setDesc(TII.get(X86::MOV64rm));
4807 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4810 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4811 bool HasAVX = Subtarget.hasAVX();
4812 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4813 switch (MI->getOpcode()) {
4815 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4817 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4818 case X86::SETB_C16r:
4819 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4820 case X86::SETB_C32r:
4821 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4822 case X86::SETB_C64r:
4823 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4827 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4829 assert(HasAVX && "AVX not supported");
4830 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4831 case X86::AVX512_512_SET0:
4832 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4833 case X86::V_SETALLONES:
4834 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4835 case X86::AVX2_SETALLONES:
4836 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4837 case X86::TEST8ri_NOREX:
4838 MI->setDesc(get(X86::TEST8ri));
4841 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4842 case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr));
4843 case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr));
4845 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4846 case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr));
4847 case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr));
4848 case TargetOpcode::LOAD_STACK_GUARD:
4849 expandLoadStackGuard(MIB, *this);
4855 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs) {
4856 unsigned NumAddrOps = MOs.size();
4857 for (unsigned i = 0; i != NumAddrOps; ++i)
4858 MIB.addOperand(MOs[i]);
4859 if (NumAddrOps < 4) // FrameIndex only
4863 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4864 ArrayRef<MachineOperand> MOs,
4865 MachineBasicBlock::iterator InsertPt,
4867 const TargetInstrInfo &TII) {
4868 // Create the base instruction with the memory operand as the first part.
4869 // Omit the implicit operands, something BuildMI can't do.
4870 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4871 MI->getDebugLoc(), true);
4872 MachineInstrBuilder MIB(MF, NewMI);
4873 addOperands(MIB, MOs);
4875 // Loop over the rest of the ri operands, converting them over.
4876 unsigned NumOps = MI->getDesc().getNumOperands()-2;
4877 for (unsigned i = 0; i != NumOps; ++i) {
4878 MachineOperand &MO = MI->getOperand(i+2);
4881 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4882 MachineOperand &MO = MI->getOperand(i);
4886 MachineBasicBlock *MBB = InsertPt->getParent();
4887 MBB->insert(InsertPt, NewMI);
4892 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4893 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4894 MachineBasicBlock::iterator InsertPt,
4895 MachineInstr *MI, const TargetInstrInfo &TII) {
4896 // Omit the implicit operands, something BuildMI can't do.
4897 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4898 MI->getDebugLoc(), true);
4899 MachineInstrBuilder MIB(MF, NewMI);
4901 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4902 MachineOperand &MO = MI->getOperand(i);
4904 assert(MO.isReg() && "Expected to fold into reg operand!");
4905 addOperands(MIB, MOs);
4911 MachineBasicBlock *MBB = InsertPt->getParent();
4912 MBB->insert(InsertPt, NewMI);
4917 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4918 ArrayRef<MachineOperand> MOs,
4919 MachineBasicBlock::iterator InsertPt,
4921 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4922 MI->getDebugLoc(), TII.get(Opcode));
4923 addOperands(MIB, MOs);
4924 return MIB.addImm(0);
4927 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4928 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
4929 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4930 unsigned Size, unsigned Align, bool AllowCommute) const {
4931 const DenseMap<unsigned,
4932 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4933 bool isCallRegIndirect = Subtarget.callRegIndirect();
4934 bool isTwoAddrFold = false;
4936 // For CPUs that favor the register form of a call or push,
4937 // do not fold loads into calls or pushes, unless optimizing for size
4939 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
4940 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
4941 MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
4942 MI->getOpcode() == X86::PUSH64r))
4945 unsigned NumOps = MI->getDesc().getNumOperands();
4946 bool isTwoAddr = NumOps > 1 &&
4947 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4949 // FIXME: AsmPrinter doesn't know how to handle
4950 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4951 if (MI->getOpcode() == X86::ADD32ri &&
4952 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4955 MachineInstr *NewMI = nullptr;
4956 // Folding a memory location into the two-address part of a two-address
4957 // instruction is different than folding it other places. It requires
4958 // replacing the *two* registers with the memory location.
4959 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
4960 MI->getOperand(0).isReg() &&
4961 MI->getOperand(1).isReg() &&
4962 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4963 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4964 isTwoAddrFold = true;
4965 } else if (OpNum == 0) {
4966 if (MI->getOpcode() == X86::MOV32r0) {
4967 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4972 OpcodeTablePtr = &RegOp2MemOpTable0;
4973 } else if (OpNum == 1) {
4974 OpcodeTablePtr = &RegOp2MemOpTable1;
4975 } else if (OpNum == 2) {
4976 OpcodeTablePtr = &RegOp2MemOpTable2;
4977 } else if (OpNum == 3) {
4978 OpcodeTablePtr = &RegOp2MemOpTable3;
4979 } else if (OpNum == 4) {
4980 OpcodeTablePtr = &RegOp2MemOpTable4;
4983 // If table selected...
4984 if (OpcodeTablePtr) {
4985 // Find the Opcode to fuse
4986 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4987 OpcodeTablePtr->find(MI->getOpcode());
4988 if (I != OpcodeTablePtr->end()) {
4989 unsigned Opcode = I->second.first;
4990 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4991 if (Align < MinAlign)
4993 bool NarrowToMOV32rm = false;
4995 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
4996 if (Size < RCSize) {
4997 // Check if it's safe to fold the load. If the size of the object is
4998 // narrower than the load width, then it's not.
4999 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5001 // If this is a 64-bit load, but the spill slot is 32, then we can do
5002 // a 32-bit load which is implicitly zero-extended. This likely is
5003 // due to live interval analysis remat'ing a load from stack slot.
5004 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5006 Opcode = X86::MOV32rm;
5007 NarrowToMOV32rm = true;
5012 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5014 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5016 if (NarrowToMOV32rm) {
5017 // If this is the special case where we use a MOV32rm to load a 32-bit
5018 // value and zero-extend the top bits. Change the destination register
5020 unsigned DstReg = NewMI->getOperand(0).getReg();
5021 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5022 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5024 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5030 // If the instruction and target operand are commutable, commute the
5031 // instruction and try again.
5033 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5034 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5035 bool HasDef = MI->getDesc().getNumDefs();
5036 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5037 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5038 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5040 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5042 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5044 // If either of the commutable operands are tied to the destination
5045 // then we can not commute + fold.
5046 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5047 (HasDef && Reg0 == Reg2 && Tied2))
5050 MachineInstr *CommutedMI =
5051 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5053 // Unable to commute.
5056 if (CommutedMI != MI) {
5057 // New instruction. We can't fold from this.
5058 CommutedMI->eraseFromParent();
5062 // Attempt to fold with the commuted version of the instruction.
5063 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5064 Size, Align, /*AllowCommute=*/false);
5068 // Folding failed again - undo the commute before returning.
5069 MachineInstr *UncommutedMI =
5070 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5071 if (!UncommutedMI) {
5072 // Unable to commute.
5075 if (UncommutedMI != MI) {
5076 // New instruction. It doesn't need to be kept.
5077 UncommutedMI->eraseFromParent();
5081 // Return here to prevent duplicate fuse failure report.
5087 if (PrintFailedFusing && !MI->isCopy())
5088 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5092 /// Return true for all instructions that only update
5093 /// the first 32 or 64-bits of the destination register and leave the rest
5094 /// unmodified. This can be used to avoid folding loads if the instructions
5095 /// only update part of the destination register, and the non-updated part is
5096 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5097 /// instructions breaks the partial register dependency and it can improve
5098 /// performance. e.g.:
5100 /// movss (%rdi), %xmm0
5101 /// cvtss2sd %xmm0, %xmm0
5104 /// cvtss2sd (%rdi), %xmm0
5106 /// FIXME: This should be turned into a TSFlags.
5108 static bool hasPartialRegUpdate(unsigned Opcode) {
5110 case X86::CVTSI2SSrr:
5111 case X86::CVTSI2SSrm:
5112 case X86::CVTSI2SS64rr:
5113 case X86::CVTSI2SS64rm:
5114 case X86::CVTSI2SDrr:
5115 case X86::CVTSI2SDrm:
5116 case X86::CVTSI2SD64rr:
5117 case X86::CVTSI2SD64rm:
5118 case X86::CVTSD2SSrr:
5119 case X86::CVTSD2SSrm:
5120 case X86::Int_CVTSD2SSrr:
5121 case X86::Int_CVTSD2SSrm:
5122 case X86::CVTSS2SDrr:
5123 case X86::CVTSS2SDrm:
5124 case X86::Int_CVTSS2SDrr:
5125 case X86::Int_CVTSS2SDrm:
5128 case X86::RCPSSr_Int:
5129 case X86::RCPSSm_Int:
5132 case X86::ROUNDSDr_Int:
5135 case X86::ROUNDSSr_Int:
5138 case X86::RSQRTSSr_Int:
5139 case X86::RSQRTSSm_Int:
5142 case X86::SQRTSSr_Int:
5143 case X86::SQRTSSm_Int:
5146 case X86::SQRTSDr_Int:
5147 case X86::SQRTSDm_Int:
5154 /// Inform the ExeDepsFix pass how many idle
5155 /// instructions we would like before a partial register update.
5156 unsigned X86InstrInfo::
5157 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5158 const TargetRegisterInfo *TRI) const {
5159 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5162 // If MI is marked as reading Reg, the partial register update is wanted.
5163 const MachineOperand &MO = MI->getOperand(0);
5164 unsigned Reg = MO.getReg();
5165 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5166 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5169 if (MI->readsRegister(Reg, TRI))
5173 // If any of the preceding 16 instructions are reading Reg, insert a
5174 // dependency breaking instruction. The magic number is based on a few
5175 // Nehalem experiments.
5179 // Return true for any instruction the copies the high bits of the first source
5180 // operand into the unused high bits of the destination operand.
5181 static bool hasUndefRegUpdate(unsigned Opcode) {
5183 case X86::VCVTSI2SSrr:
5184 case X86::VCVTSI2SSrm:
5185 case X86::Int_VCVTSI2SSrr:
5186 case X86::Int_VCVTSI2SSrm:
5187 case X86::VCVTSI2SS64rr:
5188 case X86::VCVTSI2SS64rm:
5189 case X86::Int_VCVTSI2SS64rr:
5190 case X86::Int_VCVTSI2SS64rm:
5191 case X86::VCVTSI2SDrr:
5192 case X86::VCVTSI2SDrm:
5193 case X86::Int_VCVTSI2SDrr:
5194 case X86::Int_VCVTSI2SDrm:
5195 case X86::VCVTSI2SD64rr:
5196 case X86::VCVTSI2SD64rm:
5197 case X86::Int_VCVTSI2SD64rr:
5198 case X86::Int_VCVTSI2SD64rm:
5199 case X86::VCVTSD2SSrr:
5200 case X86::VCVTSD2SSrm:
5201 case X86::Int_VCVTSD2SSrr:
5202 case X86::Int_VCVTSD2SSrm:
5203 case X86::VCVTSS2SDrr:
5204 case X86::VCVTSS2SDrm:
5205 case X86::Int_VCVTSS2SDrr:
5206 case X86::Int_VCVTSS2SDrm:
5209 case X86::VRCPSSm_Int:
5210 case X86::VROUNDSDr:
5211 case X86::VROUNDSDm:
5212 case X86::VROUNDSDr_Int:
5213 case X86::VROUNDSSr:
5214 case X86::VROUNDSSm:
5215 case X86::VROUNDSSr_Int:
5216 case X86::VRSQRTSSr:
5217 case X86::VRSQRTSSm:
5218 case X86::VRSQRTSSm_Int:
5221 case X86::VSQRTSSm_Int:
5224 case X86::VSQRTSDm_Int:
5226 case X86::VCVTSD2SSZrr:
5227 case X86::VCVTSD2SSZrm:
5228 case X86::VCVTSS2SDZrr:
5229 case X86::VCVTSS2SDZrm:
5236 /// Inform the ExeDepsFix pass how many idle instructions we would like before
5237 /// certain undef register reads.
5239 /// This catches the VCVTSI2SD family of instructions:
5241 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5243 /// We should to be careful *not* to catch VXOR idioms which are presumably
5244 /// handled specially in the pipeline:
5246 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5248 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5249 /// high bits that are passed-through are not live.
5250 unsigned X86InstrInfo::
5251 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5252 const TargetRegisterInfo *TRI) const {
5253 if (!hasUndefRegUpdate(MI->getOpcode()))
5256 // Set the OpNum parameter to the first source operand.
5259 const MachineOperand &MO = MI->getOperand(OpNum);
5260 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5261 // Use the same magic number as getPartialRegUpdateClearance.
5268 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5269 const TargetRegisterInfo *TRI) const {
5270 unsigned Reg = MI->getOperand(OpNum).getReg();
5271 // If MI kills this register, the false dependence is already broken.
5272 if (MI->killsRegister(Reg, TRI))
5274 if (X86::VR128RegClass.contains(Reg)) {
5275 // These instructions are all floating point domain, so xorps is the best
5277 bool HasAVX = Subtarget.hasAVX();
5278 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5279 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5280 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5281 } else if (X86::VR256RegClass.contains(Reg)) {
5282 // Use vxorps to clear the full ymm register.
5283 // It wants to read and write the xmm sub-register.
5284 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5285 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5286 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5287 .addReg(Reg, RegState::ImplicitDefine);
5290 MI->addRegisterKilled(Reg, TRI, true);
5293 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5294 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5295 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
5296 // Check switch flag
5297 if (NoFusing) return nullptr;
5299 // Unless optimizing for size, don't fold to avoid partial
5300 // register update stalls
5301 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
5304 const MachineFrameInfo *MFI = MF.getFrameInfo();
5305 unsigned Size = MFI->getObjectSize(FrameIndex);
5306 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5307 // If the function stack isn't realigned we don't want to fold instructions
5308 // that need increased alignment.
5309 if (!RI.needsStackRealignment(MF))
5311 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5312 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5313 unsigned NewOpc = 0;
5314 unsigned RCSize = 0;
5315 switch (MI->getOpcode()) {
5316 default: return nullptr;
5317 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5318 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5319 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5320 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5322 // Check if it's safe to fold the load. If the size of the object is
5323 // narrower than the load width, then it's not.
5326 // Change to CMPXXri r, 0 first.
5327 MI->setDesc(get(NewOpc));
5328 MI->getOperand(1).ChangeToImmediate(0);
5329 } else if (Ops.size() != 1)
5332 return foldMemoryOperandImpl(MF, MI, Ops[0],
5333 MachineOperand::CreateFI(FrameIndex), InsertPt,
5334 Size, Alignment, /*AllowCommute=*/true);
5337 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5338 /// because the latter uses contents that wouldn't be defined in the folded
5339 /// version. For instance, this transformation isn't legal:
5340 /// movss (%rdi), %xmm0
5341 /// addps %xmm0, %xmm0
5343 /// addps (%rdi), %xmm0
5345 /// But this one is:
5346 /// movss (%rdi), %xmm0
5347 /// addss %xmm0, %xmm0
5349 /// addss (%rdi), %xmm0
5351 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5352 const MachineInstr &UserMI,
5353 const MachineFunction &MF) {
5354 unsigned Opc = LoadMI.getOpcode();
5355 unsigned UserOpc = UserMI.getOpcode();
5357 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5359 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
5360 // These instructions only load 32 bits, we can't fold them if the
5361 // destination register is wider than 32 bits (4 bytes), and its user
5362 // instruction isn't scalar (SS).
5364 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
5365 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
5366 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
5367 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
5374 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
5375 // These instructions only load 64 bits, we can't fold them if the
5376 // destination register is wider than 64 bits (8 bytes), and its user
5377 // instruction isn't scalar (SD).
5379 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
5380 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
5381 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
5382 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
5392 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5393 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5394 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
5395 // If loading from a FrameIndex, fold directly from the FrameIndex.
5396 unsigned NumOps = LoadMI->getDesc().getNumOperands();
5398 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5399 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
5401 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
5404 // Check switch flag
5405 if (NoFusing) return nullptr;
5407 // Avoid partial register update stalls unless optimizing for size.
5408 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
5411 // Determine the alignment of the load.
5412 unsigned Alignment = 0;
5413 if (LoadMI->hasOneMemOperand())
5414 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
5416 switch (LoadMI->getOpcode()) {
5417 case X86::AVX2_SETALLONES:
5422 case X86::V_SETALLONES:
5434 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5435 unsigned NewOpc = 0;
5436 switch (MI->getOpcode()) {
5437 default: return nullptr;
5438 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5439 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5440 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5441 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5443 // Change to CMPXXri r, 0 first.
5444 MI->setDesc(get(NewOpc));
5445 MI->getOperand(1).ChangeToImmediate(0);
5446 } else if (Ops.size() != 1)
5449 // Make sure the subregisters match.
5450 // Otherwise we risk changing the size of the load.
5451 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
5454 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5455 switch (LoadMI->getOpcode()) {
5457 case X86::V_SETALLONES:
5458 case X86::AVX2_SETALLONES:
5461 case X86::FsFLD0SS: {
5462 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5463 // Create a constant-pool entry and operands to load from it.
5465 // Medium and large mode can't fold loads this way.
5466 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5467 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5470 // x86-32 PIC requires a PIC base register for constant pools.
5471 unsigned PICBase = 0;
5472 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5473 if (Subtarget.is64Bit())
5476 // FIXME: PICBase = getGlobalBaseReg(&MF);
5477 // This doesn't work for several reasons.
5478 // 1. GlobalBaseReg may have been spilled.
5479 // 2. It may not be live at MI.
5483 // Create a constant-pool entry.
5484 MachineConstantPool &MCP = *MF.getConstantPool();
5486 unsigned Opc = LoadMI->getOpcode();
5487 if (Opc == X86::FsFLD0SS)
5488 Ty = Type::getFloatTy(MF.getFunction()->getContext());
5489 else if (Opc == X86::FsFLD0SD)
5490 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
5491 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5492 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
5494 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
5496 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5497 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5498 Constant::getNullValue(Ty);
5499 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5501 // Create operands to load from the constant pool entry.
5502 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5503 MOs.push_back(MachineOperand::CreateImm(1));
5504 MOs.push_back(MachineOperand::CreateReg(0, false));
5505 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5506 MOs.push_back(MachineOperand::CreateReg(0, false));
5510 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
5513 // Folding a normal load. Just copy the load's address operands.
5514 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
5515 LoadMI->operands_begin() + NumOps);
5519 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5520 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5523 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5524 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
5525 SmallVectorImpl<MachineInstr*> &NewMIs) const {
5526 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5527 MemOp2RegOpTable.find(MI->getOpcode());
5528 if (I == MemOp2RegOpTable.end())
5530 unsigned Opc = I->second.first;
5531 unsigned Index = I->second.second & TB_INDEX_MASK;
5532 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5533 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5534 if (UnfoldLoad && !FoldedLoad)
5536 UnfoldLoad &= FoldedLoad;
5537 if (UnfoldStore && !FoldedStore)
5539 UnfoldStore &= FoldedStore;
5541 const MCInstrDesc &MCID = get(Opc);
5542 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5543 // TODO: Check if 32-byte or greater accesses are slow too?
5544 if (!MI->hasOneMemOperand() &&
5545 RC == &X86::VR128RegClass &&
5546 Subtarget.isUnalignedMem16Slow())
5547 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5548 // conservatively assume the address is unaligned. That's bad for
5551 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5552 SmallVector<MachineOperand,2> BeforeOps;
5553 SmallVector<MachineOperand,2> AfterOps;
5554 SmallVector<MachineOperand,4> ImpOps;
5555 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5556 MachineOperand &Op = MI->getOperand(i);
5557 if (i >= Index && i < Index + X86::AddrNumOperands)
5558 AddrOps.push_back(Op);
5559 else if (Op.isReg() && Op.isImplicit())
5560 ImpOps.push_back(Op);
5562 BeforeOps.push_back(Op);
5564 AfterOps.push_back(Op);
5567 // Emit the load instruction.
5569 std::pair<MachineInstr::mmo_iterator,
5570 MachineInstr::mmo_iterator> MMOs =
5571 MF.extractLoadMemRefs(MI->memoperands_begin(),
5572 MI->memoperands_end());
5573 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5575 // Address operands cannot be marked isKill.
5576 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5577 MachineOperand &MO = NewMIs[0]->getOperand(i);
5579 MO.setIsKill(false);
5584 // Emit the data processing instruction.
5585 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5586 MachineInstrBuilder MIB(MF, DataMI);
5589 MIB.addReg(Reg, RegState::Define);
5590 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5591 MIB.addOperand(BeforeOps[i]);
5594 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5595 MIB.addOperand(AfterOps[i]);
5596 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5597 MachineOperand &MO = ImpOps[i];
5598 MIB.addReg(MO.getReg(),
5599 getDefRegState(MO.isDef()) |
5600 RegState::Implicit |
5601 getKillRegState(MO.isKill()) |
5602 getDeadRegState(MO.isDead()) |
5603 getUndefRegState(MO.isUndef()));
5605 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5606 switch (DataMI->getOpcode()) {
5608 case X86::CMP64ri32:
5615 MachineOperand &MO0 = DataMI->getOperand(0);
5616 MachineOperand &MO1 = DataMI->getOperand(1);
5617 if (MO1.getImm() == 0) {
5619 switch (DataMI->getOpcode()) {
5620 default: llvm_unreachable("Unreachable!");
5622 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5624 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5626 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5627 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5629 DataMI->setDesc(get(NewOpc));
5630 MO1.ChangeToRegister(MO0.getReg(), false);
5634 NewMIs.push_back(DataMI);
5636 // Emit the store instruction.
5638 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5639 std::pair<MachineInstr::mmo_iterator,
5640 MachineInstr::mmo_iterator> MMOs =
5641 MF.extractStoreMemRefs(MI->memoperands_begin(),
5642 MI->memoperands_end());
5643 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5650 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5651 SmallVectorImpl<SDNode*> &NewNodes) const {
5652 if (!N->isMachineOpcode())
5655 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5656 MemOp2RegOpTable.find(N->getMachineOpcode());
5657 if (I == MemOp2RegOpTable.end())
5659 unsigned Opc = I->second.first;
5660 unsigned Index = I->second.second & TB_INDEX_MASK;
5661 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5662 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5663 const MCInstrDesc &MCID = get(Opc);
5664 MachineFunction &MF = DAG.getMachineFunction();
5665 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5666 unsigned NumDefs = MCID.NumDefs;
5667 std::vector<SDValue> AddrOps;
5668 std::vector<SDValue> BeforeOps;
5669 std::vector<SDValue> AfterOps;
5671 unsigned NumOps = N->getNumOperands();
5672 for (unsigned i = 0; i != NumOps-1; ++i) {
5673 SDValue Op = N->getOperand(i);
5674 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5675 AddrOps.push_back(Op);
5676 else if (i < Index-NumDefs)
5677 BeforeOps.push_back(Op);
5678 else if (i > Index-NumDefs)
5679 AfterOps.push_back(Op);
5681 SDValue Chain = N->getOperand(NumOps-1);
5682 AddrOps.push_back(Chain);
5684 // Emit the load instruction.
5685 SDNode *Load = nullptr;
5687 EVT VT = *RC->vt_begin();
5688 std::pair<MachineInstr::mmo_iterator,
5689 MachineInstr::mmo_iterator> MMOs =
5690 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5691 cast<MachineSDNode>(N)->memoperands_end());
5692 if (!(*MMOs.first) &&
5693 RC == &X86::VR128RegClass &&
5694 Subtarget.isUnalignedMem16Slow())
5695 // Do not introduce a slow unaligned load.
5697 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5698 // memory access is slow above.
5699 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5700 bool isAligned = (*MMOs.first) &&
5701 (*MMOs.first)->getAlignment() >= Alignment;
5702 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5703 VT, MVT::Other, AddrOps);
5704 NewNodes.push_back(Load);
5706 // Preserve memory reference information.
5707 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5710 // Emit the data processing instruction.
5711 std::vector<EVT> VTs;
5712 const TargetRegisterClass *DstRC = nullptr;
5713 if (MCID.getNumDefs() > 0) {
5714 DstRC = getRegClass(MCID, 0, &RI, MF);
5715 VTs.push_back(*DstRC->vt_begin());
5717 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5718 EVT VT = N->getValueType(i);
5719 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5723 BeforeOps.push_back(SDValue(Load, 0));
5724 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5725 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5726 NewNodes.push_back(NewNode);
5728 // Emit the store instruction.
5731 AddrOps.push_back(SDValue(NewNode, 0));
5732 AddrOps.push_back(Chain);
5733 std::pair<MachineInstr::mmo_iterator,
5734 MachineInstr::mmo_iterator> MMOs =
5735 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5736 cast<MachineSDNode>(N)->memoperands_end());
5737 if (!(*MMOs.first) &&
5738 RC == &X86::VR128RegClass &&
5739 Subtarget.isUnalignedMem16Slow())
5740 // Do not introduce a slow unaligned store.
5742 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5743 // memory access is slow above.
5744 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5745 bool isAligned = (*MMOs.first) &&
5746 (*MMOs.first)->getAlignment() >= Alignment;
5748 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5749 dl, MVT::Other, AddrOps);
5750 NewNodes.push_back(Store);
5752 // Preserve memory reference information.
5753 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
5759 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5760 bool UnfoldLoad, bool UnfoldStore,
5761 unsigned *LoadRegIndex) const {
5762 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5763 MemOp2RegOpTable.find(Opc);
5764 if (I == MemOp2RegOpTable.end())
5766 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5767 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5768 if (UnfoldLoad && !FoldedLoad)
5770 if (UnfoldStore && !FoldedStore)
5773 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5774 return I->second.first;
5778 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5779 int64_t &Offset1, int64_t &Offset2) const {
5780 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5782 unsigned Opc1 = Load1->getMachineOpcode();
5783 unsigned Opc2 = Load2->getMachineOpcode();
5785 default: return false;
5795 case X86::MMX_MOVD64rm:
5796 case X86::MMX_MOVQ64rm:
5797 case X86::FsMOVAPSrm:
5798 case X86::FsMOVAPDrm:
5804 // AVX load instructions
5807 case X86::FsVMOVAPSrm:
5808 case X86::FsVMOVAPDrm:
5809 case X86::VMOVAPSrm:
5810 case X86::VMOVUPSrm:
5811 case X86::VMOVAPDrm:
5812 case X86::VMOVDQArm:
5813 case X86::VMOVDQUrm:
5814 case X86::VMOVAPSYrm:
5815 case X86::VMOVUPSYrm:
5816 case X86::VMOVAPDYrm:
5817 case X86::VMOVDQAYrm:
5818 case X86::VMOVDQUYrm:
5822 default: return false;
5832 case X86::MMX_MOVD64rm:
5833 case X86::MMX_MOVQ64rm:
5834 case X86::FsMOVAPSrm:
5835 case X86::FsMOVAPDrm:
5841 // AVX load instructions
5844 case X86::FsVMOVAPSrm:
5845 case X86::FsVMOVAPDrm:
5846 case X86::VMOVAPSrm:
5847 case X86::VMOVUPSrm:
5848 case X86::VMOVAPDrm:
5849 case X86::VMOVDQArm:
5850 case X86::VMOVDQUrm:
5851 case X86::VMOVAPSYrm:
5852 case X86::VMOVUPSYrm:
5853 case X86::VMOVAPDYrm:
5854 case X86::VMOVDQAYrm:
5855 case X86::VMOVDQUYrm:
5859 // Check if chain operands and base addresses match.
5860 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5861 Load1->getOperand(5) != Load2->getOperand(5))
5863 // Segment operands should match as well.
5864 if (Load1->getOperand(4) != Load2->getOperand(4))
5866 // Scale should be 1, Index should be Reg0.
5867 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5868 Load1->getOperand(2) == Load2->getOperand(2)) {
5869 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5872 // Now let's examine the displacements.
5873 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5874 isa<ConstantSDNode>(Load2->getOperand(3))) {
5875 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5876 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5883 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5884 int64_t Offset1, int64_t Offset2,
5885 unsigned NumLoads) const {
5886 assert(Offset2 > Offset1);
5887 if ((Offset2 - Offset1) / 8 > 64)
5890 unsigned Opc1 = Load1->getMachineOpcode();
5891 unsigned Opc2 = Load2->getMachineOpcode();
5893 return false; // FIXME: overly conservative?
5900 case X86::MMX_MOVD64rm:
5901 case X86::MMX_MOVQ64rm:
5905 EVT VT = Load1->getValueType(0);
5906 switch (VT.getSimpleVT().SimpleTy) {
5908 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5909 // have 16 of them to play with.
5910 if (Subtarget.is64Bit()) {
5913 } else if (NumLoads) {
5931 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5932 MachineInstr *Second) const {
5933 // Check if this processor supports macro-fusion. Since this is a minor
5934 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5935 // proxy for SandyBridge+.
5936 if (!Subtarget.hasAVX())
5945 switch(Second->getOpcode()) {
5968 FuseKind = FuseTest;
5971 switch (First->getOpcode()) {
5981 case X86::TEST32i32:
5982 case X86::TEST64i32:
5983 case X86::TEST64ri32:
5988 case X86::TEST8ri_NOREX:
6000 case X86::AND64ri32:
6020 case X86::CMP64ri32:
6031 case X86::ADD16ri8_DB:
6032 case X86::ADD16ri_DB:
6035 case X86::ADD16rr_DB:
6039 case X86::ADD32ri8_DB:
6040 case X86::ADD32ri_DB:
6043 case X86::ADD32rr_DB:
6045 case X86::ADD64ri32:
6046 case X86::ADD64ri32_DB:
6048 case X86::ADD64ri8_DB:
6051 case X86::ADD64rr_DB:
6069 case X86::SUB64ri32:
6077 return FuseKind == FuseCmp || FuseKind == FuseInc;
6086 return FuseKind == FuseInc;
6091 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6092 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6093 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6094 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
6096 Cond[0].setImm(GetOppositeBranchCondition(CC));
6101 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6102 // FIXME: Return false for x87 stack register classes for now. We can't
6103 // allow any loads of these registers before FpGet_ST0_80.
6104 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6105 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6108 /// Return a virtual register initialized with the
6109 /// the global base register value. Output instructions required to
6110 /// initialize the register in the function entry block, if necessary.
6112 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6114 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6115 assert(!Subtarget.is64Bit() &&
6116 "X86-64 PIC uses RIP relative addressing");
6118 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6119 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6120 if (GlobalBaseReg != 0)
6121 return GlobalBaseReg;
6123 // Create the register. The code to initialize it is inserted
6124 // later, by the CGBR pass (below).
6125 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6126 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6127 X86FI->setGlobalBaseReg(GlobalBaseReg);
6128 return GlobalBaseReg;
6131 // These are the replaceable SSE instructions. Some of these have Int variants
6132 // that we don't include here. We don't want to replace instructions selected
6134 static const uint16_t ReplaceableInstrs[][3] = {
6135 //PackedSingle PackedDouble PackedInt
6136 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6137 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6138 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6139 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6140 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
6141 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
6142 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6143 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6144 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6145 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6146 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6147 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6148 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6149 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6150 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
6151 // AVX 128-bit support
6152 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6153 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6154 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6155 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6156 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
6157 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
6158 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6159 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6160 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6161 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6162 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6163 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6164 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
6165 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6166 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
6167 // AVX 256-bit support
6168 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6169 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6170 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6171 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6172 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
6173 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6176 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6177 //PackedSingle PackedDouble PackedInt
6178 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6179 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6180 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6181 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6182 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6183 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6184 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6185 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6186 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6187 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6188 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6189 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6190 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6191 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6192 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6193 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6194 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6195 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6196 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6197 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6200 // FIXME: Some shuffle and unpack instructions have equivalents in different
6201 // domains, but they require a bit more work than just switching opcodes.
6203 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6204 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
6205 if (ReplaceableInstrs[i][domain-1] == opcode)
6206 return ReplaceableInstrs[i];
6210 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6211 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6212 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6213 return ReplaceableInstrsAVX2[i];
6217 std::pair<uint16_t, uint16_t>
6218 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6219 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6220 bool hasAVX2 = Subtarget.hasAVX2();
6221 uint16_t validDomains = 0;
6222 if (domain && lookup(MI->getOpcode(), domain))
6224 else if (domain && lookupAVX2(MI->getOpcode(), domain))
6225 validDomains = hasAVX2 ? 0xe : 0x6;
6226 return std::make_pair(domain, validDomains);
6229 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
6230 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6231 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6232 assert(dom && "Not an SSE instruction");
6233 const uint16_t *table = lookup(MI->getOpcode(), dom);
6234 if (!table) { // try the other table
6235 assert((Subtarget.hasAVX2() || Domain < 3) &&
6236 "256-bit vector operations only available in AVX2");
6237 table = lookupAVX2(MI->getOpcode(), dom);
6239 assert(table && "Cannot change domain");
6240 MI->setDesc(get(table[Domain-1]));
6243 /// Return the noop instruction to use for a noop.
6244 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6245 NopInst.setOpcode(X86::NOOP);
6248 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6249 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6250 // on the encoding lengths of the instructions generated by
6251 // getUnconditionalBranch and getTrap.
6252 void X86InstrInfo::getUnconditionalBranch(
6253 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6254 Branch.setOpcode(X86::JMP_1);
6255 Branch.addOperand(MCOperand::createExpr(BranchTarget));
6258 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6259 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6260 // on the encoding lengths of the instructions generated by
6261 // getUnconditionalBranch and getTrap.
6262 void X86InstrInfo::getTrap(MCInst &MI) const {
6263 MI.setOpcode(X86::TRAP);
6266 // See getTrap and getUnconditionalBranch for conditions on the value returned
6267 // by this function.
6268 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6269 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6270 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6274 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6276 default: return false;
6278 case X86::DIVSDrm_Int:
6280 case X86::DIVSDrr_Int:
6282 case X86::DIVSSrm_Int:
6284 case X86::DIVSSrr_Int:
6290 case X86::SQRTSDm_Int:
6292 case X86::SQRTSDr_Int:
6294 case X86::SQRTSSm_Int:
6296 case X86::SQRTSSr_Int:
6297 // AVX instructions with high latency
6299 case X86::VDIVSDrm_Int:
6301 case X86::VDIVSDrr_Int:
6303 case X86::VDIVSSrm_Int:
6305 case X86::VDIVSSrr_Int:
6311 case X86::VSQRTSDm_Int:
6314 case X86::VSQRTSSm_Int:
6316 case X86::VSQRTPDZm:
6317 case X86::VSQRTPDZr:
6318 case X86::VSQRTPSZm:
6319 case X86::VSQRTPSZr:
6320 case X86::VSQRTSDZm:
6321 case X86::VSQRTSDZm_Int:
6322 case X86::VSQRTSDZr:
6323 case X86::VSQRTSSZm_Int:
6324 case X86::VSQRTSSZr:
6325 case X86::VSQRTSSZm:
6326 case X86::VDIVSDZrm:
6327 case X86::VDIVSDZrr:
6328 case X86::VDIVSSZrm:
6329 case X86::VDIVSSZrr:
6331 case X86::VGATHERQPSZrm:
6332 case X86::VGATHERQPDZrm:
6333 case X86::VGATHERDPDZrm:
6334 case X86::VGATHERDPSZrm:
6335 case X86::VPGATHERQDZrm:
6336 case X86::VPGATHERQQZrm:
6337 case X86::VPGATHERDDZrm:
6338 case X86::VPGATHERDQZrm:
6339 case X86::VSCATTERQPDZmr:
6340 case X86::VSCATTERQPSZmr:
6341 case X86::VSCATTERDPDZmr:
6342 case X86::VSCATTERDPSZmr:
6343 case X86::VPSCATTERQDZmr:
6344 case X86::VPSCATTERQQZmr:
6345 case X86::VPSCATTERDDZmr:
6346 case X86::VPSCATTERDQZmr:
6352 hasHighOperandLatency(const TargetSchedModel &SchedModel,
6353 const MachineRegisterInfo *MRI,
6354 const MachineInstr *DefMI, unsigned DefIdx,
6355 const MachineInstr *UseMI, unsigned UseIdx) const {
6356 return isHighLatencyDef(DefMI->getOpcode());
6359 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6360 const MachineBasicBlock *MBB) const {
6361 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
6362 "Reassociation needs binary operators");
6364 // Integer binary math/logic instructions have a third source operand:
6365 // the EFLAGS register. That operand must be both defined here and never
6366 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
6367 // not change anything because rearranging the operands could affect other
6368 // instructions that depend on the exact status flags (zero, sign, etc.)
6369 // that are set by using these particular operands with this operation.
6370 if (Inst.getNumOperands() == 4) {
6371 assert(Inst.getOperand(3).isReg() &&
6372 Inst.getOperand(3).getReg() == X86::EFLAGS &&
6373 "Unexpected operand in reassociable instruction");
6374 if (!Inst.getOperand(3).isDead())
6378 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
6381 // TODO: There are many more machine instruction opcodes to match:
6382 // 1. Other data types (integer, vectors)
6383 // 2. Other math / logic operations (xor, or)
6384 // 3. Other forms of the same operation (intrinsics and other variants)
6385 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
6386 switch (Inst.getOpcode()) {
6411 // Normal min/max instructions are not commutative because of NaN and signed
6412 // zero semantics, but these are. Thus, there's no need to check for global
6413 // relaxed math; the instructions themselves have the properties we need.
6422 case X86::VMAXCPDrr:
6423 case X86::VMAXCPSrr:
6424 case X86::VMAXCPDYrr:
6425 case X86::VMAXCPSYrr:
6426 case X86::VMAXCSDrr:
6427 case X86::VMAXCSSrr:
6428 case X86::VMINCPDrr:
6429 case X86::VMINCPSrr:
6430 case X86::VMINCPDYrr:
6431 case X86::VMINCPSYrr:
6432 case X86::VMINCSDrr:
6433 case X86::VMINCSSrr:
6445 case X86::VADDPDYrr:
6446 case X86::VADDPSYrr:
6451 case X86::VMULPDYrr:
6452 case X86::VMULPSYrr:
6455 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
6461 /// This is an architecture-specific helper function of reassociateOps.
6462 /// Set special operand attributes for new instructions after reassociation.
6463 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
6464 MachineInstr &OldMI2,
6465 MachineInstr &NewMI1,
6466 MachineInstr &NewMI2) const {
6467 // Integer instructions define an implicit EFLAGS source register operand as
6468 // the third source (fourth total) operand.
6469 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
6472 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
6473 "Unexpected instruction type for reassociation");
6475 MachineOperand &OldOp1 = OldMI1.getOperand(3);
6476 MachineOperand &OldOp2 = OldMI2.getOperand(3);
6477 MachineOperand &NewOp1 = NewMI1.getOperand(3);
6478 MachineOperand &NewOp2 = NewMI2.getOperand(3);
6480 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
6481 "Must have dead EFLAGS operand in reassociable instruction");
6482 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
6483 "Must have dead EFLAGS operand in reassociable instruction");
6488 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
6489 "Unexpected operand in reassociable instruction");
6490 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
6491 "Unexpected operand in reassociable instruction");
6493 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
6494 // of this pass or other passes. The EFLAGS operands must be dead in these new
6495 // instructions because the EFLAGS operands in the original instructions must
6496 // be dead in order for reassociation to occur.
6501 std::pair<unsigned, unsigned>
6502 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
6503 return std::make_pair(TF, 0u);
6506 ArrayRef<std::pair<unsigned, const char *>>
6507 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
6508 using namespace X86II;
6509 static const std::pair<unsigned, const char *> TargetFlags[] = {
6510 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
6511 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
6512 {MO_GOT, "x86-got"},
6513 {MO_GOTOFF, "x86-gotoff"},
6514 {MO_GOTPCREL, "x86-gotpcrel"},
6515 {MO_PLT, "x86-plt"},
6516 {MO_TLSGD, "x86-tlsgd"},
6517 {MO_TLSLD, "x86-tlsld"},
6518 {MO_TLSLDM, "x86-tlsldm"},
6519 {MO_GOTTPOFF, "x86-gottpoff"},
6520 {MO_INDNTPOFF, "x86-indntpoff"},
6521 {MO_TPOFF, "x86-tpoff"},
6522 {MO_DTPOFF, "x86-dtpoff"},
6523 {MO_NTPOFF, "x86-ntpoff"},
6524 {MO_GOTNTPOFF, "x86-gotntpoff"},
6525 {MO_DLLIMPORT, "x86-dllimport"},
6526 {MO_DARWIN_STUB, "x86-darwin-stub"},
6527 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
6528 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
6529 {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
6530 {MO_TLVP, "x86-tlvp"},
6531 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
6532 {MO_SECREL, "x86-secrel"}};
6533 return makeArrayRef(TargetFlags);
6537 /// Create Global Base Reg pass. This initializes the PIC
6538 /// global base register for x86-32.
6539 struct CGBR : public MachineFunctionPass {
6541 CGBR() : MachineFunctionPass(ID) {}
6543 bool runOnMachineFunction(MachineFunction &MF) override {
6544 const X86TargetMachine *TM =
6545 static_cast<const X86TargetMachine *>(&MF.getTarget());
6546 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
6548 // Don't do anything if this is 64-bit as 64-bit PIC
6549 // uses RIP relative addressing.
6553 // Only emit a global base reg in PIC mode.
6554 if (TM->getRelocationModel() != Reloc::PIC_)
6557 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6558 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6560 // If we didn't need a GlobalBaseReg, don't insert code.
6561 if (GlobalBaseReg == 0)
6564 // Insert the set of GlobalBaseReg into the first MBB of the function
6565 MachineBasicBlock &FirstMBB = MF.front();
6566 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6567 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6568 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6569 const X86InstrInfo *TII = STI.getInstrInfo();
6572 if (STI.isPICStyleGOT())
6573 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
6577 // Operand of MovePCtoStack is completely ignored by asm printer. It's
6578 // only used in JIT code emission as displacement to pc.
6579 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6581 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6582 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
6583 if (STI.isPICStyleGOT()) {
6584 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6585 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6586 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6587 X86II::MO_GOT_ABSOLUTE_ADDRESS);
6593 const char *getPassName() const override {
6594 return "X86 PIC Global Base Reg Initialization";
6597 void getAnalysisUsage(AnalysisUsage &AU) const override {
6598 AU.setPreservesCFG();
6599 MachineFunctionPass::getAnalysisUsage(AU);
6606 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
6609 struct LDTLSCleanup : public MachineFunctionPass {
6611 LDTLSCleanup() : MachineFunctionPass(ID) {}
6613 bool runOnMachineFunction(MachineFunction &MF) override {
6614 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6615 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6616 // No point folding accesses if there isn't at least two.
6620 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6621 return VisitNode(DT->getRootNode(), 0);
6624 // Visit the dominator subtree rooted at Node in pre-order.
6625 // If TLSBaseAddrReg is non-null, then use that to replace any
6626 // TLS_base_addr instructions. Otherwise, create the register
6627 // when the first such instruction is seen, and then use it
6628 // as we encounter more instructions.
6629 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6630 MachineBasicBlock *BB = Node->getBlock();
6631 bool Changed = false;
6633 // Traverse the current block.
6634 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6636 switch (I->getOpcode()) {
6637 case X86::TLS_base_addr32:
6638 case X86::TLS_base_addr64:
6640 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6642 I = SetRegister(I, &TLSBaseAddrReg);
6650 // Visit the children of this block in the dominator tree.
6651 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6653 Changed |= VisitNode(*I, TLSBaseAddrReg);
6659 // Replace the TLS_base_addr instruction I with a copy from
6660 // TLSBaseAddrReg, returning the new instruction.
6661 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6662 unsigned TLSBaseAddrReg) {
6663 MachineFunction *MF = I->getParent()->getParent();
6664 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6665 const bool is64Bit = STI.is64Bit();
6666 const X86InstrInfo *TII = STI.getInstrInfo();
6668 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6669 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6670 TII->get(TargetOpcode::COPY),
6671 is64Bit ? X86::RAX : X86::EAX)
6672 .addReg(TLSBaseAddrReg);
6674 // Erase the TLS_base_addr instruction.
6675 I->eraseFromParent();
6680 // Create a virtal register in *TLSBaseAddrReg, and populate it by
6681 // inserting a copy instruction after I. Returns the new instruction.
6682 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6683 MachineFunction *MF = I->getParent()->getParent();
6684 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6685 const bool is64Bit = STI.is64Bit();
6686 const X86InstrInfo *TII = STI.getInstrInfo();
6688 // Create a virtual register for the TLS base address.
6689 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6690 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6691 ? &X86::GR64RegClass
6692 : &X86::GR32RegClass);
6694 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6695 MachineInstr *Next = I->getNextNode();
6696 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6697 TII->get(TargetOpcode::COPY),
6699 .addReg(is64Bit ? X86::RAX : X86::EAX);
6704 const char *getPassName() const override {
6705 return "Local Dynamic TLS Access Clean-up";
6708 void getAnalysisUsage(AnalysisUsage &AU) const override {
6709 AU.setPreservesCFG();
6710 AU.addRequired<MachineDominatorTree>();
6711 MachineFunctionPass::getAnalysisUsage(AU);
6716 char LDTLSCleanup::ID = 0;
6718 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }