1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
44 NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
57 // Select which memory operand is being unfolded.
58 // (stored in bits 0 - 7)
64 // Minimum alignment required for load/store.
65 // Used for RegOp->MemOp conversion.
66 // (stored in bits 8 - 15)
68 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
69 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
70 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
71 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
73 // Do not insert the reverse map (MemOp -> RegOp) into the table.
74 // This may be needed because there is a many -> one mapping.
75 TB_NO_REVERSE = 1 << 16,
77 // Do not insert the forward map (RegOp -> MemOp) into the table.
78 // This is needed for Native Client, which prohibits branch
79 // instructions from using a memory operand.
80 TB_NO_FORWARD = 1 << 17,
82 TB_FOLDED_LOAD = 1 << 18,
83 TB_FOLDED_STORE = 1 << 19
86 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
87 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
88 ? X86::ADJCALLSTACKDOWN64
89 : X86::ADJCALLSTACKDOWN32),
90 (tm.getSubtarget<X86Subtarget>().is64Bit()
91 ? X86::ADJCALLSTACKUP64
92 : X86::ADJCALLSTACKUP32)),
93 TM(tm), RI(tm, *this) {
95 static const unsigned OpTbl2Addr[][3] = {
96 { X86::ADC32ri, X86::ADC32mi, 0 },
97 { X86::ADC32ri8, X86::ADC32mi8, 0 },
98 { X86::ADC32rr, X86::ADC32mr, 0 },
99 { X86::ADC64ri32, X86::ADC64mi32, 0 },
100 { X86::ADC64ri8, X86::ADC64mi8, 0 },
101 { X86::ADC64rr, X86::ADC64mr, 0 },
102 { X86::ADD16ri, X86::ADD16mi, 0 },
103 { X86::ADD16ri8, X86::ADD16mi8, 0 },
104 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
105 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
106 { X86::ADD16rr, X86::ADD16mr, 0 },
107 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
108 { X86::ADD32ri, X86::ADD32mi, 0 },
109 { X86::ADD32ri8, X86::ADD32mi8, 0 },
110 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
111 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
112 { X86::ADD32rr, X86::ADD32mr, 0 },
113 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
114 { X86::ADD64ri32, X86::ADD64mi32, 0 },
115 { X86::ADD64ri8, X86::ADD64mi8, 0 },
116 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
117 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
118 { X86::ADD64rr, X86::ADD64mr, 0 },
119 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
120 { X86::ADD8ri, X86::ADD8mi, 0 },
121 { X86::ADD8rr, X86::ADD8mr, 0 },
122 { X86::AND16ri, X86::AND16mi, 0 },
123 { X86::AND16ri8, X86::AND16mi8, 0 },
124 { X86::AND16rr, X86::AND16mr, 0 },
125 { X86::AND32ri, X86::AND32mi, 0 },
126 { X86::AND32ri8, X86::AND32mi8, 0 },
127 { X86::AND32rr, X86::AND32mr, 0 },
128 { X86::AND64ri32, X86::AND64mi32, 0 },
129 { X86::AND64ri8, X86::AND64mi8, 0 },
130 { X86::AND64rr, X86::AND64mr, 0 },
131 { X86::AND8ri, X86::AND8mi, 0 },
132 { X86::AND8rr, X86::AND8mr, 0 },
133 { X86::DEC16r, X86::DEC16m, 0 },
134 { X86::DEC32r, X86::DEC32m, 0 },
135 { X86::DEC64_16r, X86::DEC64_16m, 0 },
136 { X86::DEC64_32r, X86::DEC64_32m, 0 },
137 { X86::DEC64r, X86::DEC64m, 0 },
138 { X86::DEC8r, X86::DEC8m, 0 },
139 { X86::INC16r, X86::INC16m, 0 },
140 { X86::INC32r, X86::INC32m, 0 },
141 { X86::INC64_16r, X86::INC64_16m, 0 },
142 { X86::INC64_32r, X86::INC64_32m, 0 },
143 { X86::INC64r, X86::INC64m, 0 },
144 { X86::INC8r, X86::INC8m, 0 },
145 { X86::NEG16r, X86::NEG16m, 0 },
146 { X86::NEG32r, X86::NEG32m, 0 },
147 { X86::NEG64r, X86::NEG64m, 0 },
148 { X86::NEG8r, X86::NEG8m, 0 },
149 { X86::NOT16r, X86::NOT16m, 0 },
150 { X86::NOT32r, X86::NOT32m, 0 },
151 { X86::NOT64r, X86::NOT64m, 0 },
152 { X86::NOT8r, X86::NOT8m, 0 },
153 { X86::OR16ri, X86::OR16mi, 0 },
154 { X86::OR16ri8, X86::OR16mi8, 0 },
155 { X86::OR16rr, X86::OR16mr, 0 },
156 { X86::OR32ri, X86::OR32mi, 0 },
157 { X86::OR32ri8, X86::OR32mi8, 0 },
158 { X86::OR32rr, X86::OR32mr, 0 },
159 { X86::OR64ri32, X86::OR64mi32, 0 },
160 { X86::OR64ri8, X86::OR64mi8, 0 },
161 { X86::OR64rr, X86::OR64mr, 0 },
162 { X86::OR8ri, X86::OR8mi, 0 },
163 { X86::OR8rr, X86::OR8mr, 0 },
164 { X86::ROL16r1, X86::ROL16m1, 0 },
165 { X86::ROL16rCL, X86::ROL16mCL, 0 },
166 { X86::ROL16ri, X86::ROL16mi, 0 },
167 { X86::ROL32r1, X86::ROL32m1, 0 },
168 { X86::ROL32rCL, X86::ROL32mCL, 0 },
169 { X86::ROL32ri, X86::ROL32mi, 0 },
170 { X86::ROL64r1, X86::ROL64m1, 0 },
171 { X86::ROL64rCL, X86::ROL64mCL, 0 },
172 { X86::ROL64ri, X86::ROL64mi, 0 },
173 { X86::ROL8r1, X86::ROL8m1, 0 },
174 { X86::ROL8rCL, X86::ROL8mCL, 0 },
175 { X86::ROL8ri, X86::ROL8mi, 0 },
176 { X86::ROR16r1, X86::ROR16m1, 0 },
177 { X86::ROR16rCL, X86::ROR16mCL, 0 },
178 { X86::ROR16ri, X86::ROR16mi, 0 },
179 { X86::ROR32r1, X86::ROR32m1, 0 },
180 { X86::ROR32rCL, X86::ROR32mCL, 0 },
181 { X86::ROR32ri, X86::ROR32mi, 0 },
182 { X86::ROR64r1, X86::ROR64m1, 0 },
183 { X86::ROR64rCL, X86::ROR64mCL, 0 },
184 { X86::ROR64ri, X86::ROR64mi, 0 },
185 { X86::ROR8r1, X86::ROR8m1, 0 },
186 { X86::ROR8rCL, X86::ROR8mCL, 0 },
187 { X86::ROR8ri, X86::ROR8mi, 0 },
188 { X86::SAR16r1, X86::SAR16m1, 0 },
189 { X86::SAR16rCL, X86::SAR16mCL, 0 },
190 { X86::SAR16ri, X86::SAR16mi, 0 },
191 { X86::SAR32r1, X86::SAR32m1, 0 },
192 { X86::SAR32rCL, X86::SAR32mCL, 0 },
193 { X86::SAR32ri, X86::SAR32mi, 0 },
194 { X86::SAR64r1, X86::SAR64m1, 0 },
195 { X86::SAR64rCL, X86::SAR64mCL, 0 },
196 { X86::SAR64ri, X86::SAR64mi, 0 },
197 { X86::SAR8r1, X86::SAR8m1, 0 },
198 { X86::SAR8rCL, X86::SAR8mCL, 0 },
199 { X86::SAR8ri, X86::SAR8mi, 0 },
200 { X86::SBB32ri, X86::SBB32mi, 0 },
201 { X86::SBB32ri8, X86::SBB32mi8, 0 },
202 { X86::SBB32rr, X86::SBB32mr, 0 },
203 { X86::SBB64ri32, X86::SBB64mi32, 0 },
204 { X86::SBB64ri8, X86::SBB64mi8, 0 },
205 { X86::SBB64rr, X86::SBB64mr, 0 },
206 { X86::SHL16rCL, X86::SHL16mCL, 0 },
207 { X86::SHL16ri, X86::SHL16mi, 0 },
208 { X86::SHL32rCL, X86::SHL32mCL, 0 },
209 { X86::SHL32ri, X86::SHL32mi, 0 },
210 { X86::SHL64rCL, X86::SHL64mCL, 0 },
211 { X86::SHL64ri, X86::SHL64mi, 0 },
212 { X86::SHL8rCL, X86::SHL8mCL, 0 },
213 { X86::SHL8ri, X86::SHL8mi, 0 },
214 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
215 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
216 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
217 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
218 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
219 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
220 { X86::SHR16r1, X86::SHR16m1, 0 },
221 { X86::SHR16rCL, X86::SHR16mCL, 0 },
222 { X86::SHR16ri, X86::SHR16mi, 0 },
223 { X86::SHR32r1, X86::SHR32m1, 0 },
224 { X86::SHR32rCL, X86::SHR32mCL, 0 },
225 { X86::SHR32ri, X86::SHR32mi, 0 },
226 { X86::SHR64r1, X86::SHR64m1, 0 },
227 { X86::SHR64rCL, X86::SHR64mCL, 0 },
228 { X86::SHR64ri, X86::SHR64mi, 0 },
229 { X86::SHR8r1, X86::SHR8m1, 0 },
230 { X86::SHR8rCL, X86::SHR8mCL, 0 },
231 { X86::SHR8ri, X86::SHR8mi, 0 },
232 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
233 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
234 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
235 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
236 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
237 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
238 { X86::SUB16ri, X86::SUB16mi, 0 },
239 { X86::SUB16ri8, X86::SUB16mi8, 0 },
240 { X86::SUB16rr, X86::SUB16mr, 0 },
241 { X86::SUB32ri, X86::SUB32mi, 0 },
242 { X86::SUB32ri8, X86::SUB32mi8, 0 },
243 { X86::SUB32rr, X86::SUB32mr, 0 },
244 { X86::SUB64ri32, X86::SUB64mi32, 0 },
245 { X86::SUB64ri8, X86::SUB64mi8, 0 },
246 { X86::SUB64rr, X86::SUB64mr, 0 },
247 { X86::SUB8ri, X86::SUB8mi, 0 },
248 { X86::SUB8rr, X86::SUB8mr, 0 },
249 { X86::XOR16ri, X86::XOR16mi, 0 },
250 { X86::XOR16ri8, X86::XOR16mi8, 0 },
251 { X86::XOR16rr, X86::XOR16mr, 0 },
252 { X86::XOR32ri, X86::XOR32mi, 0 },
253 { X86::XOR32ri8, X86::XOR32mi8, 0 },
254 { X86::XOR32rr, X86::XOR32mr, 0 },
255 { X86::XOR64ri32, X86::XOR64mi32, 0 },
256 { X86::XOR64ri8, X86::XOR64mi8, 0 },
257 { X86::XOR64rr, X86::XOR64mr, 0 },
258 { X86::XOR8ri, X86::XOR8mi, 0 },
259 { X86::XOR8rr, X86::XOR8mr, 0 }
262 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
263 unsigned RegOp = OpTbl2Addr[i][0];
264 unsigned MemOp = OpTbl2Addr[i][1];
265 unsigned Flags = OpTbl2Addr[i][2];
266 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
268 // Index 0, folded load and store, no alignment requirement.
269 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
272 static const unsigned OpTbl0[][3] = {
273 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
274 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
275 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
276 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
277 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
278 { X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
279 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
280 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
281 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
282 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
283 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
284 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
285 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
286 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
287 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
288 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
289 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
290 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
291 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
292 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
293 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
294 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
295 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
296 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
297 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
298 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
299 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
300 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
301 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
302 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
303 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
304 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
305 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
306 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
307 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
308 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
309 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
310 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
311 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
312 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
313 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
314 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
315 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
316 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
317 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
318 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
319 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
320 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
321 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
322 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
323 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
324 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
325 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
326 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
327 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
328 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
329 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
330 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
331 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
332 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
333 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
334 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
335 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
336 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
337 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
338 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
339 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
340 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
341 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
342 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
343 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
344 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
345 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
346 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
347 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
348 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
349 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
350 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
351 // AVX 128-bit versions of foldable instructions
352 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
353 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
354 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
355 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
356 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
357 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
358 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
359 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
360 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
361 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
362 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
363 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
364 // AVX 256-bit foldable instructions
365 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
366 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
367 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
368 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
369 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
372 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
373 unsigned RegOp = OpTbl0[i][0];
374 unsigned MemOp = OpTbl0[i][1];
375 unsigned Flags = OpTbl0[i][2];
376 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
377 RegOp, MemOp, TB_INDEX_0 | Flags);
380 static const unsigned OpTbl1[][3] = {
381 { X86::CMP16rr, X86::CMP16rm, 0 },
382 { X86::CMP32rr, X86::CMP32rm, 0 },
383 { X86::CMP64rr, X86::CMP64rm, 0 },
384 { X86::CMP8rr, X86::CMP8rm, 0 },
385 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
386 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
387 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
388 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
389 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
390 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
391 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
392 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
393 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
394 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
395 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
396 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
397 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
398 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
399 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
400 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
401 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
402 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
403 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
404 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
405 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
406 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
407 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
408 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
409 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
410 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
411 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
412 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
413 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
414 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
415 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
416 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
417 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
418 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
419 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
420 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
421 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
422 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
423 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
424 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
425 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
426 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
427 { X86::MOV16rr, X86::MOV16rm, 0 },
428 { X86::MOV32rr, X86::MOV32rm, 0 },
429 { X86::MOV64rr, X86::MOV64rm, 0 },
430 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
431 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
432 { X86::MOV8rr, X86::MOV8rm, 0 },
433 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
434 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
435 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
436 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
437 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
438 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
439 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
440 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
441 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
442 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
443 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
444 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
445 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
446 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
447 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
448 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
449 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
450 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
451 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
452 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
453 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
454 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
455 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
456 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
457 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
458 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
459 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
460 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
461 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
462 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
463 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
464 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
465 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
466 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
467 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
468 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
469 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
470 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
471 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
472 { X86::SQRTSDr, X86::SQRTSDm, 0 },
473 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
474 { X86::SQRTSSr, X86::SQRTSSm, 0 },
475 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
476 { X86::TEST16rr, X86::TEST16rm, 0 },
477 { X86::TEST32rr, X86::TEST32rm, 0 },
478 { X86::TEST64rr, X86::TEST64rm, 0 },
479 { X86::TEST8rr, X86::TEST8rm, 0 },
480 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
481 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
482 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
483 // AVX 128-bit versions of foldable instructions
484 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
485 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
486 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
487 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
488 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
489 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
490 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
491 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
492 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
493 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
494 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
495 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
496 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
497 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
498 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
499 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
500 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
501 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
502 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
503 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
504 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
505 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
506 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
507 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
508 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
509 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
510 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
511 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
512 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
513 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
514 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
515 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
516 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
517 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
518 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
519 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
520 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
521 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
522 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
523 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
524 // AVX 256-bit foldable instructions
525 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
526 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
527 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 },
528 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
529 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }
532 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
533 unsigned RegOp = OpTbl1[i][0];
534 unsigned MemOp = OpTbl1[i][1];
535 unsigned Flags = OpTbl1[i][2];
536 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
538 // Index 1, folded load
539 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
542 static const unsigned OpTbl2[][3] = {
543 { X86::ADC32rr, X86::ADC32rm, 0 },
544 { X86::ADC64rr, X86::ADC64rm, 0 },
545 { X86::ADD16rr, X86::ADD16rm, 0 },
546 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
547 { X86::ADD32rr, X86::ADD32rm, 0 },
548 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
549 { X86::ADD64rr, X86::ADD64rm, 0 },
550 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
551 { X86::ADD8rr, X86::ADD8rm, 0 },
552 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
553 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
554 { X86::ADDSDrr, X86::ADDSDrm, 0 },
555 { X86::ADDSSrr, X86::ADDSSrm, 0 },
556 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
557 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
558 { X86::AND16rr, X86::AND16rm, 0 },
559 { X86::AND32rr, X86::AND32rm, 0 },
560 { X86::AND64rr, X86::AND64rm, 0 },
561 { X86::AND8rr, X86::AND8rm, 0 },
562 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
563 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
564 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
565 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
566 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
567 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
568 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
569 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
570 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
571 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
572 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
573 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
574 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
575 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
576 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
577 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
578 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
579 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
580 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
581 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
582 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
583 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
584 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
585 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
586 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
587 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
588 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
589 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
590 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
591 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
592 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
593 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
594 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
595 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
596 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
597 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
598 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
599 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
600 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
601 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
602 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
603 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
604 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
605 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
606 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
607 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
608 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
609 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
610 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
611 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
612 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
613 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
614 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
615 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
616 { X86::CMPSDrr, X86::CMPSDrm, 0 },
617 { X86::CMPSSrr, X86::CMPSSrm, 0 },
618 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
619 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
620 { X86::DIVSDrr, X86::DIVSDrm, 0 },
621 { X86::DIVSSrr, X86::DIVSSrm, 0 },
622 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
623 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
624 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
625 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
626 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
627 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
628 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
629 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
630 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
631 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
632 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
633 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
634 { X86::IMUL16rr, X86::IMUL16rm, 0 },
635 { X86::IMUL32rr, X86::IMUL32rm, 0 },
636 { X86::IMUL64rr, X86::IMUL64rm, 0 },
637 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
638 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
639 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
640 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
641 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
642 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
643 { X86::MAXSDrr, X86::MAXSDrm, 0 },
644 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
645 { X86::MAXSSrr, X86::MAXSSrm, 0 },
646 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
647 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
648 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
649 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
650 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
651 { X86::MINSDrr, X86::MINSDrm, 0 },
652 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
653 { X86::MINSSrr, X86::MINSSrm, 0 },
654 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
655 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
656 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
657 { X86::MULSDrr, X86::MULSDrm, 0 },
658 { X86::MULSSrr, X86::MULSSrm, 0 },
659 { X86::OR16rr, X86::OR16rm, 0 },
660 { X86::OR32rr, X86::OR32rm, 0 },
661 { X86::OR64rr, X86::OR64rm, 0 },
662 { X86::OR8rr, X86::OR8rm, 0 },
663 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
664 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
665 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
666 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
667 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
668 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
669 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
670 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
671 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
672 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
673 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
674 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
675 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
676 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
677 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
678 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
679 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
680 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
681 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
682 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
683 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
684 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
685 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
686 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
687 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
688 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
689 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
690 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
691 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
692 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
693 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
694 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
695 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
696 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
697 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
698 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
699 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
700 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
701 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
702 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
703 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
704 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
705 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
706 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
707 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
708 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
709 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
710 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
711 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
712 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
713 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
714 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
715 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
716 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
717 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
718 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
719 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
720 { X86::SBB32rr, X86::SBB32rm, 0 },
721 { X86::SBB64rr, X86::SBB64rm, 0 },
722 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
723 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
724 { X86::SUB16rr, X86::SUB16rm, 0 },
725 { X86::SUB32rr, X86::SUB32rm, 0 },
726 { X86::SUB64rr, X86::SUB64rm, 0 },
727 { X86::SUB8rr, X86::SUB8rm, 0 },
728 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
729 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
730 { X86::SUBSDrr, X86::SUBSDrm, 0 },
731 { X86::SUBSSrr, X86::SUBSSrm, 0 },
732 // FIXME: TEST*rr -> swapped operand of TEST*mr.
733 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
734 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
735 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
736 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
737 { X86::XOR16rr, X86::XOR16rm, 0 },
738 { X86::XOR32rr, X86::XOR32rm, 0 },
739 { X86::XOR64rr, X86::XOR64rm, 0 },
740 { X86::XOR8rr, X86::XOR8rm, 0 },
741 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
742 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
743 // AVX 128-bit versions of foldable instructions
744 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
745 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
746 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
747 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
748 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
749 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
750 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
751 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
752 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
753 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
754 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
755 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
756 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
757 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
758 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
759 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
760 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
761 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
762 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
763 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
764 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
765 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
766 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
767 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
768 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
769 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
770 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
771 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
772 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
773 { X86::VADDSDrr, X86::VADDSDrm, 0 },
774 { X86::VADDSSrr, X86::VADDSSrm, 0 },
775 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
776 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
777 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
778 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
779 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
780 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
781 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
782 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
783 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
784 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
785 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
786 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
787 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
788 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
789 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
790 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
791 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
792 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
793 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
794 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
795 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
796 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
797 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
798 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
799 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
800 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
801 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
802 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
803 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
804 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
805 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
806 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
807 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
808 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
809 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
810 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
811 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
812 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
813 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
814 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
815 { X86::VMINSDrr, X86::VMINSDrm, 0 },
816 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
817 { X86::VMINSSrr, X86::VMINSSrm, 0 },
818 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
819 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
820 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
821 { X86::VMULSDrr, X86::VMULSDrm, 0 },
822 { X86::VMULSSrr, X86::VMULSSrm, 0 },
823 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
824 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
825 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
826 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
827 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
828 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
829 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
830 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
831 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
832 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
833 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
834 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
835 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
836 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
837 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
838 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
839 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
840 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
841 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
842 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
843 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
844 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
845 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
846 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
847 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
848 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
849 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
850 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
851 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
852 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
853 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
854 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
855 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
856 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
857 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
858 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
859 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
860 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
861 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
862 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
863 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
864 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
865 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
866 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
867 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
868 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
869 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
870 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
871 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
872 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
873 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
874 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
875 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
876 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
877 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
878 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
879 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
880 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
881 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
882 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
883 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
884 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
885 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
886 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
887 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
888 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
889 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }
890 // FIXME: add AVX 256-bit foldable instructions
893 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
894 unsigned RegOp = OpTbl2[i][0];
895 unsigned MemOp = OpTbl2[i][1];
896 unsigned Flags = OpTbl2[i][2];
897 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
899 // Index 2, folded load
900 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
905 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
906 MemOp2RegOpTableType &M2RTable,
907 unsigned RegOp, unsigned MemOp, unsigned Flags) {
908 if ((Flags & TB_NO_FORWARD) == 0) {
909 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
910 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
912 if ((Flags & TB_NO_REVERSE) == 0) {
913 assert(!M2RTable.count(MemOp) &&
914 "Duplicated entries in unfolding maps?");
915 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
920 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
921 unsigned &SrcReg, unsigned &DstReg,
922 unsigned &SubIdx) const {
923 switch (MI.getOpcode()) {
925 case X86::MOVSX16rr8:
926 case X86::MOVZX16rr8:
927 case X86::MOVSX32rr8:
928 case X86::MOVZX32rr8:
929 case X86::MOVSX64rr8:
930 case X86::MOVZX64rr8:
931 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
932 // It's not always legal to reference the low 8-bit of the larger
933 // register in 32-bit mode.
935 case X86::MOVSX32rr16:
936 case X86::MOVZX32rr16:
937 case X86::MOVSX64rr16:
938 case X86::MOVZX64rr16:
939 case X86::MOVSX64rr32:
940 case X86::MOVZX64rr32: {
941 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
944 SrcReg = MI.getOperand(1).getReg();
945 DstReg = MI.getOperand(0).getReg();
946 switch (MI.getOpcode()) {
950 case X86::MOVSX16rr8:
951 case X86::MOVZX16rr8:
952 case X86::MOVSX32rr8:
953 case X86::MOVZX32rr8:
954 case X86::MOVSX64rr8:
955 case X86::MOVZX64rr8:
956 SubIdx = X86::sub_8bit;
958 case X86::MOVSX32rr16:
959 case X86::MOVZX32rr16:
960 case X86::MOVSX64rr16:
961 case X86::MOVZX64rr16:
962 SubIdx = X86::sub_16bit;
964 case X86::MOVSX64rr32:
965 case X86::MOVZX64rr32:
966 SubIdx = X86::sub_32bit;
975 /// isFrameOperand - Return true and the FrameIndex if the specified
976 /// operand and follow operands form a reference to the stack frame.
977 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
978 int &FrameIndex) const {
979 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
980 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
981 MI->getOperand(Op+1).getImm() == 1 &&
982 MI->getOperand(Op+2).getReg() == 0 &&
983 MI->getOperand(Op+3).getImm() == 0) {
984 FrameIndex = MI->getOperand(Op).getIndex();
990 static bool isFrameLoadOpcode(int Opcode) {
1005 case X86::VMOVAPSrm:
1006 case X86::VMOVAPDrm:
1007 case X86::VMOVDQArm:
1008 case X86::VMOVAPSYrm:
1009 case X86::VMOVAPDYrm:
1010 case X86::VMOVDQAYrm:
1011 case X86::MMX_MOVD64rm:
1012 case X86::MMX_MOVQ64rm:
1019 static bool isFrameStoreOpcode(int Opcode) {
1026 case X86::ST_FpP64m:
1034 case X86::VMOVAPSmr:
1035 case X86::VMOVAPDmr:
1036 case X86::VMOVDQAmr:
1037 case X86::VMOVAPSYmr:
1038 case X86::VMOVAPDYmr:
1039 case X86::VMOVDQAYmr:
1040 case X86::MMX_MOVD64mr:
1041 case X86::MMX_MOVQ64mr:
1042 case X86::MMX_MOVNTQmr:
1048 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1049 int &FrameIndex) const {
1050 if (isFrameLoadOpcode(MI->getOpcode()))
1051 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1052 return MI->getOperand(0).getReg();
1056 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1057 int &FrameIndex) const {
1058 if (isFrameLoadOpcode(MI->getOpcode())) {
1060 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1062 // Check for post-frame index elimination operations
1063 const MachineMemOperand *Dummy;
1064 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1069 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1070 int &FrameIndex) const {
1071 if (isFrameStoreOpcode(MI->getOpcode()))
1072 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1073 isFrameOperand(MI, 0, FrameIndex))
1074 return MI->getOperand(X86::AddrNumOperands).getReg();
1078 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1079 int &FrameIndex) const {
1080 if (isFrameStoreOpcode(MI->getOpcode())) {
1082 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1084 // Check for post-frame index elimination operations
1085 const MachineMemOperand *Dummy;
1086 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1091 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1093 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1094 bool isPICBase = false;
1095 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1096 E = MRI.def_end(); I != E; ++I) {
1097 MachineInstr *DefMI = I.getOperand().getParent();
1098 if (DefMI->getOpcode() != X86::MOVPC32r)
1100 assert(!isPICBase && "More than one PIC base?");
1107 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1108 AliasAnalysis *AA) const {
1109 switch (MI->getOpcode()) {
1124 case X86::VMOVAPSrm:
1125 case X86::VMOVUPSrm:
1126 case X86::VMOVAPDrm:
1127 case X86::VMOVDQArm:
1128 case X86::VMOVAPSYrm:
1129 case X86::VMOVUPSYrm:
1130 case X86::VMOVAPDYrm:
1131 case X86::VMOVDQAYrm:
1132 case X86::MMX_MOVD64rm:
1133 case X86::MMX_MOVQ64rm:
1134 case X86::FsVMOVAPSrm:
1135 case X86::FsVMOVAPDrm:
1136 case X86::FsMOVAPSrm:
1137 case X86::FsMOVAPDrm: {
1138 // Loads from constant pools are trivially rematerializable.
1139 if (MI->getOperand(1).isReg() &&
1140 MI->getOperand(2).isImm() &&
1141 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1142 MI->isInvariantLoad(AA)) {
1143 unsigned BaseReg = MI->getOperand(1).getReg();
1144 if (BaseReg == 0 || BaseReg == X86::RIP)
1146 // Allow re-materialization of PIC load.
1147 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1149 const MachineFunction &MF = *MI->getParent()->getParent();
1150 const MachineRegisterInfo &MRI = MF.getRegInfo();
1151 bool isPICBase = false;
1152 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1153 E = MRI.def_end(); I != E; ++I) {
1154 MachineInstr *DefMI = I.getOperand().getParent();
1155 if (DefMI->getOpcode() != X86::MOVPC32r)
1157 assert(!isPICBase && "More than one PIC base?");
1167 if (MI->getOperand(2).isImm() &&
1168 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1169 !MI->getOperand(4).isReg()) {
1170 // lea fi#, lea GV, etc. are all rematerializable.
1171 if (!MI->getOperand(1).isReg())
1173 unsigned BaseReg = MI->getOperand(1).getReg();
1176 // Allow re-materialization of lea PICBase + x.
1177 const MachineFunction &MF = *MI->getParent()->getParent();
1178 const MachineRegisterInfo &MRI = MF.getRegInfo();
1179 return regIsPICBase(BaseReg, MRI);
1185 // All other instructions marked M_REMATERIALIZABLE are always trivially
1186 // rematerializable.
1190 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1191 /// would clobber the EFLAGS condition register. Note the result may be
1192 /// conservative. If it cannot definitely determine the safety after visiting
1193 /// a few instructions in each direction it assumes it's not safe.
1194 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1195 MachineBasicBlock::iterator I) {
1196 MachineBasicBlock::iterator E = MBB.end();
1198 // For compile time consideration, if we are not able to determine the
1199 // safety after visiting 4 instructions in each direction, we will assume
1201 MachineBasicBlock::iterator Iter = I;
1202 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1203 bool SeenDef = false;
1204 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1205 MachineOperand &MO = Iter->getOperand(j);
1208 if (MO.getReg() == X86::EFLAGS) {
1216 // This instruction defines EFLAGS, no need to look any further.
1219 // Skip over DBG_VALUE.
1220 while (Iter != E && Iter->isDebugValue())
1224 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1227 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1228 SE = MBB.succ_end(); SI != SE; ++SI)
1229 if ((*SI)->isLiveIn(X86::EFLAGS))
1234 MachineBasicBlock::iterator B = MBB.begin();
1236 for (unsigned i = 0; i < 4; ++i) {
1237 // If we make it to the beginning of the block, it's safe to clobber
1238 // EFLAGS iff EFLAGS is not live-in.
1240 return !MBB.isLiveIn(X86::EFLAGS);
1243 // Skip over DBG_VALUE.
1244 while (Iter != B && Iter->isDebugValue())
1247 bool SawKill = false;
1248 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1249 MachineOperand &MO = Iter->getOperand(j);
1250 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1251 if (MO.isDef()) return MO.isDead();
1252 if (MO.isKill()) SawKill = true;
1257 // This instruction kills EFLAGS and doesn't redefine it, so
1258 // there's no need to look further.
1262 // Conservative answer.
1266 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1267 MachineBasicBlock::iterator I,
1268 unsigned DestReg, unsigned SubIdx,
1269 const MachineInstr *Orig,
1270 const TargetRegisterInfo &TRI) const {
1271 DebugLoc DL = Orig->getDebugLoc();
1273 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1274 // Re-materialize them as movri instructions to avoid side effects.
1276 unsigned Opc = Orig->getOpcode();
1282 case X86::MOV64r0: {
1283 if (!isSafeToClobberEFLAGS(MBB, I)) {
1286 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1287 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1288 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1289 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1298 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1301 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1304 MachineInstr *NewMI = prior(I);
1305 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1308 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1309 /// is not marked dead.
1310 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1311 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1312 MachineOperand &MO = MI->getOperand(i);
1313 if (MO.isReg() && MO.isDef() &&
1314 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1321 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1322 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1323 /// to a 32-bit superregister and then truncating back down to a 16-bit
1326 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1327 MachineFunction::iterator &MFI,
1328 MachineBasicBlock::iterator &MBBI,
1329 LiveVariables *LV) const {
1330 MachineInstr *MI = MBBI;
1331 unsigned Dest = MI->getOperand(0).getReg();
1332 unsigned Src = MI->getOperand(1).getReg();
1333 bool isDead = MI->getOperand(0).isDead();
1334 bool isKill = MI->getOperand(1).isKill();
1336 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1337 ? X86::LEA64_32r : X86::LEA32r;
1338 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1339 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1340 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1342 // Build and insert into an implicit UNDEF value. This is OK because
1343 // well be shifting and then extracting the lower 16-bits.
1344 // This has the potential to cause partial register stall. e.g.
1345 // movw (%rbp,%rcx,2), %dx
1346 // leal -65(%rdx), %esi
1347 // But testing has shown this *does* help performance in 64-bit mode (at
1348 // least on modern x86 machines).
1349 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1350 MachineInstr *InsMI =
1351 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1352 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1353 .addReg(Src, getKillRegState(isKill));
1355 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1356 get(Opc), leaOutReg);
1359 llvm_unreachable(0);
1361 case X86::SHL16ri: {
1362 unsigned ShAmt = MI->getOperand(2).getImm();
1363 MIB.addReg(0).addImm(1 << ShAmt)
1364 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1368 case X86::INC64_16r:
1369 addRegOffset(MIB, leaInReg, true, 1);
1372 case X86::DEC64_16r:
1373 addRegOffset(MIB, leaInReg, true, -1);
1377 case X86::ADD16ri_DB:
1378 case X86::ADD16ri8_DB:
1379 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1382 case X86::ADD16rr_DB: {
1383 unsigned Src2 = MI->getOperand(2).getReg();
1384 bool isKill2 = MI->getOperand(2).isKill();
1385 unsigned leaInReg2 = 0;
1386 MachineInstr *InsMI2 = 0;
1388 // ADD16rr %reg1028<kill>, %reg1028
1389 // just a single insert_subreg.
1390 addRegReg(MIB, leaInReg, true, leaInReg, false);
1392 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1393 // Build and insert into an implicit UNDEF value. This is OK because
1394 // well be shifting and then extracting the lower 16-bits.
1395 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1397 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1398 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1399 .addReg(Src2, getKillRegState(isKill2));
1400 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1402 if (LV && isKill2 && InsMI2)
1403 LV->replaceKillInstruction(Src2, MI, InsMI2);
1408 MachineInstr *NewMI = MIB;
1409 MachineInstr *ExtMI =
1410 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1411 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1412 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1415 // Update live variables
1416 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1417 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1419 LV->replaceKillInstruction(Src, MI, InsMI);
1421 LV->replaceKillInstruction(Dest, MI, ExtMI);
1427 /// convertToThreeAddress - This method must be implemented by targets that
1428 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1429 /// may be able to convert a two-address instruction into a true
1430 /// three-address instruction on demand. This allows the X86 target (for
1431 /// example) to convert ADD and SHL instructions into LEA instructions if they
1432 /// would require register copies due to two-addressness.
1434 /// This method returns a null pointer if the transformation cannot be
1435 /// performed, otherwise it returns the new instruction.
1438 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1439 MachineBasicBlock::iterator &MBBI,
1440 LiveVariables *LV) const {
1441 MachineInstr *MI = MBBI;
1442 MachineFunction &MF = *MI->getParent()->getParent();
1443 // All instructions input are two-addr instructions. Get the known operands.
1444 unsigned Dest = MI->getOperand(0).getReg();
1445 unsigned Src = MI->getOperand(1).getReg();
1446 bool isDead = MI->getOperand(0).isDead();
1447 bool isKill = MI->getOperand(1).isKill();
1449 MachineInstr *NewMI = NULL;
1450 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1451 // we have better subtarget support, enable the 16-bit LEA generation here.
1452 // 16-bit LEA is also slow on Core2.
1453 bool DisableLEA16 = true;
1454 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1456 unsigned MIOpc = MI->getOpcode();
1458 case X86::SHUFPSrri: {
1459 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1460 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1462 unsigned B = MI->getOperand(1).getReg();
1463 unsigned C = MI->getOperand(2).getReg();
1464 if (B != C) return 0;
1465 unsigned A = MI->getOperand(0).getReg();
1466 unsigned M = MI->getOperand(3).getImm();
1467 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1468 .addReg(A, RegState::Define | getDeadRegState(isDead))
1469 .addReg(B, getKillRegState(isKill)).addImm(M);
1472 case X86::SHL64ri: {
1473 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1474 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1475 // the flags produced by a shift yet, so this is safe.
1476 unsigned ShAmt = MI->getOperand(2).getImm();
1477 if (ShAmt == 0 || ShAmt >= 4) return 0;
1479 // LEA can't handle RSP.
1480 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1481 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1484 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1485 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1486 .addReg(0).addImm(1 << ShAmt)
1487 .addReg(Src, getKillRegState(isKill))
1488 .addImm(0).addReg(0);
1491 case X86::SHL32ri: {
1492 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1493 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1494 // the flags produced by a shift yet, so this is safe.
1495 unsigned ShAmt = MI->getOperand(2).getImm();
1496 if (ShAmt == 0 || ShAmt >= 4) return 0;
1498 // LEA can't handle ESP.
1499 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1500 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1503 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1504 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1505 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1506 .addReg(0).addImm(1 << ShAmt)
1507 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1510 case X86::SHL16ri: {
1511 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1512 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1513 // the flags produced by a shift yet, so this is safe.
1514 unsigned ShAmt = MI->getOperand(2).getImm();
1515 if (ShAmt == 0 || ShAmt >= 4) return 0;
1518 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1519 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1520 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1521 .addReg(0).addImm(1 << ShAmt)
1522 .addReg(Src, getKillRegState(isKill))
1523 .addImm(0).addReg(0);
1527 // The following opcodes also sets the condition code register(s). Only
1528 // convert them to equivalent lea if the condition code register def's
1530 if (hasLiveCondCodeDef(MI))
1537 case X86::INC64_32r: {
1538 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1539 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1540 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1542 // LEA can't handle RSP.
1543 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1544 !MF.getRegInfo().constrainRegClass(Src,
1545 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1546 X86::GR32_NOSPRegisterClass))
1549 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1550 .addReg(Dest, RegState::Define |
1551 getDeadRegState(isDead)),
1556 case X86::INC64_16r:
1558 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1559 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1560 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1561 .addReg(Dest, RegState::Define |
1562 getDeadRegState(isDead)),
1567 case X86::DEC64_32r: {
1568 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1569 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1570 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1571 // LEA can't handle RSP.
1572 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1573 !MF.getRegInfo().constrainRegClass(Src,
1574 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1575 X86::GR32_NOSPRegisterClass))
1578 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1579 .addReg(Dest, RegState::Define |
1580 getDeadRegState(isDead)),
1585 case X86::DEC64_16r:
1587 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1588 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1589 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1590 .addReg(Dest, RegState::Define |
1591 getDeadRegState(isDead)),
1595 case X86::ADD64rr_DB:
1597 case X86::ADD32rr_DB: {
1598 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1600 TargetRegisterClass *RC;
1601 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1603 RC = X86::GR64_NOSPRegisterClass;
1605 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1606 RC = X86::GR32_NOSPRegisterClass;
1610 unsigned Src2 = MI->getOperand(2).getReg();
1611 bool isKill2 = MI->getOperand(2).isKill();
1613 // LEA can't handle RSP.
1614 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1615 !MF.getRegInfo().constrainRegClass(Src2, RC))
1618 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1619 .addReg(Dest, RegState::Define |
1620 getDeadRegState(isDead)),
1621 Src, isKill, Src2, isKill2);
1623 LV->replaceKillInstruction(Src2, MI, NewMI);
1627 case X86::ADD16rr_DB: {
1629 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1630 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1631 unsigned Src2 = MI->getOperand(2).getReg();
1632 bool isKill2 = MI->getOperand(2).isKill();
1633 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1634 .addReg(Dest, RegState::Define |
1635 getDeadRegState(isDead)),
1636 Src, isKill, Src2, isKill2);
1638 LV->replaceKillInstruction(Src2, MI, NewMI);
1641 case X86::ADD64ri32:
1643 case X86::ADD64ri32_DB:
1644 case X86::ADD64ri8_DB:
1645 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1646 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1647 .addReg(Dest, RegState::Define |
1648 getDeadRegState(isDead)),
1649 Src, isKill, MI->getOperand(2).getImm());
1653 case X86::ADD32ri_DB:
1654 case X86::ADD32ri8_DB: {
1655 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1656 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1657 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1658 .addReg(Dest, RegState::Define |
1659 getDeadRegState(isDead)),
1660 Src, isKill, MI->getOperand(2).getImm());
1665 case X86::ADD16ri_DB:
1666 case X86::ADD16ri8_DB:
1668 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1669 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1670 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1671 .addReg(Dest, RegState::Define |
1672 getDeadRegState(isDead)),
1673 Src, isKill, MI->getOperand(2).getImm());
1679 if (!NewMI) return 0;
1681 if (LV) { // Update live variables
1683 LV->replaceKillInstruction(Src, MI, NewMI);
1685 LV->replaceKillInstruction(Dest, MI, NewMI);
1688 MFI->insert(MBBI, NewMI); // Insert the new inst
1692 /// commuteInstruction - We have a few instructions that must be hacked on to
1696 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1697 switch (MI->getOpcode()) {
1698 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1699 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1700 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1701 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1702 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1703 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1706 switch (MI->getOpcode()) {
1707 default: llvm_unreachable("Unreachable!");
1708 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1709 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1710 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1711 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1712 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1713 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1715 unsigned Amt = MI->getOperand(3).getImm();
1717 MachineFunction &MF = *MI->getParent()->getParent();
1718 MI = MF.CloneMachineInstr(MI);
1721 MI->setDesc(get(Opc));
1722 MI->getOperand(3).setImm(Size-Amt);
1723 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1725 case X86::CMOVB16rr:
1726 case X86::CMOVB32rr:
1727 case X86::CMOVB64rr:
1728 case X86::CMOVAE16rr:
1729 case X86::CMOVAE32rr:
1730 case X86::CMOVAE64rr:
1731 case X86::CMOVE16rr:
1732 case X86::CMOVE32rr:
1733 case X86::CMOVE64rr:
1734 case X86::CMOVNE16rr:
1735 case X86::CMOVNE32rr:
1736 case X86::CMOVNE64rr:
1737 case X86::CMOVBE16rr:
1738 case X86::CMOVBE32rr:
1739 case X86::CMOVBE64rr:
1740 case X86::CMOVA16rr:
1741 case X86::CMOVA32rr:
1742 case X86::CMOVA64rr:
1743 case X86::CMOVL16rr:
1744 case X86::CMOVL32rr:
1745 case X86::CMOVL64rr:
1746 case X86::CMOVGE16rr:
1747 case X86::CMOVGE32rr:
1748 case X86::CMOVGE64rr:
1749 case X86::CMOVLE16rr:
1750 case X86::CMOVLE32rr:
1751 case X86::CMOVLE64rr:
1752 case X86::CMOVG16rr:
1753 case X86::CMOVG32rr:
1754 case X86::CMOVG64rr:
1755 case X86::CMOVS16rr:
1756 case X86::CMOVS32rr:
1757 case X86::CMOVS64rr:
1758 case X86::CMOVNS16rr:
1759 case X86::CMOVNS32rr:
1760 case X86::CMOVNS64rr:
1761 case X86::CMOVP16rr:
1762 case X86::CMOVP32rr:
1763 case X86::CMOVP64rr:
1764 case X86::CMOVNP16rr:
1765 case X86::CMOVNP32rr:
1766 case X86::CMOVNP64rr:
1767 case X86::CMOVO16rr:
1768 case X86::CMOVO32rr:
1769 case X86::CMOVO64rr:
1770 case X86::CMOVNO16rr:
1771 case X86::CMOVNO32rr:
1772 case X86::CMOVNO64rr: {
1774 switch (MI->getOpcode()) {
1776 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1777 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1778 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1779 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1780 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1781 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1782 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1783 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1784 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1785 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1786 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1787 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1788 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1789 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1790 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1791 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1792 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1793 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1794 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1795 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1796 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1797 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1798 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1799 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1800 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1801 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1802 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1803 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1804 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1805 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1806 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1807 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1808 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1809 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1810 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1811 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1812 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1813 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1814 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1815 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1816 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1817 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1818 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1819 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1820 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1821 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1822 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1823 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1826 MachineFunction &MF = *MI->getParent()->getParent();
1827 MI = MF.CloneMachineInstr(MI);
1830 MI->setDesc(get(Opc));
1831 // Fallthrough intended.
1834 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1838 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1840 default: return X86::COND_INVALID;
1841 case X86::JE_4: return X86::COND_E;
1842 case X86::JNE_4: return X86::COND_NE;
1843 case X86::JL_4: return X86::COND_L;
1844 case X86::JLE_4: return X86::COND_LE;
1845 case X86::JG_4: return X86::COND_G;
1846 case X86::JGE_4: return X86::COND_GE;
1847 case X86::JB_4: return X86::COND_B;
1848 case X86::JBE_4: return X86::COND_BE;
1849 case X86::JA_4: return X86::COND_A;
1850 case X86::JAE_4: return X86::COND_AE;
1851 case X86::JS_4: return X86::COND_S;
1852 case X86::JNS_4: return X86::COND_NS;
1853 case X86::JP_4: return X86::COND_P;
1854 case X86::JNP_4: return X86::COND_NP;
1855 case X86::JO_4: return X86::COND_O;
1856 case X86::JNO_4: return X86::COND_NO;
1860 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1862 default: llvm_unreachable("Illegal condition code!");
1863 case X86::COND_E: return X86::JE_4;
1864 case X86::COND_NE: return X86::JNE_4;
1865 case X86::COND_L: return X86::JL_4;
1866 case X86::COND_LE: return X86::JLE_4;
1867 case X86::COND_G: return X86::JG_4;
1868 case X86::COND_GE: return X86::JGE_4;
1869 case X86::COND_B: return X86::JB_4;
1870 case X86::COND_BE: return X86::JBE_4;
1871 case X86::COND_A: return X86::JA_4;
1872 case X86::COND_AE: return X86::JAE_4;
1873 case X86::COND_S: return X86::JS_4;
1874 case X86::COND_NS: return X86::JNS_4;
1875 case X86::COND_P: return X86::JP_4;
1876 case X86::COND_NP: return X86::JNP_4;
1877 case X86::COND_O: return X86::JO_4;
1878 case X86::COND_NO: return X86::JNO_4;
1882 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1883 /// e.g. turning COND_E to COND_NE.
1884 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1886 default: llvm_unreachable("Illegal condition code!");
1887 case X86::COND_E: return X86::COND_NE;
1888 case X86::COND_NE: return X86::COND_E;
1889 case X86::COND_L: return X86::COND_GE;
1890 case X86::COND_LE: return X86::COND_G;
1891 case X86::COND_G: return X86::COND_LE;
1892 case X86::COND_GE: return X86::COND_L;
1893 case X86::COND_B: return X86::COND_AE;
1894 case X86::COND_BE: return X86::COND_A;
1895 case X86::COND_A: return X86::COND_BE;
1896 case X86::COND_AE: return X86::COND_B;
1897 case X86::COND_S: return X86::COND_NS;
1898 case X86::COND_NS: return X86::COND_S;
1899 case X86::COND_P: return X86::COND_NP;
1900 case X86::COND_NP: return X86::COND_P;
1901 case X86::COND_O: return X86::COND_NO;
1902 case X86::COND_NO: return X86::COND_O;
1906 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1907 const MCInstrDesc &MCID = MI->getDesc();
1908 if (!MCID.isTerminator()) return false;
1910 // Conditional branch is a special case.
1911 if (MCID.isBranch() && !MCID.isBarrier())
1913 if (!MCID.isPredicable())
1915 return !isPredicated(MI);
1918 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1919 MachineBasicBlock *&TBB,
1920 MachineBasicBlock *&FBB,
1921 SmallVectorImpl<MachineOperand> &Cond,
1922 bool AllowModify) const {
1923 // Start from the bottom of the block and work up, examining the
1924 // terminator instructions.
1925 MachineBasicBlock::iterator I = MBB.end();
1926 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1927 while (I != MBB.begin()) {
1929 if (I->isDebugValue())
1932 // Working from the bottom, when we see a non-terminator instruction, we're
1934 if (!isUnpredicatedTerminator(I))
1937 // A terminator that isn't a branch can't easily be handled by this
1939 if (!I->getDesc().isBranch())
1942 // Handle unconditional branches.
1943 if (I->getOpcode() == X86::JMP_4) {
1947 TBB = I->getOperand(0).getMBB();
1951 // If the block has any instructions after a JMP, delete them.
1952 while (llvm::next(I) != MBB.end())
1953 llvm::next(I)->eraseFromParent();
1958 // Delete the JMP if it's equivalent to a fall-through.
1959 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1961 I->eraseFromParent();
1963 UnCondBrIter = MBB.end();
1967 // TBB is used to indicate the unconditional destination.
1968 TBB = I->getOperand(0).getMBB();
1972 // Handle conditional branches.
1973 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1974 if (BranchCode == X86::COND_INVALID)
1975 return true; // Can't handle indirect branch.
1977 // Working from the bottom, handle the first conditional branch.
1979 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1980 if (AllowModify && UnCondBrIter != MBB.end() &&
1981 MBB.isLayoutSuccessor(TargetBB)) {
1982 // If we can modify the code and it ends in something like:
1990 // Then we can change this to:
1997 // Which is a bit more efficient.
1998 // We conditionally jump to the fall-through block.
1999 BranchCode = GetOppositeBranchCondition(BranchCode);
2000 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2001 MachineBasicBlock::iterator OldInst = I;
2003 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2004 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2005 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2008 OldInst->eraseFromParent();
2009 UnCondBrIter->eraseFromParent();
2011 // Restart the analysis.
2012 UnCondBrIter = MBB.end();
2018 TBB = I->getOperand(0).getMBB();
2019 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2023 // Handle subsequent conditional branches. Only handle the case where all
2024 // conditional branches branch to the same destination and their condition
2025 // opcodes fit one of the special multi-branch idioms.
2026 assert(Cond.size() == 1);
2029 // Only handle the case where all conditional branches branch to the same
2031 if (TBB != I->getOperand(0).getMBB())
2034 // If the conditions are the same, we can leave them alone.
2035 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2036 if (OldBranchCode == BranchCode)
2039 // If they differ, see if they fit one of the known patterns. Theoretically,
2040 // we could handle more patterns here, but we shouldn't expect to see them
2041 // if instruction selection has done a reasonable job.
2042 if ((OldBranchCode == X86::COND_NP &&
2043 BranchCode == X86::COND_E) ||
2044 (OldBranchCode == X86::COND_E &&
2045 BranchCode == X86::COND_NP))
2046 BranchCode = X86::COND_NP_OR_E;
2047 else if ((OldBranchCode == X86::COND_P &&
2048 BranchCode == X86::COND_NE) ||
2049 (OldBranchCode == X86::COND_NE &&
2050 BranchCode == X86::COND_P))
2051 BranchCode = X86::COND_NE_OR_P;
2055 // Update the MachineOperand.
2056 Cond[0].setImm(BranchCode);
2062 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2063 MachineBasicBlock::iterator I = MBB.end();
2066 while (I != MBB.begin()) {
2068 if (I->isDebugValue())
2070 if (I->getOpcode() != X86::JMP_4 &&
2071 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2073 // Remove the branch.
2074 I->eraseFromParent();
2083 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2084 MachineBasicBlock *FBB,
2085 const SmallVectorImpl<MachineOperand> &Cond,
2086 DebugLoc DL) const {
2087 // Shouldn't be a fall through.
2088 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2089 assert((Cond.size() == 1 || Cond.size() == 0) &&
2090 "X86 branch conditions have one component!");
2093 // Unconditional branch?
2094 assert(!FBB && "Unconditional branch with multiple successors!");
2095 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2099 // Conditional branch.
2101 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2103 case X86::COND_NP_OR_E:
2104 // Synthesize NP_OR_E with two branches.
2105 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2107 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2110 case X86::COND_NE_OR_P:
2111 // Synthesize NE_OR_P with two branches.
2112 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2114 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2118 unsigned Opc = GetCondBranchFromCond(CC);
2119 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2124 // Two-way Conditional branch. Insert the second branch.
2125 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2131 /// isHReg - Test if the given register is a physical h register.
2132 static bool isHReg(unsigned Reg) {
2133 return X86::GR8_ABCD_HRegClass.contains(Reg);
2136 // Try and copy between VR128/VR64 and GR64 registers.
2137 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2139 // SrcReg(VR128) -> DestReg(GR64)
2140 // SrcReg(VR64) -> DestReg(GR64)
2141 // SrcReg(GR64) -> DestReg(VR128)
2142 // SrcReg(GR64) -> DestReg(VR64)
2144 if (X86::GR64RegClass.contains(DestReg)) {
2145 if (X86::VR128RegClass.contains(SrcReg)) {
2146 // Copy from a VR128 register to a GR64 register.
2147 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2148 } else if (X86::VR64RegClass.contains(SrcReg)) {
2149 // Copy from a VR64 register to a GR64 register.
2150 return X86::MOVSDto64rr;
2152 } else if (X86::GR64RegClass.contains(SrcReg)) {
2153 // Copy from a GR64 register to a VR128 register.
2154 if (X86::VR128RegClass.contains(DestReg))
2155 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2156 // Copy from a GR64 register to a VR64 register.
2157 else if (X86::VR64RegClass.contains(DestReg))
2158 return X86::MOV64toSDrr;
2164 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2165 MachineBasicBlock::iterator MI, DebugLoc DL,
2166 unsigned DestReg, unsigned SrcReg,
2167 bool KillSrc) const {
2168 // First deal with the normal symmetric copies.
2169 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2171 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2173 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2175 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2177 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2178 // Copying to or from a physical H register on x86-64 requires a NOREX
2179 // move. Otherwise use a normal move.
2180 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2181 TM.getSubtarget<X86Subtarget>().is64Bit())
2182 Opc = X86::MOV8rr_NOREX;
2185 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2186 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2187 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2188 Opc = X86::VMOVAPSYrr;
2189 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2190 Opc = X86::MMX_MOVQ64rr;
2192 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2195 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2196 .addReg(SrcReg, getKillRegState(KillSrc));
2200 // Moving EFLAGS to / from another register requires a push and a pop.
2201 if (SrcReg == X86::EFLAGS) {
2202 if (X86::GR64RegClass.contains(DestReg)) {
2203 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2204 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2206 } else if (X86::GR32RegClass.contains(DestReg)) {
2207 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2208 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2212 if (DestReg == X86::EFLAGS) {
2213 if (X86::GR64RegClass.contains(SrcReg)) {
2214 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2215 .addReg(SrcReg, getKillRegState(KillSrc));
2216 BuildMI(MBB, MI, DL, get(X86::POPF64));
2218 } else if (X86::GR32RegClass.contains(SrcReg)) {
2219 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2220 .addReg(SrcReg, getKillRegState(KillSrc));
2221 BuildMI(MBB, MI, DL, get(X86::POPF32));
2226 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2227 << " to " << RI.getName(DestReg) << '\n');
2228 llvm_unreachable("Cannot emit physreg copy instruction");
2231 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2232 const TargetRegisterClass *RC,
2233 bool isStackAligned,
2234 const TargetMachine &TM,
2236 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2237 switch (RC->getSize()) {
2239 llvm_unreachable("Unknown spill size");
2241 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2242 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2243 // Copying to or from a physical H register on x86-64 requires a NOREX
2244 // move. Otherwise use a normal move.
2245 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2246 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2247 return load ? X86::MOV8rm : X86::MOV8mr;
2249 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2250 return load ? X86::MOV16rm : X86::MOV16mr;
2252 if (X86::GR32RegClass.hasSubClassEq(RC))
2253 return load ? X86::MOV32rm : X86::MOV32mr;
2254 if (X86::FR32RegClass.hasSubClassEq(RC))
2256 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2257 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2258 if (X86::RFP32RegClass.hasSubClassEq(RC))
2259 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2260 llvm_unreachable("Unknown 4-byte regclass");
2262 if (X86::GR64RegClass.hasSubClassEq(RC))
2263 return load ? X86::MOV64rm : X86::MOV64mr;
2264 if (X86::FR64RegClass.hasSubClassEq(RC))
2266 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2267 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2268 if (X86::VR64RegClass.hasSubClassEq(RC))
2269 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2270 if (X86::RFP64RegClass.hasSubClassEq(RC))
2271 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2272 llvm_unreachable("Unknown 8-byte regclass");
2274 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2275 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2277 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2278 // If stack is realigned we can use aligned stores.
2281 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2282 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2285 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2286 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2289 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2290 // If stack is realigned we can use aligned stores.
2292 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2294 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2298 static unsigned getStoreRegOpcode(unsigned SrcReg,
2299 const TargetRegisterClass *RC,
2300 bool isStackAligned,
2301 TargetMachine &TM) {
2302 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2306 static unsigned getLoadRegOpcode(unsigned DestReg,
2307 const TargetRegisterClass *RC,
2308 bool isStackAligned,
2309 const TargetMachine &TM) {
2310 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2313 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2314 MachineBasicBlock::iterator MI,
2315 unsigned SrcReg, bool isKill, int FrameIdx,
2316 const TargetRegisterClass *RC,
2317 const TargetRegisterInfo *TRI) const {
2318 const MachineFunction &MF = *MBB.getParent();
2319 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2320 "Stack slot too small for store");
2321 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2322 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2323 RI.canRealignStack(MF);
2324 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2325 DebugLoc DL = MBB.findDebugLoc(MI);
2326 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2327 .addReg(SrcReg, getKillRegState(isKill));
2330 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2332 SmallVectorImpl<MachineOperand> &Addr,
2333 const TargetRegisterClass *RC,
2334 MachineInstr::mmo_iterator MMOBegin,
2335 MachineInstr::mmo_iterator MMOEnd,
2336 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2337 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2338 bool isAligned = MMOBegin != MMOEnd &&
2339 (*MMOBegin)->getAlignment() >= Alignment;
2340 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2342 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2343 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2344 MIB.addOperand(Addr[i]);
2345 MIB.addReg(SrcReg, getKillRegState(isKill));
2346 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2347 NewMIs.push_back(MIB);
2351 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2352 MachineBasicBlock::iterator MI,
2353 unsigned DestReg, int FrameIdx,
2354 const TargetRegisterClass *RC,
2355 const TargetRegisterInfo *TRI) const {
2356 const MachineFunction &MF = *MBB.getParent();
2357 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2358 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2359 RI.canRealignStack(MF);
2360 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2361 DebugLoc DL = MBB.findDebugLoc(MI);
2362 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2365 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2366 SmallVectorImpl<MachineOperand> &Addr,
2367 const TargetRegisterClass *RC,
2368 MachineInstr::mmo_iterator MMOBegin,
2369 MachineInstr::mmo_iterator MMOEnd,
2370 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2371 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2372 bool isAligned = MMOBegin != MMOEnd &&
2373 (*MMOBegin)->getAlignment() >= Alignment;
2374 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2376 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2377 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2378 MIB.addOperand(Addr[i]);
2379 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2380 NewMIs.push_back(MIB);
2384 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2385 int FrameIx, uint64_t Offset,
2386 const MDNode *MDPtr,
2387 DebugLoc DL) const {
2389 AM.BaseType = X86AddressMode::FrameIndexBase;
2390 AM.Base.FrameIndex = FrameIx;
2391 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2392 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2396 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2397 const SmallVectorImpl<MachineOperand> &MOs,
2399 const TargetInstrInfo &TII) {
2400 // Create the base instruction with the memory operand as the first part.
2401 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2402 MI->getDebugLoc(), true);
2403 MachineInstrBuilder MIB(NewMI);
2404 unsigned NumAddrOps = MOs.size();
2405 for (unsigned i = 0; i != NumAddrOps; ++i)
2406 MIB.addOperand(MOs[i]);
2407 if (NumAddrOps < 4) // FrameIndex only
2410 // Loop over the rest of the ri operands, converting them over.
2411 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2412 for (unsigned i = 0; i != NumOps; ++i) {
2413 MachineOperand &MO = MI->getOperand(i+2);
2416 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2417 MachineOperand &MO = MI->getOperand(i);
2423 static MachineInstr *FuseInst(MachineFunction &MF,
2424 unsigned Opcode, unsigned OpNo,
2425 const SmallVectorImpl<MachineOperand> &MOs,
2426 MachineInstr *MI, const TargetInstrInfo &TII) {
2427 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2428 MI->getDebugLoc(), true);
2429 MachineInstrBuilder MIB(NewMI);
2431 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2432 MachineOperand &MO = MI->getOperand(i);
2434 assert(MO.isReg() && "Expected to fold into reg operand!");
2435 unsigned NumAddrOps = MOs.size();
2436 for (unsigned i = 0; i != NumAddrOps; ++i)
2437 MIB.addOperand(MOs[i]);
2438 if (NumAddrOps < 4) // FrameIndex only
2447 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2448 const SmallVectorImpl<MachineOperand> &MOs,
2450 MachineFunction &MF = *MI->getParent()->getParent();
2451 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2453 unsigned NumAddrOps = MOs.size();
2454 for (unsigned i = 0; i != NumAddrOps; ++i)
2455 MIB.addOperand(MOs[i]);
2456 if (NumAddrOps < 4) // FrameIndex only
2458 return MIB.addImm(0);
2462 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2463 MachineInstr *MI, unsigned i,
2464 const SmallVectorImpl<MachineOperand> &MOs,
2465 unsigned Size, unsigned Align) const {
2466 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2467 bool isTwoAddrFold = false;
2468 unsigned NumOps = MI->getDesc().getNumOperands();
2469 bool isTwoAddr = NumOps > 1 &&
2470 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2472 // FIXME: AsmPrinter doesn't know how to handle
2473 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2474 if (MI->getOpcode() == X86::ADD32ri &&
2475 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2478 MachineInstr *NewMI = NULL;
2479 // Folding a memory location into the two-address part of a two-address
2480 // instruction is different than folding it other places. It requires
2481 // replacing the *two* registers with the memory location.
2482 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2483 MI->getOperand(0).isReg() &&
2484 MI->getOperand(1).isReg() &&
2485 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2486 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2487 isTwoAddrFold = true;
2488 } else if (i == 0) { // If operand 0
2489 if (MI->getOpcode() == X86::MOV64r0)
2490 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2491 else if (MI->getOpcode() == X86::MOV32r0)
2492 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2493 else if (MI->getOpcode() == X86::MOV16r0)
2494 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2495 else if (MI->getOpcode() == X86::MOV8r0)
2496 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2500 OpcodeTablePtr = &RegOp2MemOpTable0;
2501 } else if (i == 1) {
2502 OpcodeTablePtr = &RegOp2MemOpTable1;
2503 } else if (i == 2) {
2504 OpcodeTablePtr = &RegOp2MemOpTable2;
2507 // If table selected...
2508 if (OpcodeTablePtr) {
2509 // Find the Opcode to fuse
2510 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2511 OpcodeTablePtr->find(MI->getOpcode());
2512 if (I != OpcodeTablePtr->end()) {
2513 unsigned Opcode = I->second.first;
2514 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2515 if (Align < MinAlign)
2517 bool NarrowToMOV32rm = false;
2519 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2520 if (Size < RCSize) {
2521 // Check if it's safe to fold the load. If the size of the object is
2522 // narrower than the load width, then it's not.
2523 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2525 // If this is a 64-bit load, but the spill slot is 32, then we can do
2526 // a 32-bit load which is implicitly zero-extended. This likely is due
2527 // to liveintervalanalysis remat'ing a load from stack slot.
2528 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2530 Opcode = X86::MOV32rm;
2531 NarrowToMOV32rm = true;
2536 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2538 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2540 if (NarrowToMOV32rm) {
2541 // If this is the special case where we use a MOV32rm to load a 32-bit
2542 // value and zero-extend the top bits. Change the destination register
2544 unsigned DstReg = NewMI->getOperand(0).getReg();
2545 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2546 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2549 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2556 if (PrintFailedFusing && !MI->isCopy())
2557 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2561 /// hasPartialRegUpdate - Return true for all instructions that only update
2562 /// the first 32 or 64-bits of the destination register and leave the rest
2563 /// unmodified. This can be used to avoid folding loads if the instructions
2564 /// only update part of the destination register, and the non-updated part is
2565 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2566 /// instructions breaks the partial register dependency and it can improve
2567 /// performance. e.g.:
2569 /// movss (%rdi), %xmm0
2570 /// cvtss2sd %xmm0, %xmm0
2573 /// cvtss2sd (%rdi), %xmm0
2575 /// FIXME: This should be turned into a TSFlags.
2577 static bool hasPartialRegUpdate(unsigned Opcode) {
2579 case X86::CVTSD2SSrr:
2580 case X86::Int_CVTSD2SSrr:
2581 case X86::CVTSS2SDrr:
2582 case X86::Int_CVTSS2SDrr:
2584 case X86::RCPSSr_Int:
2588 case X86::RSQRTSSr_Int:
2590 case X86::SQRTSSr_Int:
2591 // AVX encoded versions
2592 case X86::VCVTSD2SSrr:
2593 case X86::Int_VCVTSD2SSrr:
2594 case X86::VCVTSS2SDrr:
2595 case X86::Int_VCVTSS2SDrr:
2597 case X86::VROUNDSDr:
2598 case X86::VROUNDSSr:
2599 case X86::VRSQRTSSr:
2607 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2609 const SmallVectorImpl<unsigned> &Ops,
2610 int FrameIndex) const {
2611 // Check switch flag
2612 if (NoFusing) return NULL;
2614 // Unless optimizing for size, don't fold to avoid partial
2615 // register update stalls
2616 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2617 hasPartialRegUpdate(MI->getOpcode()))
2620 const MachineFrameInfo *MFI = MF.getFrameInfo();
2621 unsigned Size = MFI->getObjectSize(FrameIndex);
2622 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2623 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2624 unsigned NewOpc = 0;
2625 unsigned RCSize = 0;
2626 switch (MI->getOpcode()) {
2627 default: return NULL;
2628 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2629 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2630 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2631 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2633 // Check if it's safe to fold the load. If the size of the object is
2634 // narrower than the load width, then it's not.
2637 // Change to CMPXXri r, 0 first.
2638 MI->setDesc(get(NewOpc));
2639 MI->getOperand(1).ChangeToImmediate(0);
2640 } else if (Ops.size() != 1)
2643 SmallVector<MachineOperand,4> MOs;
2644 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2645 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2648 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2650 const SmallVectorImpl<unsigned> &Ops,
2651 MachineInstr *LoadMI) const {
2652 // Check switch flag
2653 if (NoFusing) return NULL;
2655 // Unless optimizing for size, don't fold to avoid partial
2656 // register update stalls
2657 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2658 hasPartialRegUpdate(MI->getOpcode()))
2661 // Determine the alignment of the load.
2662 unsigned Alignment = 0;
2663 if (LoadMI->hasOneMemOperand())
2664 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2666 switch (LoadMI->getOpcode()) {
2667 case X86::AVX_SET0PSY:
2668 case X86::AVX_SET0PDY:
2674 case X86::V_SETALLONES:
2675 case X86::AVX_SET0PS:
2676 case X86::AVX_SET0PD:
2677 case X86::AVX_SET0PI:
2678 case X86::AVX_SETALLONES:
2682 case X86::VFsFLD0SD:
2686 case X86::VFsFLD0SS:
2692 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2693 unsigned NewOpc = 0;
2694 switch (MI->getOpcode()) {
2695 default: return NULL;
2696 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2697 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2698 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2699 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2701 // Change to CMPXXri r, 0 first.
2702 MI->setDesc(get(NewOpc));
2703 MI->getOperand(1).ChangeToImmediate(0);
2704 } else if (Ops.size() != 1)
2707 // Make sure the subregisters match.
2708 // Otherwise we risk changing the size of the load.
2709 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2712 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2713 switch (LoadMI->getOpcode()) {
2717 case X86::V_SETALLONES:
2718 case X86::AVX_SET0PS:
2719 case X86::AVX_SET0PD:
2720 case X86::AVX_SET0PI:
2721 case X86::AVX_SET0PSY:
2722 case X86::AVX_SET0PDY:
2723 case X86::AVX_SETALLONES:
2726 case X86::VFsFLD0SD:
2727 case X86::VFsFLD0SS: {
2728 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2729 // Create a constant-pool entry and operands to load from it.
2731 // Medium and large mode can't fold loads this way.
2732 if (TM.getCodeModel() != CodeModel::Small &&
2733 TM.getCodeModel() != CodeModel::Kernel)
2736 // x86-32 PIC requires a PIC base register for constant pools.
2737 unsigned PICBase = 0;
2738 if (TM.getRelocationModel() == Reloc::PIC_) {
2739 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2742 // FIXME: PICBase = getGlobalBaseReg(&MF);
2743 // This doesn't work for several reasons.
2744 // 1. GlobalBaseReg may have been spilled.
2745 // 2. It may not be live at MI.
2749 // Create a constant-pool entry.
2750 MachineConstantPool &MCP = *MF.getConstantPool();
2752 unsigned Opc = LoadMI->getOpcode();
2753 if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS)
2754 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2755 else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD)
2756 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2757 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2758 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2760 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2762 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
2763 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
2764 Constant::getNullValue(Ty);
2765 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2767 // Create operands to load from the constant pool entry.
2768 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2769 MOs.push_back(MachineOperand::CreateImm(1));
2770 MOs.push_back(MachineOperand::CreateReg(0, false));
2771 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2772 MOs.push_back(MachineOperand::CreateReg(0, false));
2776 // Folding a normal load. Just copy the load's address operands.
2777 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2778 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2779 MOs.push_back(LoadMI->getOperand(i));
2783 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2787 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2788 const SmallVectorImpl<unsigned> &Ops) const {
2789 // Check switch flag
2790 if (NoFusing) return 0;
2792 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2793 switch (MI->getOpcode()) {
2794 default: return false;
2801 // FIXME: AsmPrinter doesn't know how to handle
2802 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2803 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2809 if (Ops.size() != 1)
2812 unsigned OpNum = Ops[0];
2813 unsigned Opc = MI->getOpcode();
2814 unsigned NumOps = MI->getDesc().getNumOperands();
2815 bool isTwoAddr = NumOps > 1 &&
2816 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2818 // Folding a memory location into the two-address part of a two-address
2819 // instruction is different than folding it other places. It requires
2820 // replacing the *two* registers with the memory location.
2821 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2822 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2823 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2824 } else if (OpNum == 0) { // If operand 0
2829 case X86::MOV64r0: return true;
2832 OpcodeTablePtr = &RegOp2MemOpTable0;
2833 } else if (OpNum == 1) {
2834 OpcodeTablePtr = &RegOp2MemOpTable1;
2835 } else if (OpNum == 2) {
2836 OpcodeTablePtr = &RegOp2MemOpTable2;
2839 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2841 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2844 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2845 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2846 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2847 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2848 MemOp2RegOpTable.find(MI->getOpcode());
2849 if (I == MemOp2RegOpTable.end())
2851 unsigned Opc = I->second.first;
2852 unsigned Index = I->second.second & TB_INDEX_MASK;
2853 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2854 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2855 if (UnfoldLoad && !FoldedLoad)
2857 UnfoldLoad &= FoldedLoad;
2858 if (UnfoldStore && !FoldedStore)
2860 UnfoldStore &= FoldedStore;
2862 const MCInstrDesc &MCID = get(Opc);
2863 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2864 if (!MI->hasOneMemOperand() &&
2865 RC == &X86::VR128RegClass &&
2866 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2867 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2868 // conservatively assume the address is unaligned. That's bad for
2871 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2872 SmallVector<MachineOperand,2> BeforeOps;
2873 SmallVector<MachineOperand,2> AfterOps;
2874 SmallVector<MachineOperand,4> ImpOps;
2875 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2876 MachineOperand &Op = MI->getOperand(i);
2877 if (i >= Index && i < Index + X86::AddrNumOperands)
2878 AddrOps.push_back(Op);
2879 else if (Op.isReg() && Op.isImplicit())
2880 ImpOps.push_back(Op);
2882 BeforeOps.push_back(Op);
2884 AfterOps.push_back(Op);
2887 // Emit the load instruction.
2889 std::pair<MachineInstr::mmo_iterator,
2890 MachineInstr::mmo_iterator> MMOs =
2891 MF.extractLoadMemRefs(MI->memoperands_begin(),
2892 MI->memoperands_end());
2893 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2895 // Address operands cannot be marked isKill.
2896 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2897 MachineOperand &MO = NewMIs[0]->getOperand(i);
2899 MO.setIsKill(false);
2904 // Emit the data processing instruction.
2905 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
2906 MachineInstrBuilder MIB(DataMI);
2909 MIB.addReg(Reg, RegState::Define);
2910 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2911 MIB.addOperand(BeforeOps[i]);
2914 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2915 MIB.addOperand(AfterOps[i]);
2916 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2917 MachineOperand &MO = ImpOps[i];
2918 MIB.addReg(MO.getReg(),
2919 getDefRegState(MO.isDef()) |
2920 RegState::Implicit |
2921 getKillRegState(MO.isKill()) |
2922 getDeadRegState(MO.isDead()) |
2923 getUndefRegState(MO.isUndef()));
2925 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2926 unsigned NewOpc = 0;
2927 switch (DataMI->getOpcode()) {
2929 case X86::CMP64ri32:
2936 MachineOperand &MO0 = DataMI->getOperand(0);
2937 MachineOperand &MO1 = DataMI->getOperand(1);
2938 if (MO1.getImm() == 0) {
2939 switch (DataMI->getOpcode()) {
2942 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2944 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2946 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2947 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2949 DataMI->setDesc(get(NewOpc));
2950 MO1.ChangeToRegister(MO0.getReg(), false);
2954 NewMIs.push_back(DataMI);
2956 // Emit the store instruction.
2958 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
2959 std::pair<MachineInstr::mmo_iterator,
2960 MachineInstr::mmo_iterator> MMOs =
2961 MF.extractStoreMemRefs(MI->memoperands_begin(),
2962 MI->memoperands_end());
2963 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2970 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2971 SmallVectorImpl<SDNode*> &NewNodes) const {
2972 if (!N->isMachineOpcode())
2975 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2976 MemOp2RegOpTable.find(N->getMachineOpcode());
2977 if (I == MemOp2RegOpTable.end())
2979 unsigned Opc = I->second.first;
2980 unsigned Index = I->second.second & TB_INDEX_MASK;
2981 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2982 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2983 const MCInstrDesc &MCID = get(Opc);
2984 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2985 unsigned NumDefs = MCID.NumDefs;
2986 std::vector<SDValue> AddrOps;
2987 std::vector<SDValue> BeforeOps;
2988 std::vector<SDValue> AfterOps;
2989 DebugLoc dl = N->getDebugLoc();
2990 unsigned NumOps = N->getNumOperands();
2991 for (unsigned i = 0; i != NumOps-1; ++i) {
2992 SDValue Op = N->getOperand(i);
2993 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2994 AddrOps.push_back(Op);
2995 else if (i < Index-NumDefs)
2996 BeforeOps.push_back(Op);
2997 else if (i > Index-NumDefs)
2998 AfterOps.push_back(Op);
3000 SDValue Chain = N->getOperand(NumOps-1);
3001 AddrOps.push_back(Chain);
3003 // Emit the load instruction.
3005 MachineFunction &MF = DAG.getMachineFunction();
3007 EVT VT = *RC->vt_begin();
3008 std::pair<MachineInstr::mmo_iterator,
3009 MachineInstr::mmo_iterator> MMOs =
3010 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3011 cast<MachineSDNode>(N)->memoperands_end());
3012 if (!(*MMOs.first) &&
3013 RC == &X86::VR128RegClass &&
3014 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3015 // Do not introduce a slow unaligned load.
3017 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3018 bool isAligned = (*MMOs.first) &&
3019 (*MMOs.first)->getAlignment() >= Alignment;
3020 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3021 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3022 NewNodes.push_back(Load);
3024 // Preserve memory reference information.
3025 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3028 // Emit the data processing instruction.
3029 std::vector<EVT> VTs;
3030 const TargetRegisterClass *DstRC = 0;
3031 if (MCID.getNumDefs() > 0) {
3032 DstRC = getRegClass(MCID, 0, &RI);
3033 VTs.push_back(*DstRC->vt_begin());
3035 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3036 EVT VT = N->getValueType(i);
3037 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3041 BeforeOps.push_back(SDValue(Load, 0));
3042 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3043 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3045 NewNodes.push_back(NewNode);
3047 // Emit the store instruction.
3050 AddrOps.push_back(SDValue(NewNode, 0));
3051 AddrOps.push_back(Chain);
3052 std::pair<MachineInstr::mmo_iterator,
3053 MachineInstr::mmo_iterator> MMOs =
3054 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3055 cast<MachineSDNode>(N)->memoperands_end());
3056 if (!(*MMOs.first) &&
3057 RC == &X86::VR128RegClass &&
3058 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3059 // Do not introduce a slow unaligned store.
3061 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3062 bool isAligned = (*MMOs.first) &&
3063 (*MMOs.first)->getAlignment() >= Alignment;
3064 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3067 &AddrOps[0], AddrOps.size());
3068 NewNodes.push_back(Store);
3070 // Preserve memory reference information.
3071 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3077 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3078 bool UnfoldLoad, bool UnfoldStore,
3079 unsigned *LoadRegIndex) const {
3080 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3081 MemOp2RegOpTable.find(Opc);
3082 if (I == MemOp2RegOpTable.end())
3084 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3085 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3086 if (UnfoldLoad && !FoldedLoad)
3088 if (UnfoldStore && !FoldedStore)
3091 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3092 return I->second.first;
3096 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3097 int64_t &Offset1, int64_t &Offset2) const {
3098 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3100 unsigned Opc1 = Load1->getMachineOpcode();
3101 unsigned Opc2 = Load2->getMachineOpcode();
3103 default: return false;
3113 case X86::MMX_MOVD64rm:
3114 case X86::MMX_MOVQ64rm:
3115 case X86::FsMOVAPSrm:
3116 case X86::FsMOVAPDrm:
3122 // AVX load instructions
3125 case X86::FsVMOVAPSrm:
3126 case X86::FsVMOVAPDrm:
3127 case X86::VMOVAPSrm:
3128 case X86::VMOVUPSrm:
3129 case X86::VMOVAPDrm:
3130 case X86::VMOVDQArm:
3131 case X86::VMOVDQUrm:
3132 case X86::VMOVAPSYrm:
3133 case X86::VMOVUPSYrm:
3134 case X86::VMOVAPDYrm:
3135 case X86::VMOVDQAYrm:
3136 case X86::VMOVDQUYrm:
3140 default: return false;
3150 case X86::MMX_MOVD64rm:
3151 case X86::MMX_MOVQ64rm:
3152 case X86::FsMOVAPSrm:
3153 case X86::FsMOVAPDrm:
3159 // AVX load instructions
3162 case X86::FsVMOVAPSrm:
3163 case X86::FsVMOVAPDrm:
3164 case X86::VMOVAPSrm:
3165 case X86::VMOVUPSrm:
3166 case X86::VMOVAPDrm:
3167 case X86::VMOVDQArm:
3168 case X86::VMOVDQUrm:
3169 case X86::VMOVAPSYrm:
3170 case X86::VMOVUPSYrm:
3171 case X86::VMOVAPDYrm:
3172 case X86::VMOVDQAYrm:
3173 case X86::VMOVDQUYrm:
3177 // Check if chain operands and base addresses match.
3178 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3179 Load1->getOperand(5) != Load2->getOperand(5))
3181 // Segment operands should match as well.
3182 if (Load1->getOperand(4) != Load2->getOperand(4))
3184 // Scale should be 1, Index should be Reg0.
3185 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3186 Load1->getOperand(2) == Load2->getOperand(2)) {
3187 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3190 // Now let's examine the displacements.
3191 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3192 isa<ConstantSDNode>(Load2->getOperand(3))) {
3193 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3194 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3201 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3202 int64_t Offset1, int64_t Offset2,
3203 unsigned NumLoads) const {
3204 assert(Offset2 > Offset1);
3205 if ((Offset2 - Offset1) / 8 > 64)
3208 unsigned Opc1 = Load1->getMachineOpcode();
3209 unsigned Opc2 = Load2->getMachineOpcode();
3211 return false; // FIXME: overly conservative?
3218 case X86::MMX_MOVD64rm:
3219 case X86::MMX_MOVQ64rm:
3223 EVT VT = Load1->getValueType(0);
3224 switch (VT.getSimpleVT().SimpleTy) {
3226 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3227 // have 16 of them to play with.
3228 if (TM.getSubtargetImpl()->is64Bit()) {
3231 } else if (NumLoads) {
3251 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3252 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3253 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3254 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3256 Cond[0].setImm(GetOppositeBranchCondition(CC));
3261 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3262 // FIXME: Return false for x87 stack register classes for now. We can't
3263 // allow any loads of these registers before FpGet_ST0_80.
3264 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3265 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3268 /// getGlobalBaseReg - Return a virtual register initialized with the
3269 /// the global base register value. Output instructions required to
3270 /// initialize the register in the function entry block, if necessary.
3272 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3274 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3275 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3276 "X86-64 PIC uses RIP relative addressing");
3278 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3279 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3280 if (GlobalBaseReg != 0)
3281 return GlobalBaseReg;
3283 // Create the register. The code to initialize it is inserted
3284 // later, by the CGBR pass (below).
3285 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3286 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3287 X86FI->setGlobalBaseReg(GlobalBaseReg);
3288 return GlobalBaseReg;
3291 // These are the replaceable SSE instructions. Some of these have Int variants
3292 // that we don't include here. We don't want to replace instructions selected
3294 static const unsigned ReplaceableInstrs[][3] = {
3295 //PackedSingle PackedDouble PackedInt
3296 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3297 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3298 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3299 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3300 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3301 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3302 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3303 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3304 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3305 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3306 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3307 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3308 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3309 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3310 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3311 // AVX 128-bit support
3312 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3313 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3314 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3315 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3316 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3317 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3318 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3319 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3320 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3321 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3322 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3323 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3324 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3325 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3326 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3327 // AVX 256-bit support
3328 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3329 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3330 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3331 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3332 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3333 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
3336 // FIXME: Some shuffle and unpack instructions have equivalents in different
3337 // domains, but they require a bit more work than just switching opcodes.
3339 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3340 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3341 if (ReplaceableInstrs[i][domain-1] == opcode)
3342 return ReplaceableInstrs[i];
3346 std::pair<uint16_t, uint16_t>
3347 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3348 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3349 return std::make_pair(domain,
3350 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3353 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3354 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3355 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3356 assert(dom && "Not an SSE instruction");
3357 const unsigned *table = lookup(MI->getOpcode(), dom);
3358 assert(table && "Cannot change domain");
3359 MI->setDesc(get(table[Domain-1]));
3362 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3363 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3364 NopInst.setOpcode(X86::NOOP);
3367 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3369 default: return false;
3371 case X86::DIVSDrm_Int:
3373 case X86::DIVSDrr_Int:
3375 case X86::DIVSSrm_Int:
3377 case X86::DIVSSrr_Int:
3379 case X86::SQRTPDm_Int:
3381 case X86::SQRTPDr_Int:
3383 case X86::SQRTPSm_Int:
3385 case X86::SQRTPSr_Int:
3387 case X86::SQRTSDm_Int:
3389 case X86::SQRTSDr_Int:
3391 case X86::SQRTSSm_Int:
3393 case X86::SQRTSSr_Int:
3394 // AVX instructions with high latency
3396 case X86::VDIVSDrm_Int:
3398 case X86::VDIVSDrr_Int:
3400 case X86::VDIVSSrm_Int:
3402 case X86::VDIVSSrr_Int:
3404 case X86::VSQRTPDm_Int:
3406 case X86::VSQRTPDr_Int:
3408 case X86::VSQRTPSm_Int:
3410 case X86::VSQRTPSr_Int:
3412 case X86::VSQRTSDm_Int:
3415 case X86::VSQRTSSm_Int:
3422 hasHighOperandLatency(const InstrItineraryData *ItinData,
3423 const MachineRegisterInfo *MRI,
3424 const MachineInstr *DefMI, unsigned DefIdx,
3425 const MachineInstr *UseMI, unsigned UseIdx) const {
3426 return isHighLatencyDef(DefMI->getOpcode());
3430 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3431 /// global base register for x86-32.
3432 struct CGBR : public MachineFunctionPass {
3434 CGBR() : MachineFunctionPass(ID) {}
3436 virtual bool runOnMachineFunction(MachineFunction &MF) {
3437 const X86TargetMachine *TM =
3438 static_cast<const X86TargetMachine *>(&MF.getTarget());
3440 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3441 "X86-64 PIC uses RIP relative addressing");
3443 // Only emit a global base reg in PIC mode.
3444 if (TM->getRelocationModel() != Reloc::PIC_)
3447 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3448 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3450 // If we didn't need a GlobalBaseReg, don't insert code.
3451 if (GlobalBaseReg == 0)
3454 // Insert the set of GlobalBaseReg into the first MBB of the function
3455 MachineBasicBlock &FirstMBB = MF.front();
3456 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3457 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3458 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3459 const X86InstrInfo *TII = TM->getInstrInfo();
3462 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3463 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3467 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3468 // only used in JIT code emission as displacement to pc.
3469 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3471 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3472 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3473 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3474 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3475 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3476 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3477 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3483 virtual const char *getPassName() const {
3484 return "X86 PIC Global Base Reg Initialization";
3487 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3488 AU.setPreservesCFG();
3489 MachineFunctionPass::getAnalysisUsage(AU);
3496 llvm::createGlobalBaseRegPass() { return new CGBR(); }