1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "X86GenInstrInfo.inc"
21 X86InstrInfo::X86InstrInfo()
22 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
26 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 MachineOpCode oc = MI.getOpcode();
30 if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
32 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
33 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
34 assert(MI.getNumOperands() == 2 &&
35 MI.getOperand(0).isRegister() &&
36 MI.getOperand(1).isRegister() &&
37 "invalid register-register move instruction");
38 sourceReg = MI.getOperand(1).getReg();
39 destReg = MI.getOperand(0).getReg();
45 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
46 int &FrameIndex) const {
47 switch (MI->getOpcode()) {
55 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
56 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
57 MI->getOperand(2).getImmedValue() == 1 &&
58 MI->getOperand(3).getReg() == 0 &&
59 MI->getOperand(4).getImmedValue() == 0) {
60 FrameIndex = MI->getOperand(1).getFrameIndex();
61 return MI->getOperand(0).getReg();
68 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
69 int &FrameIndex) const {
70 switch (MI->getOpcode()) {
78 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
79 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
80 MI->getOperand(1).getImmedValue() == 1 &&
81 MI->getOperand(2).getReg() == 0 &&
82 MI->getOperand(3).getImmedValue() == 0) {
83 FrameIndex = MI->getOperand(0).getFrameIndex();
84 return MI->getOperand(4).getReg();
93 /// convertToThreeAddress - This method must be implemented by targets that
94 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
95 /// may be able to convert a two-address instruction into a true
96 /// three-address instruction on demand. This allows the X86 target (for
97 /// example) to convert ADD and SHL instructions into LEA instructions if they
98 /// would require register copies due to two-addressness.
100 /// This method returns a null pointer if the transformation cannot be
101 /// performed, otherwise it returns the new instruction.
103 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
104 // All instructions input are two-addr instructions. Get the known operands.
105 unsigned Dest = MI->getOperand(0).getReg();
106 unsigned Src = MI->getOperand(1).getReg();
108 // FIXME: None of these instructions are promotable to LEAs without
109 // additional information. In particular, LEA doesn't set the flags that
110 // add and inc do. :(
113 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
114 // we have subtarget support, enable the 16-bit LEA generation here.
115 bool DisableLEA16 = true;
117 switch (MI->getOpcode()) {
119 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
120 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
122 if (DisableLEA16) return 0;
123 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
124 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
126 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
127 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
129 if (DisableLEA16) return 0;
130 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
131 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
133 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
134 return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
135 MI->getOperand(2).getReg());
137 if (DisableLEA16) return 0;
138 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
139 return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
140 MI->getOperand(2).getReg());
142 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
143 if (MI->getOperand(2).isImmediate())
144 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
145 MI->getOperand(2).getImmedValue());
148 if (DisableLEA16) return 0;
149 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
150 if (MI->getOperand(2).isImmediate())
151 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
152 MI->getOperand(2).getImmedValue());
156 if (DisableLEA16) return 0;
158 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
159 "Unknown shl instruction!");
160 unsigned ShAmt = MI->getOperand(2).getImmedValue();
161 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
163 AM.Scale = 1 << ShAmt;
165 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
166 return addFullAddress(BuildMI(Opc, 5, Dest), AM);
174 /// commuteInstruction - We have a few instructions that must be hacked on to
177 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
178 switch (MI->getOpcode()) {
179 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
180 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
181 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
182 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
185 switch (MI->getOpcode()) {
186 default: assert(0 && "Unreachable!");
187 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
188 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
189 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
190 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
192 unsigned Amt = MI->getOperand(3).getImmedValue();
193 unsigned A = MI->getOperand(0).getReg();
194 unsigned B = MI->getOperand(1).getReg();
195 unsigned C = MI->getOperand(2).getReg();
196 return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
199 return TargetInstrInfo::commuteInstruction(MI);
204 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
205 MachineBasicBlock& TMBB) const {
206 BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
209 MachineBasicBlock::iterator
210 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
211 unsigned Opcode = MI->getOpcode();
212 assert(isBranch(Opcode) && "MachineInstr must be a branch");
215 default: assert(0 && "Cannot reverse unconditional branches!");
216 case X86::JB: ROpcode = X86::JAE; break;
217 case X86::JAE: ROpcode = X86::JB; break;
218 case X86::JE: ROpcode = X86::JNE; break;
219 case X86::JNE: ROpcode = X86::JE; break;
220 case X86::JBE: ROpcode = X86::JA; break;
221 case X86::JA: ROpcode = X86::JBE; break;
222 case X86::JS: ROpcode = X86::JNS; break;
223 case X86::JNS: ROpcode = X86::JS; break;
224 case X86::JP: ROpcode = X86::JNP; break;
225 case X86::JNP: ROpcode = X86::JP; break;
226 case X86::JL: ROpcode = X86::JGE; break;
227 case X86::JGE: ROpcode = X86::JL; break;
228 case X86::JLE: ROpcode = X86::JG; break;
229 case X86::JG: ROpcode = X86::JLE; break;
231 MachineBasicBlock* MBB = MI->getParent();
232 MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
233 return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);