1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
27 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
28 : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
29 TM(tm), RI(tm, *this) {
32 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
34 unsigned& destReg) const {
35 MachineOpCode oc = MI.getOpcode();
36 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
37 oc == X86::MOV32rr || oc == X86::MOV64rr ||
38 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
39 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
40 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
41 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
42 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
43 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
44 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
45 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
46 assert(MI.getNumOperands() >= 2 &&
47 MI.getOperand(0).isRegister() &&
48 MI.getOperand(1).isRegister() &&
49 "invalid register-register move instruction");
50 sourceReg = MI.getOperand(1).getReg();
51 destReg = MI.getOperand(0).getReg();
57 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
58 int &FrameIndex) const {
59 switch (MI->getOpcode()) {
72 case X86::MMX_MOVD64rm:
73 case X86::MMX_MOVQ64rm:
74 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
75 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
76 MI->getOperand(2).getImmedValue() == 1 &&
77 MI->getOperand(3).getReg() == 0 &&
78 MI->getOperand(4).getImmedValue() == 0) {
79 FrameIndex = MI->getOperand(1).getFrameIndex();
80 return MI->getOperand(0).getReg();
87 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
88 int &FrameIndex) const {
89 switch (MI->getOpcode()) {
102 case X86::MMX_MOVD64mr:
103 case X86::MMX_MOVQ64mr:
104 case X86::MMX_MOVNTQmr:
105 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
106 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
107 MI->getOperand(1).getImmedValue() == 1 &&
108 MI->getOperand(2).getReg() == 0 &&
109 MI->getOperand(3).getImmedValue() == 0) {
110 FrameIndex = MI->getOperand(0).getFrameIndex();
111 return MI->getOperand(4).getReg();
119 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
120 switch (MI->getOpcode()) {
133 case X86::MMX_MOVD64rm:
134 case X86::MMX_MOVQ64rm:
135 // Loads from constant pools are trivially rematerializable.
136 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
137 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
138 MI->getOperand(1).getReg() == 0 &&
139 MI->getOperand(2).getImmedValue() == 1 &&
140 MI->getOperand(3).getReg() == 0;
142 // All other instructions marked M_REMATERIALIZABLE are always trivially
147 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
148 /// is not marked dead.
149 static bool hasLiveCondCodeDef(MachineInstr *MI) {
150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
151 MachineOperand &MO = MI->getOperand(i);
152 if (MO.isRegister() && MO.isDef() &&
153 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
160 /// convertToThreeAddress - This method must be implemented by targets that
161 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
162 /// may be able to convert a two-address instruction into a true
163 /// three-address instruction on demand. This allows the X86 target (for
164 /// example) to convert ADD and SHL instructions into LEA instructions if they
165 /// would require register copies due to two-addressness.
167 /// This method returns a null pointer if the transformation cannot be
168 /// performed, otherwise it returns the new instruction.
171 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
172 MachineBasicBlock::iterator &MBBI,
173 LiveVariables &LV) const {
174 MachineInstr *MI = MBBI;
175 // All instructions input are two-addr instructions. Get the known operands.
176 unsigned Dest = MI->getOperand(0).getReg();
177 unsigned Src = MI->getOperand(1).getReg();
179 MachineInstr *NewMI = NULL;
180 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
181 // we have better subtarget support, enable the 16-bit LEA generation here.
182 bool DisableLEA16 = true;
184 unsigned MIOpc = MI->getOpcode();
186 case X86::SHUFPSrri: {
187 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
188 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
190 unsigned A = MI->getOperand(0).getReg();
191 unsigned B = MI->getOperand(1).getReg();
192 unsigned C = MI->getOperand(2).getReg();
193 unsigned M = MI->getOperand(3).getImm();
194 if (B != C) return 0;
195 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
199 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
200 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
201 // the flags produced by a shift yet, so this is safe.
202 unsigned Dest = MI->getOperand(0).getReg();
203 unsigned Src = MI->getOperand(1).getReg();
204 unsigned ShAmt = MI->getOperand(2).getImm();
205 if (ShAmt == 0 || ShAmt >= 4) return 0;
207 NewMI = BuildMI(get(X86::LEA64r), Dest)
208 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
212 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
213 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
214 // the flags produced by a shift yet, so this is safe.
215 unsigned Dest = MI->getOperand(0).getReg();
216 unsigned Src = MI->getOperand(1).getReg();
217 unsigned ShAmt = MI->getOperand(2).getImm();
218 if (ShAmt == 0 || ShAmt >= 4) return 0;
220 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
221 X86::LEA64_32r : X86::LEA32r;
222 NewMI = BuildMI(get(Opc), Dest)
223 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
227 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
228 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
229 // the flags produced by a shift yet, so this is safe.
230 unsigned Dest = MI->getOperand(0).getReg();
231 unsigned Src = MI->getOperand(1).getReg();
232 unsigned ShAmt = MI->getOperand(2).getImm();
233 if (ShAmt == 0 || ShAmt >= 4) return 0;
236 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
237 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
238 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
239 ? X86::LEA64_32r : X86::LEA32r;
240 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
241 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
244 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
245 Ins->copyKillDeadInfo(MI);
247 NewMI = BuildMI(get(Opc), leaOutReg)
248 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
251 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
252 Ext->copyKillDeadInfo(MI);
254 MFI->insert(MBBI, Ins); // Insert the insert_subreg
255 LV.instructionChanged(MI, NewMI); // Update live variables
256 LV.addVirtualRegisterKilled(leaInReg, NewMI);
257 MFI->insert(MBBI, NewMI); // Insert the new inst
258 LV.addVirtualRegisterKilled(leaOutReg, Ext);
259 MFI->insert(MBBI, Ext); // Insert the extract_subreg
262 NewMI = BuildMI(get(X86::LEA16r), Dest)
263 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
268 // The following opcodes also sets the condition code register(s). Only
269 // convert them to equivalent lea if the condition code register def's
271 if (hasLiveCondCodeDef(MI))
278 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
279 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : X86::LEA32r;
280 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
285 if (DisableLEA16) return 0;
286 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
287 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
291 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
292 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r : X86::LEA32r;
293 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
298 if (DisableLEA16) return 0;
299 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
300 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
304 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
305 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r : X86::LEA32r;
306 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
307 MI->getOperand(2).getReg());
311 if (DisableLEA16) return 0;
312 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
313 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
314 MI->getOperand(2).getReg());
318 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
319 if (MI->getOperand(2).isImmediate())
320 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
321 MI->getOperand(2).getImmedValue());
325 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
326 if (MI->getOperand(2).isImmediate())
327 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
328 MI->getOperand(2).getImmedValue());
332 if (DisableLEA16) return 0;
333 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
334 if (MI->getOperand(2).isImmediate())
335 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
336 MI->getOperand(2).getImmedValue());
339 if (DisableLEA16) return 0;
342 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
343 "Unknown shl instruction!");
344 unsigned ShAmt = MI->getOperand(2).getImmedValue();
345 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
347 AM.Scale = 1 << ShAmt;
349 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
350 : (MIOpc == X86::SHL32ri ? X86::LEA32r : X86::LEA16r);
351 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
359 NewMI->copyKillDeadInfo(MI);
360 LV.instructionChanged(MI, NewMI); // Update live variables
361 MFI->insert(MBBI, NewMI); // Insert the new inst
365 /// commuteInstruction - We have a few instructions that must be hacked on to
368 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
369 // FIXME: Can commute cmoves by changing the condition!
370 switch (MI->getOpcode()) {
371 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
372 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
373 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
374 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
375 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
376 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
379 switch (MI->getOpcode()) {
380 default: assert(0 && "Unreachable!");
381 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
382 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
383 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
384 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
385 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
386 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
388 unsigned Amt = MI->getOperand(3).getImmedValue();
389 unsigned A = MI->getOperand(0).getReg();
390 unsigned B = MI->getOperand(1).getReg();
391 unsigned C = MI->getOperand(2).getReg();
392 bool BisKill = MI->getOperand(1).isKill();
393 bool CisKill = MI->getOperand(2).isKill();
394 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
395 .addReg(B, false, false, BisKill).addImm(Size-Amt);
398 return TargetInstrInfo::commuteInstruction(MI);
402 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
404 default: return X86::COND_INVALID;
405 case X86::JE: return X86::COND_E;
406 case X86::JNE: return X86::COND_NE;
407 case X86::JL: return X86::COND_L;
408 case X86::JLE: return X86::COND_LE;
409 case X86::JG: return X86::COND_G;
410 case X86::JGE: return X86::COND_GE;
411 case X86::JB: return X86::COND_B;
412 case X86::JBE: return X86::COND_BE;
413 case X86::JA: return X86::COND_A;
414 case X86::JAE: return X86::COND_AE;
415 case X86::JS: return X86::COND_S;
416 case X86::JNS: return X86::COND_NS;
417 case X86::JP: return X86::COND_P;
418 case X86::JNP: return X86::COND_NP;
419 case X86::JO: return X86::COND_O;
420 case X86::JNO: return X86::COND_NO;
424 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
426 default: assert(0 && "Illegal condition code!");
427 case X86::COND_E: return X86::JE;
428 case X86::COND_NE: return X86::JNE;
429 case X86::COND_L: return X86::JL;
430 case X86::COND_LE: return X86::JLE;
431 case X86::COND_G: return X86::JG;
432 case X86::COND_GE: return X86::JGE;
433 case X86::COND_B: return X86::JB;
434 case X86::COND_BE: return X86::JBE;
435 case X86::COND_A: return X86::JA;
436 case X86::COND_AE: return X86::JAE;
437 case X86::COND_S: return X86::JS;
438 case X86::COND_NS: return X86::JNS;
439 case X86::COND_P: return X86::JP;
440 case X86::COND_NP: return X86::JNP;
441 case X86::COND_O: return X86::JO;
442 case X86::COND_NO: return X86::JNO;
446 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
447 /// e.g. turning COND_E to COND_NE.
448 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
450 default: assert(0 && "Illegal condition code!");
451 case X86::COND_E: return X86::COND_NE;
452 case X86::COND_NE: return X86::COND_E;
453 case X86::COND_L: return X86::COND_GE;
454 case X86::COND_LE: return X86::COND_G;
455 case X86::COND_G: return X86::COND_LE;
456 case X86::COND_GE: return X86::COND_L;
457 case X86::COND_B: return X86::COND_AE;
458 case X86::COND_BE: return X86::COND_A;
459 case X86::COND_A: return X86::COND_BE;
460 case X86::COND_AE: return X86::COND_B;
461 case X86::COND_S: return X86::COND_NS;
462 case X86::COND_NS: return X86::COND_S;
463 case X86::COND_P: return X86::COND_NP;
464 case X86::COND_NP: return X86::COND_P;
465 case X86::COND_O: return X86::COND_NO;
466 case X86::COND_NO: return X86::COND_O;
470 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
471 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
472 if (TID->Flags & M_TERMINATOR_FLAG) {
473 // Conditional branch is a special case.
474 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
476 if ((TID->Flags & M_PREDICABLE) == 0)
478 return !isPredicated(MI);
483 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
484 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
485 const X86InstrInfo &TII) {
486 if (MI->getOpcode() == X86::FP_REG_KILL)
488 return TII.isUnpredicatedTerminator(MI);
491 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
492 MachineBasicBlock *&TBB,
493 MachineBasicBlock *&FBB,
494 std::vector<MachineOperand> &Cond) const {
495 // If the block has no terminators, it just falls into the block after it.
496 MachineBasicBlock::iterator I = MBB.end();
497 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
500 // Get the last instruction in the block.
501 MachineInstr *LastInst = I;
503 // If there is only one terminator instruction, process it.
504 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
505 if (!isBranch(LastInst->getOpcode()))
508 // If the block ends with a branch there are 3 possibilities:
509 // it's an unconditional, conditional, or indirect branch.
511 if (LastInst->getOpcode() == X86::JMP) {
512 TBB = LastInst->getOperand(0).getMachineBasicBlock();
515 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
516 if (BranchCode == X86::COND_INVALID)
517 return true; // Can't handle indirect branch.
519 // Otherwise, block ends with fall-through condbranch.
520 TBB = LastInst->getOperand(0).getMachineBasicBlock();
521 Cond.push_back(MachineOperand::CreateImm(BranchCode));
525 // Get the instruction before it if it's a terminator.
526 MachineInstr *SecondLastInst = I;
528 // If there are three terminators, we don't know what sort of block this is.
529 if (SecondLastInst && I != MBB.begin() &&
530 isBrAnalysisUnpredicatedTerminator(--I, *this))
533 // If the block ends with X86::JMP and a conditional branch, handle it.
534 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
535 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
536 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
537 Cond.push_back(MachineOperand::CreateImm(BranchCode));
538 FBB = LastInst->getOperand(0).getMachineBasicBlock();
542 // If the block ends with two X86::JMPs, handle it. The second one is not
543 // executed, so remove it.
544 if (SecondLastInst->getOpcode() == X86::JMP &&
545 LastInst->getOpcode() == X86::JMP) {
546 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
548 I->eraseFromParent();
552 // Otherwise, can't handle this.
556 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
557 MachineBasicBlock::iterator I = MBB.end();
558 if (I == MBB.begin()) return 0;
560 if (I->getOpcode() != X86::JMP &&
561 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
564 // Remove the branch.
565 I->eraseFromParent();
569 if (I == MBB.begin()) return 1;
571 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
574 // Remove the branch.
575 I->eraseFromParent();
580 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
581 MachineBasicBlock *FBB,
582 const std::vector<MachineOperand> &Cond) const {
583 // Shouldn't be a fall through.
584 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
585 assert((Cond.size() == 1 || Cond.size() == 0) &&
586 "X86 branch conditions have one component!");
588 if (FBB == 0) { // One way branch.
590 // Unconditional branch?
591 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
593 // Conditional branch.
594 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
595 BuildMI(&MBB, get(Opc)).addMBB(TBB);
600 // Two-way Conditional branch.
601 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
602 BuildMI(&MBB, get(Opc)).addMBB(TBB);
603 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
607 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
608 if (MBB.empty()) return false;
610 switch (MBB.back().getOpcode()) {
611 case X86::RET: // Return.
616 case X86::JMP: // Uncond branch.
617 case X86::JMP32r: // Indirect branch.
618 case X86::JMP64r: // Indirect branch (64-bit).
619 case X86::JMP32m: // Indirect branch through mem.
620 case X86::JMP64m: // Indirect branch through mem (64-bit).
622 default: return false;
627 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
628 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
629 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
633 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
634 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
635 if (Subtarget->is64Bit())
636 return &X86::GR64RegClass;
638 return &X86::GR32RegClass;