1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
33 NoFusing("disable-spill-fusing",
34 cl::desc("Disable fusing of spill code into instructions"));
36 PrintFailedFusing("print-failed-fuse-candidates",
37 cl::desc("Print instructions that the allocator wants to"
38 " fuse, but the X86 backend currently can't"),
42 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
43 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
44 TM(tm), RI(tm, *this) {
45 SmallVector<unsigned,16> AmbEntries;
46 static const unsigned OpTbl2Addr[][2] = {
47 { X86::ADC32ri, X86::ADC32mi },
48 { X86::ADC32ri8, X86::ADC32mi8 },
49 { X86::ADC32rr, X86::ADC32mr },
50 { X86::ADC64ri32, X86::ADC64mi32 },
51 { X86::ADC64ri8, X86::ADC64mi8 },
52 { X86::ADC64rr, X86::ADC64mr },
53 { X86::ADD16ri, X86::ADD16mi },
54 { X86::ADD16ri8, X86::ADD16mi8 },
55 { X86::ADD16rr, X86::ADD16mr },
56 { X86::ADD32ri, X86::ADD32mi },
57 { X86::ADD32ri8, X86::ADD32mi8 },
58 { X86::ADD32rr, X86::ADD32mr },
59 { X86::ADD64ri32, X86::ADD64mi32 },
60 { X86::ADD64ri8, X86::ADD64mi8 },
61 { X86::ADD64rr, X86::ADD64mr },
62 { X86::ADD8ri, X86::ADD8mi },
63 { X86::ADD8rr, X86::ADD8mr },
64 { X86::AND16ri, X86::AND16mi },
65 { X86::AND16ri8, X86::AND16mi8 },
66 { X86::AND16rr, X86::AND16mr },
67 { X86::AND32ri, X86::AND32mi },
68 { X86::AND32ri8, X86::AND32mi8 },
69 { X86::AND32rr, X86::AND32mr },
70 { X86::AND64ri32, X86::AND64mi32 },
71 { X86::AND64ri8, X86::AND64mi8 },
72 { X86::AND64rr, X86::AND64mr },
73 { X86::AND8ri, X86::AND8mi },
74 { X86::AND8rr, X86::AND8mr },
75 { X86::DEC16r, X86::DEC16m },
76 { X86::DEC32r, X86::DEC32m },
77 { X86::DEC64_16r, X86::DEC64_16m },
78 { X86::DEC64_32r, X86::DEC64_32m },
79 { X86::DEC64r, X86::DEC64m },
80 { X86::DEC8r, X86::DEC8m },
81 { X86::INC16r, X86::INC16m },
82 { X86::INC32r, X86::INC32m },
83 { X86::INC64_16r, X86::INC64_16m },
84 { X86::INC64_32r, X86::INC64_32m },
85 { X86::INC64r, X86::INC64m },
86 { X86::INC8r, X86::INC8m },
87 { X86::NEG16r, X86::NEG16m },
88 { X86::NEG32r, X86::NEG32m },
89 { X86::NEG64r, X86::NEG64m },
90 { X86::NEG8r, X86::NEG8m },
91 { X86::NOT16r, X86::NOT16m },
92 { X86::NOT32r, X86::NOT32m },
93 { X86::NOT64r, X86::NOT64m },
94 { X86::NOT8r, X86::NOT8m },
95 { X86::OR16ri, X86::OR16mi },
96 { X86::OR16ri8, X86::OR16mi8 },
97 { X86::OR16rr, X86::OR16mr },
98 { X86::OR32ri, X86::OR32mi },
99 { X86::OR32ri8, X86::OR32mi8 },
100 { X86::OR32rr, X86::OR32mr },
101 { X86::OR64ri32, X86::OR64mi32 },
102 { X86::OR64ri8, X86::OR64mi8 },
103 { X86::OR64rr, X86::OR64mr },
104 { X86::OR8ri, X86::OR8mi },
105 { X86::OR8rr, X86::OR8mr },
106 { X86::ROL16r1, X86::ROL16m1 },
107 { X86::ROL16rCL, X86::ROL16mCL },
108 { X86::ROL16ri, X86::ROL16mi },
109 { X86::ROL32r1, X86::ROL32m1 },
110 { X86::ROL32rCL, X86::ROL32mCL },
111 { X86::ROL32ri, X86::ROL32mi },
112 { X86::ROL64r1, X86::ROL64m1 },
113 { X86::ROL64rCL, X86::ROL64mCL },
114 { X86::ROL64ri, X86::ROL64mi },
115 { X86::ROL8r1, X86::ROL8m1 },
116 { X86::ROL8rCL, X86::ROL8mCL },
117 { X86::ROL8ri, X86::ROL8mi },
118 { X86::ROR16r1, X86::ROR16m1 },
119 { X86::ROR16rCL, X86::ROR16mCL },
120 { X86::ROR16ri, X86::ROR16mi },
121 { X86::ROR32r1, X86::ROR32m1 },
122 { X86::ROR32rCL, X86::ROR32mCL },
123 { X86::ROR32ri, X86::ROR32mi },
124 { X86::ROR64r1, X86::ROR64m1 },
125 { X86::ROR64rCL, X86::ROR64mCL },
126 { X86::ROR64ri, X86::ROR64mi },
127 { X86::ROR8r1, X86::ROR8m1 },
128 { X86::ROR8rCL, X86::ROR8mCL },
129 { X86::ROR8ri, X86::ROR8mi },
130 { X86::SAR16r1, X86::SAR16m1 },
131 { X86::SAR16rCL, X86::SAR16mCL },
132 { X86::SAR16ri, X86::SAR16mi },
133 { X86::SAR32r1, X86::SAR32m1 },
134 { X86::SAR32rCL, X86::SAR32mCL },
135 { X86::SAR32ri, X86::SAR32mi },
136 { X86::SAR64r1, X86::SAR64m1 },
137 { X86::SAR64rCL, X86::SAR64mCL },
138 { X86::SAR64ri, X86::SAR64mi },
139 { X86::SAR8r1, X86::SAR8m1 },
140 { X86::SAR8rCL, X86::SAR8mCL },
141 { X86::SAR8ri, X86::SAR8mi },
142 { X86::SBB32ri, X86::SBB32mi },
143 { X86::SBB32ri8, X86::SBB32mi8 },
144 { X86::SBB32rr, X86::SBB32mr },
145 { X86::SBB64ri32, X86::SBB64mi32 },
146 { X86::SBB64ri8, X86::SBB64mi8 },
147 { X86::SBB64rr, X86::SBB64mr },
148 { X86::SHL16rCL, X86::SHL16mCL },
149 { X86::SHL16ri, X86::SHL16mi },
150 { X86::SHL32rCL, X86::SHL32mCL },
151 { X86::SHL32ri, X86::SHL32mi },
152 { X86::SHL64rCL, X86::SHL64mCL },
153 { X86::SHL64ri, X86::SHL64mi },
154 { X86::SHL8rCL, X86::SHL8mCL },
155 { X86::SHL8ri, X86::SHL8mi },
156 { X86::SHLD16rrCL, X86::SHLD16mrCL },
157 { X86::SHLD16rri8, X86::SHLD16mri8 },
158 { X86::SHLD32rrCL, X86::SHLD32mrCL },
159 { X86::SHLD32rri8, X86::SHLD32mri8 },
160 { X86::SHLD64rrCL, X86::SHLD64mrCL },
161 { X86::SHLD64rri8, X86::SHLD64mri8 },
162 { X86::SHR16r1, X86::SHR16m1 },
163 { X86::SHR16rCL, X86::SHR16mCL },
164 { X86::SHR16ri, X86::SHR16mi },
165 { X86::SHR32r1, X86::SHR32m1 },
166 { X86::SHR32rCL, X86::SHR32mCL },
167 { X86::SHR32ri, X86::SHR32mi },
168 { X86::SHR64r1, X86::SHR64m1 },
169 { X86::SHR64rCL, X86::SHR64mCL },
170 { X86::SHR64ri, X86::SHR64mi },
171 { X86::SHR8r1, X86::SHR8m1 },
172 { X86::SHR8rCL, X86::SHR8mCL },
173 { X86::SHR8ri, X86::SHR8mi },
174 { X86::SHRD16rrCL, X86::SHRD16mrCL },
175 { X86::SHRD16rri8, X86::SHRD16mri8 },
176 { X86::SHRD32rrCL, X86::SHRD32mrCL },
177 { X86::SHRD32rri8, X86::SHRD32mri8 },
178 { X86::SHRD64rrCL, X86::SHRD64mrCL },
179 { X86::SHRD64rri8, X86::SHRD64mri8 },
180 { X86::SUB16ri, X86::SUB16mi },
181 { X86::SUB16ri8, X86::SUB16mi8 },
182 { X86::SUB16rr, X86::SUB16mr },
183 { X86::SUB32ri, X86::SUB32mi },
184 { X86::SUB32ri8, X86::SUB32mi8 },
185 { X86::SUB32rr, X86::SUB32mr },
186 { X86::SUB64ri32, X86::SUB64mi32 },
187 { X86::SUB64ri8, X86::SUB64mi8 },
188 { X86::SUB64rr, X86::SUB64mr },
189 { X86::SUB8ri, X86::SUB8mi },
190 { X86::SUB8rr, X86::SUB8mr },
191 { X86::XOR16ri, X86::XOR16mi },
192 { X86::XOR16ri8, X86::XOR16mi8 },
193 { X86::XOR16rr, X86::XOR16mr },
194 { X86::XOR32ri, X86::XOR32mi },
195 { X86::XOR32ri8, X86::XOR32mi8 },
196 { X86::XOR32rr, X86::XOR32mr },
197 { X86::XOR64ri32, X86::XOR64mi32 },
198 { X86::XOR64ri8, X86::XOR64mi8 },
199 { X86::XOR64rr, X86::XOR64mr },
200 { X86::XOR8ri, X86::XOR8mi },
201 { X86::XOR8rr, X86::XOR8mr }
204 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
205 unsigned RegOp = OpTbl2Addr[i][0];
206 unsigned MemOp = OpTbl2Addr[i][1];
207 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
208 assert(false && "Duplicated entries?");
209 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
210 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
211 std::make_pair(RegOp, AuxInfo))))
212 AmbEntries.push_back(MemOp);
215 // If the third value is 1, then it's folding either a load or a store.
216 static const unsigned OpTbl0[][3] = {
217 { X86::CALL32r, X86::CALL32m, 1 },
218 { X86::CALL64r, X86::CALL64m, 1 },
219 { X86::CMP16ri, X86::CMP16mi, 1 },
220 { X86::CMP16ri8, X86::CMP16mi8, 1 },
221 { X86::CMP32ri, X86::CMP32mi, 1 },
222 { X86::CMP32ri8, X86::CMP32mi8, 1 },
223 { X86::CMP64ri32, X86::CMP64mi32, 1 },
224 { X86::CMP64ri8, X86::CMP64mi8, 1 },
225 { X86::CMP8ri, X86::CMP8mi, 1 },
226 { X86::DIV16r, X86::DIV16m, 1 },
227 { X86::DIV32r, X86::DIV32m, 1 },
228 { X86::DIV64r, X86::DIV64m, 1 },
229 { X86::DIV8r, X86::DIV8m, 1 },
230 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
231 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
232 { X86::IDIV16r, X86::IDIV16m, 1 },
233 { X86::IDIV32r, X86::IDIV32m, 1 },
234 { X86::IDIV64r, X86::IDIV64m, 1 },
235 { X86::IDIV8r, X86::IDIV8m, 1 },
236 { X86::IMUL16r, X86::IMUL16m, 1 },
237 { X86::IMUL32r, X86::IMUL32m, 1 },
238 { X86::IMUL64r, X86::IMUL64m, 1 },
239 { X86::IMUL8r, X86::IMUL8m, 1 },
240 { X86::JMP32r, X86::JMP32m, 1 },
241 { X86::JMP64r, X86::JMP64m, 1 },
242 { X86::MOV16ri, X86::MOV16mi, 0 },
243 { X86::MOV16rr, X86::MOV16mr, 0 },
244 { X86::MOV16to16_, X86::MOV16_mr, 0 },
245 { X86::MOV32ri, X86::MOV32mi, 0 },
246 { X86::MOV32rr, X86::MOV32mr, 0 },
247 { X86::MOV32to32_, X86::MOV32_mr, 0 },
248 { X86::MOV64ri32, X86::MOV64mi32, 0 },
249 { X86::MOV64rr, X86::MOV64mr, 0 },
250 { X86::MOV8ri, X86::MOV8mi, 0 },
251 { X86::MOV8rr, X86::MOV8mr, 0 },
252 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
253 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
254 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
255 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
256 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
257 { X86::MOVSDrr, X86::MOVSDmr, 0 },
258 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
259 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
260 { X86::MOVSSrr, X86::MOVSSmr, 0 },
261 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
262 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
263 { X86::MUL16r, X86::MUL16m, 1 },
264 { X86::MUL32r, X86::MUL32m, 1 },
265 { X86::MUL64r, X86::MUL64m, 1 },
266 { X86::MUL8r, X86::MUL8m, 1 },
267 { X86::SETAEr, X86::SETAEm, 0 },
268 { X86::SETAr, X86::SETAm, 0 },
269 { X86::SETBEr, X86::SETBEm, 0 },
270 { X86::SETBr, X86::SETBm, 0 },
271 { X86::SETEr, X86::SETEm, 0 },
272 { X86::SETGEr, X86::SETGEm, 0 },
273 { X86::SETGr, X86::SETGm, 0 },
274 { X86::SETLEr, X86::SETLEm, 0 },
275 { X86::SETLr, X86::SETLm, 0 },
276 { X86::SETNEr, X86::SETNEm, 0 },
277 { X86::SETNPr, X86::SETNPm, 0 },
278 { X86::SETNSr, X86::SETNSm, 0 },
279 { X86::SETPr, X86::SETPm, 0 },
280 { X86::SETSr, X86::SETSm, 0 },
281 { X86::TAILJMPr, X86::TAILJMPm, 1 },
282 { X86::TEST16ri, X86::TEST16mi, 1 },
283 { X86::TEST32ri, X86::TEST32mi, 1 },
284 { X86::TEST64ri32, X86::TEST64mi32, 1 },
285 { X86::TEST8ri, X86::TEST8mi, 1 }
288 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
289 unsigned RegOp = OpTbl0[i][0];
290 unsigned MemOp = OpTbl0[i][1];
291 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
292 assert(false && "Duplicated entries?");
293 unsigned FoldedLoad = OpTbl0[i][2];
294 // Index 0, folded load or store.
295 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
296 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
297 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
298 std::make_pair(RegOp, AuxInfo))))
299 AmbEntries.push_back(MemOp);
302 static const unsigned OpTbl1[][2] = {
303 { X86::CMP16rr, X86::CMP16rm },
304 { X86::CMP32rr, X86::CMP32rm },
305 { X86::CMP64rr, X86::CMP64rm },
306 { X86::CMP8rr, X86::CMP8rm },
307 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
308 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
309 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
310 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
311 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
312 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
313 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
314 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
315 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
316 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
317 { X86::FsMOVAPDrr, X86::MOVSDrm },
318 { X86::FsMOVAPSrr, X86::MOVSSrm },
319 { X86::IMUL16rri, X86::IMUL16rmi },
320 { X86::IMUL16rri8, X86::IMUL16rmi8 },
321 { X86::IMUL32rri, X86::IMUL32rmi },
322 { X86::IMUL32rri8, X86::IMUL32rmi8 },
323 { X86::IMUL64rri32, X86::IMUL64rmi32 },
324 { X86::IMUL64rri8, X86::IMUL64rmi8 },
325 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
326 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
327 { X86::Int_COMISDrr, X86::Int_COMISDrm },
328 { X86::Int_COMISSrr, X86::Int_COMISSrm },
329 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
330 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
331 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
332 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
333 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
334 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
335 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
336 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
337 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
338 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
339 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
340 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
341 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
342 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
343 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
344 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
345 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
346 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
347 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
348 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
349 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
350 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
351 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
352 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
353 { X86::MOV16rr, X86::MOV16rm },
354 { X86::MOV16to16_, X86::MOV16_rm },
355 { X86::MOV32rr, X86::MOV32rm },
356 { X86::MOV32to32_, X86::MOV32_rm },
357 { X86::MOV64rr, X86::MOV64rm },
358 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
359 { X86::MOV64toSDrr, X86::MOV64toSDrm },
360 { X86::MOV8rr, X86::MOV8rm },
361 { X86::MOVAPDrr, X86::MOVAPDrm },
362 { X86::MOVAPSrr, X86::MOVAPSrm },
363 { X86::MOVDDUPrr, X86::MOVDDUPrm },
364 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
365 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
366 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
367 { X86::MOVSDrr, X86::MOVSDrm },
368 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
369 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
370 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
371 { X86::MOVSSrr, X86::MOVSSrm },
372 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
373 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
374 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
375 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
376 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
377 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
378 { X86::MOVUPDrr, X86::MOVUPDrm },
379 { X86::MOVUPSrr, X86::MOVUPSrm },
380 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
381 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
382 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
383 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
384 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
385 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
386 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
387 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
388 { X86::PSHUFDri, X86::PSHUFDmi },
389 { X86::PSHUFHWri, X86::PSHUFHWmi },
390 { X86::PSHUFLWri, X86::PSHUFLWmi },
391 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
392 { X86::RCPPSr, X86::RCPPSm },
393 { X86::RCPPSr_Int, X86::RCPPSm_Int },
394 { X86::RSQRTPSr, X86::RSQRTPSm },
395 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
396 { X86::RSQRTSSr, X86::RSQRTSSm },
397 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
398 { X86::SQRTPDr, X86::SQRTPDm },
399 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
400 { X86::SQRTPSr, X86::SQRTPSm },
401 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
402 { X86::SQRTSDr, X86::SQRTSDm },
403 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
404 { X86::SQRTSSr, X86::SQRTSSm },
405 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
406 { X86::TEST16rr, X86::TEST16rm },
407 { X86::TEST32rr, X86::TEST32rm },
408 { X86::TEST64rr, X86::TEST64rm },
409 { X86::TEST8rr, X86::TEST8rm },
410 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
411 { X86::UCOMISDrr, X86::UCOMISDrm },
412 { X86::UCOMISSrr, X86::UCOMISSrm }
415 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
416 unsigned RegOp = OpTbl1[i][0];
417 unsigned MemOp = OpTbl1[i][1];
418 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
419 assert(false && "Duplicated entries?");
420 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
421 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
422 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
423 std::make_pair(RegOp, AuxInfo))))
424 AmbEntries.push_back(MemOp);
427 static const unsigned OpTbl2[][2] = {
428 { X86::ADC32rr, X86::ADC32rm },
429 { X86::ADC64rr, X86::ADC64rm },
430 { X86::ADD16rr, X86::ADD16rm },
431 { X86::ADD32rr, X86::ADD32rm },
432 { X86::ADD64rr, X86::ADD64rm },
433 { X86::ADD8rr, X86::ADD8rm },
434 { X86::ADDPDrr, X86::ADDPDrm },
435 { X86::ADDPSrr, X86::ADDPSrm },
436 { X86::ADDSDrr, X86::ADDSDrm },
437 { X86::ADDSSrr, X86::ADDSSrm },
438 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
439 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
440 { X86::AND16rr, X86::AND16rm },
441 { X86::AND32rr, X86::AND32rm },
442 { X86::AND64rr, X86::AND64rm },
443 { X86::AND8rr, X86::AND8rm },
444 { X86::ANDNPDrr, X86::ANDNPDrm },
445 { X86::ANDNPSrr, X86::ANDNPSrm },
446 { X86::ANDPDrr, X86::ANDPDrm },
447 { X86::ANDPSrr, X86::ANDPSrm },
448 { X86::CMOVA16rr, X86::CMOVA16rm },
449 { X86::CMOVA32rr, X86::CMOVA32rm },
450 { X86::CMOVA64rr, X86::CMOVA64rm },
451 { X86::CMOVAE16rr, X86::CMOVAE16rm },
452 { X86::CMOVAE32rr, X86::CMOVAE32rm },
453 { X86::CMOVAE64rr, X86::CMOVAE64rm },
454 { X86::CMOVB16rr, X86::CMOVB16rm },
455 { X86::CMOVB32rr, X86::CMOVB32rm },
456 { X86::CMOVB64rr, X86::CMOVB64rm },
457 { X86::CMOVBE16rr, X86::CMOVBE16rm },
458 { X86::CMOVBE32rr, X86::CMOVBE32rm },
459 { X86::CMOVBE64rr, X86::CMOVBE64rm },
460 { X86::CMOVE16rr, X86::CMOVE16rm },
461 { X86::CMOVE32rr, X86::CMOVE32rm },
462 { X86::CMOVE64rr, X86::CMOVE64rm },
463 { X86::CMOVG16rr, X86::CMOVG16rm },
464 { X86::CMOVG32rr, X86::CMOVG32rm },
465 { X86::CMOVG64rr, X86::CMOVG64rm },
466 { X86::CMOVGE16rr, X86::CMOVGE16rm },
467 { X86::CMOVGE32rr, X86::CMOVGE32rm },
468 { X86::CMOVGE64rr, X86::CMOVGE64rm },
469 { X86::CMOVL16rr, X86::CMOVL16rm },
470 { X86::CMOVL32rr, X86::CMOVL32rm },
471 { X86::CMOVL64rr, X86::CMOVL64rm },
472 { X86::CMOVLE16rr, X86::CMOVLE16rm },
473 { X86::CMOVLE32rr, X86::CMOVLE32rm },
474 { X86::CMOVLE64rr, X86::CMOVLE64rm },
475 { X86::CMOVNE16rr, X86::CMOVNE16rm },
476 { X86::CMOVNE32rr, X86::CMOVNE32rm },
477 { X86::CMOVNE64rr, X86::CMOVNE64rm },
478 { X86::CMOVNP16rr, X86::CMOVNP16rm },
479 { X86::CMOVNP32rr, X86::CMOVNP32rm },
480 { X86::CMOVNP64rr, X86::CMOVNP64rm },
481 { X86::CMOVNS16rr, X86::CMOVNS16rm },
482 { X86::CMOVNS32rr, X86::CMOVNS32rm },
483 { X86::CMOVNS64rr, X86::CMOVNS64rm },
484 { X86::CMOVP16rr, X86::CMOVP16rm },
485 { X86::CMOVP32rr, X86::CMOVP32rm },
486 { X86::CMOVP64rr, X86::CMOVP64rm },
487 { X86::CMOVS16rr, X86::CMOVS16rm },
488 { X86::CMOVS32rr, X86::CMOVS32rm },
489 { X86::CMOVS64rr, X86::CMOVS64rm },
490 { X86::CMPPDrri, X86::CMPPDrmi },
491 { X86::CMPPSrri, X86::CMPPSrmi },
492 { X86::CMPSDrr, X86::CMPSDrm },
493 { X86::CMPSSrr, X86::CMPSSrm },
494 { X86::DIVPDrr, X86::DIVPDrm },
495 { X86::DIVPSrr, X86::DIVPSrm },
496 { X86::DIVSDrr, X86::DIVSDrm },
497 { X86::DIVSSrr, X86::DIVSSrm },
498 { X86::FsANDNPDrr, X86::FsANDNPDrm },
499 { X86::FsANDNPSrr, X86::FsANDNPSrm },
500 { X86::FsANDPDrr, X86::FsANDPDrm },
501 { X86::FsANDPSrr, X86::FsANDPSrm },
502 { X86::FsORPDrr, X86::FsORPDrm },
503 { X86::FsORPSrr, X86::FsORPSrm },
504 { X86::FsXORPDrr, X86::FsXORPDrm },
505 { X86::FsXORPSrr, X86::FsXORPSrm },
506 { X86::HADDPDrr, X86::HADDPDrm },
507 { X86::HADDPSrr, X86::HADDPSrm },
508 { X86::HSUBPDrr, X86::HSUBPDrm },
509 { X86::HSUBPSrr, X86::HSUBPSrm },
510 { X86::IMUL16rr, X86::IMUL16rm },
511 { X86::IMUL32rr, X86::IMUL32rm },
512 { X86::IMUL64rr, X86::IMUL64rm },
513 { X86::MAXPDrr, X86::MAXPDrm },
514 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
515 { X86::MAXPSrr, X86::MAXPSrm },
516 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
517 { X86::MAXSDrr, X86::MAXSDrm },
518 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
519 { X86::MAXSSrr, X86::MAXSSrm },
520 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
521 { X86::MINPDrr, X86::MINPDrm },
522 { X86::MINPDrr_Int, X86::MINPDrm_Int },
523 { X86::MINPSrr, X86::MINPSrm },
524 { X86::MINPSrr_Int, X86::MINPSrm_Int },
525 { X86::MINSDrr, X86::MINSDrm },
526 { X86::MINSDrr_Int, X86::MINSDrm_Int },
527 { X86::MINSSrr, X86::MINSSrm },
528 { X86::MINSSrr_Int, X86::MINSSrm_Int },
529 { X86::MULPDrr, X86::MULPDrm },
530 { X86::MULPSrr, X86::MULPSrm },
531 { X86::MULSDrr, X86::MULSDrm },
532 { X86::MULSSrr, X86::MULSSrm },
533 { X86::OR16rr, X86::OR16rm },
534 { X86::OR32rr, X86::OR32rm },
535 { X86::OR64rr, X86::OR64rm },
536 { X86::OR8rr, X86::OR8rm },
537 { X86::ORPDrr, X86::ORPDrm },
538 { X86::ORPSrr, X86::ORPSrm },
539 { X86::PACKSSDWrr, X86::PACKSSDWrm },
540 { X86::PACKSSWBrr, X86::PACKSSWBrm },
541 { X86::PACKUSWBrr, X86::PACKUSWBrm },
542 { X86::PADDBrr, X86::PADDBrm },
543 { X86::PADDDrr, X86::PADDDrm },
544 { X86::PADDQrr, X86::PADDQrm },
545 { X86::PADDSBrr, X86::PADDSBrm },
546 { X86::PADDSWrr, X86::PADDSWrm },
547 { X86::PADDWrr, X86::PADDWrm },
548 { X86::PANDNrr, X86::PANDNrm },
549 { X86::PANDrr, X86::PANDrm },
550 { X86::PAVGBrr, X86::PAVGBrm },
551 { X86::PAVGWrr, X86::PAVGWrm },
552 { X86::PCMPEQBrr, X86::PCMPEQBrm },
553 { X86::PCMPEQDrr, X86::PCMPEQDrm },
554 { X86::PCMPEQWrr, X86::PCMPEQWrm },
555 { X86::PCMPGTBrr, X86::PCMPGTBrm },
556 { X86::PCMPGTDrr, X86::PCMPGTDrm },
557 { X86::PCMPGTWrr, X86::PCMPGTWrm },
558 { X86::PINSRWrri, X86::PINSRWrmi },
559 { X86::PMADDWDrr, X86::PMADDWDrm },
560 { X86::PMAXSWrr, X86::PMAXSWrm },
561 { X86::PMAXUBrr, X86::PMAXUBrm },
562 { X86::PMINSWrr, X86::PMINSWrm },
563 { X86::PMINUBrr, X86::PMINUBrm },
564 { X86::PMULHUWrr, X86::PMULHUWrm },
565 { X86::PMULHWrr, X86::PMULHWrm },
566 { X86::PMULLWrr, X86::PMULLWrm },
567 { X86::PMULUDQrr, X86::PMULUDQrm },
568 { X86::PORrr, X86::PORrm },
569 { X86::PSADBWrr, X86::PSADBWrm },
570 { X86::PSLLDrr, X86::PSLLDrm },
571 { X86::PSLLQrr, X86::PSLLQrm },
572 { X86::PSLLWrr, X86::PSLLWrm },
573 { X86::PSRADrr, X86::PSRADrm },
574 { X86::PSRAWrr, X86::PSRAWrm },
575 { X86::PSRLDrr, X86::PSRLDrm },
576 { X86::PSRLQrr, X86::PSRLQrm },
577 { X86::PSRLWrr, X86::PSRLWrm },
578 { X86::PSUBBrr, X86::PSUBBrm },
579 { X86::PSUBDrr, X86::PSUBDrm },
580 { X86::PSUBSBrr, X86::PSUBSBrm },
581 { X86::PSUBSWrr, X86::PSUBSWrm },
582 { X86::PSUBWrr, X86::PSUBWrm },
583 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
584 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
585 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
586 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
587 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
588 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
589 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
590 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
591 { X86::PXORrr, X86::PXORrm },
592 { X86::SBB32rr, X86::SBB32rm },
593 { X86::SBB64rr, X86::SBB64rm },
594 { X86::SHUFPDrri, X86::SHUFPDrmi },
595 { X86::SHUFPSrri, X86::SHUFPSrmi },
596 { X86::SUB16rr, X86::SUB16rm },
597 { X86::SUB32rr, X86::SUB32rm },
598 { X86::SUB64rr, X86::SUB64rm },
599 { X86::SUB8rr, X86::SUB8rm },
600 { X86::SUBPDrr, X86::SUBPDrm },
601 { X86::SUBPSrr, X86::SUBPSrm },
602 { X86::SUBSDrr, X86::SUBSDrm },
603 { X86::SUBSSrr, X86::SUBSSrm },
604 // FIXME: TEST*rr -> swapped operand of TEST*mr.
605 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
606 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
607 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
608 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
609 { X86::XOR16rr, X86::XOR16rm },
610 { X86::XOR32rr, X86::XOR32rm },
611 { X86::XOR64rr, X86::XOR64rm },
612 { X86::XOR8rr, X86::XOR8rm },
613 { X86::XORPDrr, X86::XORPDrm },
614 { X86::XORPSrr, X86::XORPSrm }
617 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
618 unsigned RegOp = OpTbl2[i][0];
619 unsigned MemOp = OpTbl2[i][1];
620 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
621 assert(false && "Duplicated entries?");
622 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
623 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
624 std::make_pair(RegOp, AuxInfo))))
625 AmbEntries.push_back(MemOp);
628 // Remove ambiguous entries.
629 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
632 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
634 unsigned& destReg) const {
635 unsigned oc = MI.getOpcode();
636 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
637 oc == X86::MOV32rr || oc == X86::MOV64rr ||
638 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
639 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
640 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
641 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
642 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
643 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
644 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
645 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
646 assert(MI.getNumOperands() >= 2 &&
647 MI.getOperand(0).isRegister() &&
648 MI.getOperand(1).isRegister() &&
649 "invalid register-register move instruction");
650 sourceReg = MI.getOperand(1).getReg();
651 destReg = MI.getOperand(0).getReg();
657 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
658 int &FrameIndex) const {
659 switch (MI->getOpcode()) {
672 case X86::MMX_MOVD64rm:
673 case X86::MMX_MOVQ64rm:
674 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
675 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
676 MI->getOperand(2).getImm() == 1 &&
677 MI->getOperand(3).getReg() == 0 &&
678 MI->getOperand(4).getImm() == 0) {
679 FrameIndex = MI->getOperand(1).getIndex();
680 return MI->getOperand(0).getReg();
687 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
688 int &FrameIndex) const {
689 switch (MI->getOpcode()) {
702 case X86::MMX_MOVD64mr:
703 case X86::MMX_MOVQ64mr:
704 case X86::MMX_MOVNTQmr:
705 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
706 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
707 MI->getOperand(1).getImm() == 1 &&
708 MI->getOperand(2).getReg() == 0 &&
709 MI->getOperand(3).getImm() == 0) {
710 FrameIndex = MI->getOperand(0).getIndex();
711 return MI->getOperand(4).getReg();
719 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
720 switch (MI->getOpcode()) {
733 case X86::MMX_MOVD64rm:
734 case X86::MMX_MOVQ64rm:
735 // Loads from constant pools are trivially rematerializable.
736 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
737 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
738 MI->getOperand(1).getReg() == 0 &&
739 MI->getOperand(2).getImm() == 1 &&
740 MI->getOperand(3).getReg() == 0)
743 // If this is a load from a fixed argument slot, we know the value is
744 // invariant across the whole function, because we don't redefine argument
747 // FIXME: This is disabled due to a remat bug. rdar://5671644
748 if (MI->getOperand(1).isFI()) {
749 const MachineFrameInfo &MFI=*MI->getParent()->getParent()->getFrameInfo();
750 int Idx = MI->getOperand(1).getIndex();
751 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
757 // All other instructions marked M_REMATERIALIZABLE are always trivially
762 /// isInvariantLoad - Return true if the specified instruction (which is marked
763 /// mayLoad) is loading from a location whose value is invariant across the
764 /// function. For example, loading a value from the constant pool or from
765 /// from the argument area of a function if it does not change. This should
766 /// only return true of *all* loads the instruction does are invariant (if it
767 /// does multiple loads).
768 bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
769 // This code cares about loads from three cases: constant pool entries,
770 // invariant argument slots, and global stubs. In order to handle these cases
771 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
772 // operand and base our analysis on it. This is safe because the address of
773 // none of these three cases is ever used as anything other than a load base
774 // and X86 doesn't have any instructions that load from multiple places.
776 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
777 const MachineOperand &MO = MI->getOperand(i);
778 // Loads from constant pools are trivially invariant.
783 if (TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(MO.getGlobal(),
789 // If this is a load from an invariant stack slot, the load is a constant.
791 const MachineFrameInfo &MFI =
792 *MI->getParent()->getParent()->getFrameInfo();
793 int Idx = MO.getIndex();
794 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
798 // All other instances of these instructions are presumed to have other
803 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
804 /// is not marked dead.
805 static bool hasLiveCondCodeDef(MachineInstr *MI) {
806 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
807 MachineOperand &MO = MI->getOperand(i);
808 if (MO.isRegister() && MO.isDef() &&
809 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
816 /// convertToThreeAddress - This method must be implemented by targets that
817 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
818 /// may be able to convert a two-address instruction into a true
819 /// three-address instruction on demand. This allows the X86 target (for
820 /// example) to convert ADD and SHL instructions into LEA instructions if they
821 /// would require register copies due to two-addressness.
823 /// This method returns a null pointer if the transformation cannot be
824 /// performed, otherwise it returns the new instruction.
827 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
828 MachineBasicBlock::iterator &MBBI,
829 LiveVariables &LV) const {
830 MachineInstr *MI = MBBI;
831 // All instructions input are two-addr instructions. Get the known operands.
832 unsigned Dest = MI->getOperand(0).getReg();
833 unsigned Src = MI->getOperand(1).getReg();
835 MachineInstr *NewMI = NULL;
836 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
837 // we have better subtarget support, enable the 16-bit LEA generation here.
838 bool DisableLEA16 = true;
840 unsigned MIOpc = MI->getOpcode();
842 case X86::SHUFPSrri: {
843 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
844 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
846 unsigned A = MI->getOperand(0).getReg();
847 unsigned B = MI->getOperand(1).getReg();
848 unsigned C = MI->getOperand(2).getReg();
849 unsigned M = MI->getOperand(3).getImm();
850 if (B != C) return 0;
851 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
855 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
856 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
857 // the flags produced by a shift yet, so this is safe.
858 unsigned Dest = MI->getOperand(0).getReg();
859 unsigned Src = MI->getOperand(1).getReg();
860 unsigned ShAmt = MI->getOperand(2).getImm();
861 if (ShAmt == 0 || ShAmt >= 4) return 0;
863 NewMI = BuildMI(get(X86::LEA64r), Dest)
864 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
868 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
869 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
870 // the flags produced by a shift yet, so this is safe.
871 unsigned Dest = MI->getOperand(0).getReg();
872 unsigned Src = MI->getOperand(1).getReg();
873 unsigned ShAmt = MI->getOperand(2).getImm();
874 if (ShAmt == 0 || ShAmt >= 4) return 0;
876 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
877 X86::LEA64_32r : X86::LEA32r;
878 NewMI = BuildMI(get(Opc), Dest)
879 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
883 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
884 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
885 // the flags produced by a shift yet, so this is safe.
886 unsigned Dest = MI->getOperand(0).getReg();
887 unsigned Src = MI->getOperand(1).getReg();
888 unsigned ShAmt = MI->getOperand(2).getImm();
889 if (ShAmt == 0 || ShAmt >= 4) return 0;
892 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
893 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
894 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
895 ? X86::LEA64_32r : X86::LEA32r;
896 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
897 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
900 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
901 Ins->copyKillDeadInfo(MI);
903 NewMI = BuildMI(get(Opc), leaOutReg)
904 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
907 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
908 Ext->copyKillDeadInfo(MI);
910 MFI->insert(MBBI, Ins); // Insert the insert_subreg
911 LV.instructionChanged(MI, NewMI); // Update live variables
912 LV.addVirtualRegisterKilled(leaInReg, NewMI);
913 MFI->insert(MBBI, NewMI); // Insert the new inst
914 LV.addVirtualRegisterKilled(leaOutReg, Ext);
915 MFI->insert(MBBI, Ext); // Insert the extract_subreg
918 NewMI = BuildMI(get(X86::LEA16r), Dest)
919 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
924 // The following opcodes also sets the condition code register(s). Only
925 // convert them to equivalent lea if the condition code register def's
927 if (hasLiveCondCodeDef(MI))
930 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
935 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
936 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
937 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
938 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
943 if (DisableLEA16) return 0;
944 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
945 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
949 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
950 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
951 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
952 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
957 if (DisableLEA16) return 0;
958 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
959 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
963 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
964 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
965 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
966 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
967 MI->getOperand(2).getReg());
971 if (DisableLEA16) return 0;
972 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
973 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
974 MI->getOperand(2).getReg());
978 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
979 if (MI->getOperand(2).isImmediate())
980 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
981 MI->getOperand(2).getImm());
985 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
986 if (MI->getOperand(2).isImmediate()) {
987 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
988 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
989 MI->getOperand(2).getImm());
994 if (DisableLEA16) return 0;
995 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
996 if (MI->getOperand(2).isImmediate())
997 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
998 MI->getOperand(2).getImm());
1001 if (DisableLEA16) return 0;
1003 case X86::SHL64ri: {
1004 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
1005 "Unknown shl instruction!");
1006 unsigned ShAmt = MI->getOperand(2).getImm();
1007 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1009 AM.Scale = 1 << ShAmt;
1011 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1012 : (MIOpc == X86::SHL32ri
1013 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1014 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
1022 if (!NewMI) return 0;
1024 NewMI->copyKillDeadInfo(MI);
1025 LV.instructionChanged(MI, NewMI); // Update live variables
1026 MFI->insert(MBBI, NewMI); // Insert the new inst
1030 /// commuteInstruction - We have a few instructions that must be hacked on to
1033 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
1034 switch (MI->getOpcode()) {
1035 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1036 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1037 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1038 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1039 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1040 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1043 switch (MI->getOpcode()) {
1044 default: assert(0 && "Unreachable!");
1045 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1046 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1047 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1048 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1049 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1050 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1052 unsigned Amt = MI->getOperand(3).getImm();
1053 unsigned A = MI->getOperand(0).getReg();
1054 unsigned B = MI->getOperand(1).getReg();
1055 unsigned C = MI->getOperand(2).getReg();
1056 bool BisKill = MI->getOperand(1).isKill();
1057 bool CisKill = MI->getOperand(2).isKill();
1058 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
1059 .addReg(B, false, false, BisKill).addImm(Size-Amt);
1061 case X86::CMOVB16rr:
1062 case X86::CMOVB32rr:
1063 case X86::CMOVB64rr:
1064 case X86::CMOVAE16rr:
1065 case X86::CMOVAE32rr:
1066 case X86::CMOVAE64rr:
1067 case X86::CMOVE16rr:
1068 case X86::CMOVE32rr:
1069 case X86::CMOVE64rr:
1070 case X86::CMOVNE16rr:
1071 case X86::CMOVNE32rr:
1072 case X86::CMOVNE64rr:
1073 case X86::CMOVBE16rr:
1074 case X86::CMOVBE32rr:
1075 case X86::CMOVBE64rr:
1076 case X86::CMOVA16rr:
1077 case X86::CMOVA32rr:
1078 case X86::CMOVA64rr:
1079 case X86::CMOVL16rr:
1080 case X86::CMOVL32rr:
1081 case X86::CMOVL64rr:
1082 case X86::CMOVGE16rr:
1083 case X86::CMOVGE32rr:
1084 case X86::CMOVGE64rr:
1085 case X86::CMOVLE16rr:
1086 case X86::CMOVLE32rr:
1087 case X86::CMOVLE64rr:
1088 case X86::CMOVG16rr:
1089 case X86::CMOVG32rr:
1090 case X86::CMOVG64rr:
1091 case X86::CMOVS16rr:
1092 case X86::CMOVS32rr:
1093 case X86::CMOVS64rr:
1094 case X86::CMOVNS16rr:
1095 case X86::CMOVNS32rr:
1096 case X86::CMOVNS64rr:
1097 case X86::CMOVP16rr:
1098 case X86::CMOVP32rr:
1099 case X86::CMOVP64rr:
1100 case X86::CMOVNP16rr:
1101 case X86::CMOVNP32rr:
1102 case X86::CMOVNP64rr: {
1104 switch (MI->getOpcode()) {
1106 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1107 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1108 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1109 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1110 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1111 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1112 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1113 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1114 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1115 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1116 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1117 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1118 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1119 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1120 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1121 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1122 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1123 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1124 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1125 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1126 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1127 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1128 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1129 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1130 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1131 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1132 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1133 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1134 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1135 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1136 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1137 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1138 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1139 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1140 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1141 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1142 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1143 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1144 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1145 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1146 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1147 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1150 MI->setDesc(get(Opc));
1151 // Fallthrough intended.
1154 return TargetInstrInfoImpl::commuteInstruction(MI);
1158 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1160 default: return X86::COND_INVALID;
1161 case X86::JE: return X86::COND_E;
1162 case X86::JNE: return X86::COND_NE;
1163 case X86::JL: return X86::COND_L;
1164 case X86::JLE: return X86::COND_LE;
1165 case X86::JG: return X86::COND_G;
1166 case X86::JGE: return X86::COND_GE;
1167 case X86::JB: return X86::COND_B;
1168 case X86::JBE: return X86::COND_BE;
1169 case X86::JA: return X86::COND_A;
1170 case X86::JAE: return X86::COND_AE;
1171 case X86::JS: return X86::COND_S;
1172 case X86::JNS: return X86::COND_NS;
1173 case X86::JP: return X86::COND_P;
1174 case X86::JNP: return X86::COND_NP;
1175 case X86::JO: return X86::COND_O;
1176 case X86::JNO: return X86::COND_NO;
1180 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1182 default: assert(0 && "Illegal condition code!");
1183 case X86::COND_E: return X86::JE;
1184 case X86::COND_NE: return X86::JNE;
1185 case X86::COND_L: return X86::JL;
1186 case X86::COND_LE: return X86::JLE;
1187 case X86::COND_G: return X86::JG;
1188 case X86::COND_GE: return X86::JGE;
1189 case X86::COND_B: return X86::JB;
1190 case X86::COND_BE: return X86::JBE;
1191 case X86::COND_A: return X86::JA;
1192 case X86::COND_AE: return X86::JAE;
1193 case X86::COND_S: return X86::JS;
1194 case X86::COND_NS: return X86::JNS;
1195 case X86::COND_P: return X86::JP;
1196 case X86::COND_NP: return X86::JNP;
1197 case X86::COND_O: return X86::JO;
1198 case X86::COND_NO: return X86::JNO;
1202 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1203 /// e.g. turning COND_E to COND_NE.
1204 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1206 default: assert(0 && "Illegal condition code!");
1207 case X86::COND_E: return X86::COND_NE;
1208 case X86::COND_NE: return X86::COND_E;
1209 case X86::COND_L: return X86::COND_GE;
1210 case X86::COND_LE: return X86::COND_G;
1211 case X86::COND_G: return X86::COND_LE;
1212 case X86::COND_GE: return X86::COND_L;
1213 case X86::COND_B: return X86::COND_AE;
1214 case X86::COND_BE: return X86::COND_A;
1215 case X86::COND_A: return X86::COND_BE;
1216 case X86::COND_AE: return X86::COND_B;
1217 case X86::COND_S: return X86::COND_NS;
1218 case X86::COND_NS: return X86::COND_S;
1219 case X86::COND_P: return X86::COND_NP;
1220 case X86::COND_NP: return X86::COND_P;
1221 case X86::COND_O: return X86::COND_NO;
1222 case X86::COND_NO: return X86::COND_O;
1226 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1227 const TargetInstrDesc &TID = MI->getDesc();
1228 if (!TID.isTerminator()) return false;
1230 // Conditional branch is a special case.
1231 if (TID.isBranch() && !TID.isBarrier())
1233 if (!TID.isPredicable())
1235 return !isPredicated(MI);
1238 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1239 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1240 const X86InstrInfo &TII) {
1241 if (MI->getOpcode() == X86::FP_REG_KILL)
1243 return TII.isUnpredicatedTerminator(MI);
1246 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1247 MachineBasicBlock *&TBB,
1248 MachineBasicBlock *&FBB,
1249 std::vector<MachineOperand> &Cond) const {
1250 // If the block has no terminators, it just falls into the block after it.
1251 MachineBasicBlock::iterator I = MBB.end();
1252 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
1255 // Get the last instruction in the block.
1256 MachineInstr *LastInst = I;
1258 // If there is only one terminator instruction, process it.
1259 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1260 if (!LastInst->getDesc().isBranch())
1263 // If the block ends with a branch there are 3 possibilities:
1264 // it's an unconditional, conditional, or indirect branch.
1266 if (LastInst->getOpcode() == X86::JMP) {
1267 TBB = LastInst->getOperand(0).getMBB();
1270 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
1271 if (BranchCode == X86::COND_INVALID)
1272 return true; // Can't handle indirect branch.
1274 // Otherwise, block ends with fall-through condbranch.
1275 TBB = LastInst->getOperand(0).getMBB();
1276 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1280 // Get the instruction before it if it's a terminator.
1281 MachineInstr *SecondLastInst = I;
1283 // If there are three terminators, we don't know what sort of block this is.
1284 if (SecondLastInst && I != MBB.begin() &&
1285 isBrAnalysisUnpredicatedTerminator(--I, *this))
1288 // If the block ends with X86::JMP and a conditional branch, handle it.
1289 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
1290 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
1291 TBB = SecondLastInst->getOperand(0).getMBB();
1292 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1293 FBB = LastInst->getOperand(0).getMBB();
1297 // If the block ends with two X86::JMPs, handle it. The second one is not
1298 // executed, so remove it.
1299 if (SecondLastInst->getOpcode() == X86::JMP &&
1300 LastInst->getOpcode() == X86::JMP) {
1301 TBB = SecondLastInst->getOperand(0).getMBB();
1303 I->eraseFromParent();
1307 // Otherwise, can't handle this.
1311 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1312 MachineBasicBlock::iterator I = MBB.end();
1313 if (I == MBB.begin()) return 0;
1315 if (I->getOpcode() != X86::JMP &&
1316 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1319 // Remove the branch.
1320 I->eraseFromParent();
1324 if (I == MBB.begin()) return 1;
1326 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1329 // Remove the branch.
1330 I->eraseFromParent();
1334 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1335 MachineOperand &MO) {
1336 if (MO.isRegister())
1337 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1338 false, false, MO.getSubReg());
1339 else if (MO.isImmediate())
1340 MIB = MIB.addImm(MO.getImm());
1341 else if (MO.isFrameIndex())
1342 MIB = MIB.addFrameIndex(MO.getIndex());
1343 else if (MO.isGlobalAddress())
1344 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1345 else if (MO.isConstantPoolIndex())
1346 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1347 else if (MO.isJumpTableIndex())
1348 MIB = MIB.addJumpTableIndex(MO.getIndex());
1349 else if (MO.isExternalSymbol())
1350 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1352 assert(0 && "Unknown operand for X86InstrAddOperand!");
1358 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1359 MachineBasicBlock *FBB,
1360 const std::vector<MachineOperand> &Cond) const {
1361 // Shouldn't be a fall through.
1362 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1363 assert((Cond.size() == 1 || Cond.size() == 0) &&
1364 "X86 branch conditions have one component!");
1366 if (FBB == 0) { // One way branch.
1368 // Unconditional branch?
1369 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1371 // Conditional branch.
1372 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1373 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1378 // Two-way Conditional branch.
1379 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1380 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1381 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1385 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1386 MachineBasicBlock::iterator MI,
1387 unsigned DestReg, unsigned SrcReg,
1388 const TargetRegisterClass *DestRC,
1389 const TargetRegisterClass *SrcRC) const {
1390 if (DestRC != SrcRC) {
1391 // Moving EFLAGS to / from another register requires a push and a pop.
1392 if (SrcRC == &X86::CCRRegClass) {
1393 assert(SrcReg == X86::EFLAGS);
1394 if (DestRC == &X86::GR64RegClass) {
1395 BuildMI(MBB, MI, get(X86::PUSHFQ));
1396 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1398 } else if (DestRC == &X86::GR32RegClass) {
1399 BuildMI(MBB, MI, get(X86::PUSHFD));
1400 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1403 } else if (DestRC == &X86::CCRRegClass) {
1404 assert(DestReg == X86::EFLAGS);
1405 if (SrcRC == &X86::GR64RegClass) {
1406 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1407 BuildMI(MBB, MI, get(X86::POPFQ));
1409 } else if (SrcRC == &X86::GR32RegClass) {
1410 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1411 BuildMI(MBB, MI, get(X86::POPFD));
1415 cerr << "Not yet supported!";
1420 if (DestRC == &X86::GR64RegClass) {
1422 } else if (DestRC == &X86::GR32RegClass) {
1424 } else if (DestRC == &X86::GR16RegClass) {
1426 } else if (DestRC == &X86::GR8RegClass) {
1428 } else if (DestRC == &X86::GR32_RegClass) {
1429 Opc = X86::MOV32_rr;
1430 } else if (DestRC == &X86::GR16_RegClass) {
1431 Opc = X86::MOV16_rr;
1432 } else if (DestRC == &X86::RFP32RegClass) {
1433 Opc = X86::MOV_Fp3232;
1434 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1435 Opc = X86::MOV_Fp6464;
1436 } else if (DestRC == &X86::RFP80RegClass) {
1437 Opc = X86::MOV_Fp8080;
1438 } else if (DestRC == &X86::FR32RegClass) {
1439 Opc = X86::FsMOVAPSrr;
1440 } else if (DestRC == &X86::FR64RegClass) {
1441 Opc = X86::FsMOVAPDrr;
1442 } else if (DestRC == &X86::VR128RegClass) {
1443 Opc = X86::MOVAPSrr;
1444 } else if (DestRC == &X86::VR64RegClass) {
1445 Opc = X86::MMX_MOVQ64rr;
1447 assert(0 && "Unknown regclass");
1450 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1453 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1454 unsigned StackAlign) {
1456 if (RC == &X86::GR64RegClass) {
1458 } else if (RC == &X86::GR32RegClass) {
1460 } else if (RC == &X86::GR16RegClass) {
1462 } else if (RC == &X86::GR8RegClass) {
1464 } else if (RC == &X86::GR32_RegClass) {
1465 Opc = X86::MOV32_mr;
1466 } else if (RC == &X86::GR16_RegClass) {
1467 Opc = X86::MOV16_mr;
1468 } else if (RC == &X86::RFP80RegClass) {
1469 Opc = X86::ST_FpP80m; // pops
1470 } else if (RC == &X86::RFP64RegClass) {
1471 Opc = X86::ST_Fp64m;
1472 } else if (RC == &X86::RFP32RegClass) {
1473 Opc = X86::ST_Fp32m;
1474 } else if (RC == &X86::FR32RegClass) {
1476 } else if (RC == &X86::FR64RegClass) {
1478 } else if (RC == &X86::VR128RegClass) {
1479 // FIXME: Use movaps once we are capable of selectively
1480 // aligning functions that spill SSE registers on 16-byte boundaries.
1481 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
1482 } else if (RC == &X86::VR64RegClass) {
1483 Opc = X86::MMX_MOVQ64mr;
1485 assert(0 && "Unknown regclass");
1492 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1493 MachineBasicBlock::iterator MI,
1494 unsigned SrcReg, bool isKill, int FrameIdx,
1495 const TargetRegisterClass *RC) const {
1496 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1497 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1498 .addReg(SrcReg, false, false, isKill);
1501 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1503 SmallVectorImpl<MachineOperand> &Addr,
1504 const TargetRegisterClass *RC,
1505 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1506 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1507 MachineInstrBuilder MIB = BuildMI(get(Opc));
1508 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1509 MIB = X86InstrAddOperand(MIB, Addr[i]);
1510 MIB.addReg(SrcReg, false, false, isKill);
1511 NewMIs.push_back(MIB);
1514 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1515 unsigned StackAlign) {
1517 if (RC == &X86::GR64RegClass) {
1519 } else if (RC == &X86::GR32RegClass) {
1521 } else if (RC == &X86::GR16RegClass) {
1523 } else if (RC == &X86::GR8RegClass) {
1525 } else if (RC == &X86::GR32_RegClass) {
1526 Opc = X86::MOV32_rm;
1527 } else if (RC == &X86::GR16_RegClass) {
1528 Opc = X86::MOV16_rm;
1529 } else if (RC == &X86::RFP80RegClass) {
1530 Opc = X86::LD_Fp80m;
1531 } else if (RC == &X86::RFP64RegClass) {
1532 Opc = X86::LD_Fp64m;
1533 } else if (RC == &X86::RFP32RegClass) {
1534 Opc = X86::LD_Fp32m;
1535 } else if (RC == &X86::FR32RegClass) {
1537 } else if (RC == &X86::FR64RegClass) {
1539 } else if (RC == &X86::VR128RegClass) {
1540 // FIXME: Use movaps once we are capable of selectively
1541 // aligning functions that spill SSE registers on 16-byte boundaries.
1542 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
1543 } else if (RC == &X86::VR64RegClass) {
1544 Opc = X86::MMX_MOVQ64rm;
1546 assert(0 && "Unknown regclass");
1553 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1554 MachineBasicBlock::iterator MI,
1555 unsigned DestReg, int FrameIdx,
1556 const TargetRegisterClass *RC) const{
1557 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1558 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1561 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1562 SmallVectorImpl<MachineOperand> &Addr,
1563 const TargetRegisterClass *RC,
1564 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1565 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1566 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
1567 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1568 MIB = X86InstrAddOperand(MIB, Addr[i]);
1569 NewMIs.push_back(MIB);
1572 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1573 MachineBasicBlock::iterator MI,
1574 const std::vector<CalleeSavedInfo> &CSI) const {
1578 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1579 unsigned SlotSize = is64Bit ? 8 : 4;
1581 MachineFunction &MF = *MBB.getParent();
1582 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1583 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1585 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1586 for (unsigned i = CSI.size(); i != 0; --i) {
1587 unsigned Reg = CSI[i-1].getReg();
1588 // Add the callee-saved register as live-in. It's killed at the spill.
1590 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1595 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1596 MachineBasicBlock::iterator MI,
1597 const std::vector<CalleeSavedInfo> &CSI) const {
1601 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1603 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1604 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1605 unsigned Reg = CSI[i].getReg();
1606 BuildMI(MBB, MI, get(Opc), Reg);
1611 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1612 SmallVector<MachineOperand,4> &MOs,
1613 MachineInstr *MI, const TargetInstrInfo &TII) {
1614 // Create the base instruction with the memory operand as the first part.
1615 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1616 MachineInstrBuilder MIB(NewMI);
1617 unsigned NumAddrOps = MOs.size();
1618 for (unsigned i = 0; i != NumAddrOps; ++i)
1619 MIB = X86InstrAddOperand(MIB, MOs[i]);
1620 if (NumAddrOps < 4) // FrameIndex only
1621 MIB.addImm(1).addReg(0).addImm(0);
1623 // Loop over the rest of the ri operands, converting them over.
1624 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1625 for (unsigned i = 0; i != NumOps; ++i) {
1626 MachineOperand &MO = MI->getOperand(i+2);
1627 MIB = X86InstrAddOperand(MIB, MO);
1629 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1630 MachineOperand &MO = MI->getOperand(i);
1631 MIB = X86InstrAddOperand(MIB, MO);
1636 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1637 SmallVector<MachineOperand,4> &MOs,
1638 MachineInstr *MI, const TargetInstrInfo &TII) {
1639 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1640 MachineInstrBuilder MIB(NewMI);
1642 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1643 MachineOperand &MO = MI->getOperand(i);
1645 assert(MO.isRegister() && "Expected to fold into reg operand!");
1646 unsigned NumAddrOps = MOs.size();
1647 for (unsigned i = 0; i != NumAddrOps; ++i)
1648 MIB = X86InstrAddOperand(MIB, MOs[i]);
1649 if (NumAddrOps < 4) // FrameIndex only
1650 MIB.addImm(1).addReg(0).addImm(0);
1652 MIB = X86InstrAddOperand(MIB, MO);
1658 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1659 SmallVector<MachineOperand,4> &MOs,
1661 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1663 unsigned NumAddrOps = MOs.size();
1664 for (unsigned i = 0; i != NumAddrOps; ++i)
1665 MIB = X86InstrAddOperand(MIB, MOs[i]);
1666 if (NumAddrOps < 4) // FrameIndex only
1667 MIB.addImm(1).addReg(0).addImm(0);
1668 return MIB.addImm(0);
1672 X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1673 SmallVector<MachineOperand,4> &MOs) const {
1674 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1675 bool isTwoAddrFold = false;
1676 unsigned NumOps = MI->getDesc().getNumOperands();
1677 bool isTwoAddr = NumOps > 1 &&
1678 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1680 MachineInstr *NewMI = NULL;
1681 // Folding a memory location into the two-address part of a two-address
1682 // instruction is different than folding it other places. It requires
1683 // replacing the *two* registers with the memory location.
1684 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1685 MI->getOperand(0).isRegister() &&
1686 MI->getOperand(1).isRegister() &&
1687 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1688 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1689 isTwoAddrFold = true;
1690 } else if (i == 0) { // If operand 0
1691 if (MI->getOpcode() == X86::MOV16r0)
1692 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1693 else if (MI->getOpcode() == X86::MOV32r0)
1694 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1695 else if (MI->getOpcode() == X86::MOV64r0)
1696 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1697 else if (MI->getOpcode() == X86::MOV8r0)
1698 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1700 NewMI->copyKillDeadInfo(MI);
1704 OpcodeTablePtr = &RegOp2MemOpTable0;
1705 } else if (i == 1) {
1706 OpcodeTablePtr = &RegOp2MemOpTable1;
1707 } else if (i == 2) {
1708 OpcodeTablePtr = &RegOp2MemOpTable2;
1711 // If table selected...
1712 if (OpcodeTablePtr) {
1713 // Find the Opcode to fuse
1714 DenseMap<unsigned*, unsigned>::iterator I =
1715 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1716 if (I != OpcodeTablePtr->end()) {
1718 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
1720 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1721 NewMI->copyKillDeadInfo(MI);
1727 if (PrintFailedFusing)
1728 cerr << "We failed to fuse operand " << i << *MI;
1733 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1735 SmallVectorImpl<unsigned> &Ops,
1736 int FrameIndex) const {
1737 // Check switch flag
1738 if (NoFusing) return NULL;
1740 const MachineFrameInfo *MFI = MF.getFrameInfo();
1741 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
1742 // FIXME: Move alignment requirement into tables?
1743 if (Alignment < 16) {
1744 switch (MI->getOpcode()) {
1746 // Not always safe to fold movsd into these instructions since their load
1747 // folding variants expects the address to be 16 byte aligned.
1748 case X86::FsANDNPDrr:
1749 case X86::FsANDNPSrr:
1750 case X86::FsANDPDrr:
1751 case X86::FsANDPSrr:
1754 case X86::FsXORPDrr:
1755 case X86::FsXORPSrr:
1760 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1761 unsigned NewOpc = 0;
1762 switch (MI->getOpcode()) {
1763 default: return NULL;
1764 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1765 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1766 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1767 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1769 // Change to CMPXXri r, 0 first.
1770 MI->setDesc(get(NewOpc));
1771 MI->getOperand(1).ChangeToImmediate(0);
1772 } else if (Ops.size() != 1)
1775 SmallVector<MachineOperand,4> MOs;
1776 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
1777 return foldMemoryOperand(MI, Ops[0], MOs);
1780 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1782 SmallVectorImpl<unsigned> &Ops,
1783 MachineInstr *LoadMI) const {
1784 // Check switch flag
1785 if (NoFusing) return NULL;
1787 unsigned Alignment = 0;
1788 for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) {
1789 const MemOperand &MRO = LoadMI->getMemOperand(i);
1790 unsigned Align = MRO.getAlignment();
1791 if (Align > Alignment)
1795 // FIXME: Move alignment requirement into tables?
1796 if (Alignment < 16) {
1797 switch (MI->getOpcode()) {
1799 // Not always safe to fold movsd into these instructions since their load
1800 // folding variants expects the address to be 16 byte aligned.
1801 case X86::FsANDNPDrr:
1802 case X86::FsANDNPSrr:
1803 case X86::FsANDPDrr:
1804 case X86::FsANDPSrr:
1807 case X86::FsXORPDrr:
1808 case X86::FsXORPSrr:
1813 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1814 unsigned NewOpc = 0;
1815 switch (MI->getOpcode()) {
1816 default: return NULL;
1817 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1818 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1819 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1820 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1822 // Change to CMPXXri r, 0 first.
1823 MI->setDesc(get(NewOpc));
1824 MI->getOperand(1).ChangeToImmediate(0);
1825 } else if (Ops.size() != 1)
1828 SmallVector<MachineOperand,4> MOs;
1829 unsigned NumOps = LoadMI->getDesc().getNumOperands();
1830 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1831 MOs.push_back(LoadMI->getOperand(i));
1832 return foldMemoryOperand(MI, Ops[0], MOs);
1836 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
1837 SmallVectorImpl<unsigned> &Ops) const {
1838 // Check switch flag
1839 if (NoFusing) return 0;
1841 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1842 switch (MI->getOpcode()) {
1843 default: return false;
1852 if (Ops.size() != 1)
1855 unsigned OpNum = Ops[0];
1856 unsigned Opc = MI->getOpcode();
1857 unsigned NumOps = MI->getDesc().getNumOperands();
1858 bool isTwoAddr = NumOps > 1 &&
1859 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1861 // Folding a memory location into the two-address part of a two-address
1862 // instruction is different than folding it other places. It requires
1863 // replacing the *two* registers with the memory location.
1864 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1865 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1866 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1867 } else if (OpNum == 0) { // If operand 0
1876 OpcodeTablePtr = &RegOp2MemOpTable0;
1877 } else if (OpNum == 1) {
1878 OpcodeTablePtr = &RegOp2MemOpTable1;
1879 } else if (OpNum == 2) {
1880 OpcodeTablePtr = &RegOp2MemOpTable2;
1883 if (OpcodeTablePtr) {
1884 // Find the Opcode to fuse
1885 DenseMap<unsigned*, unsigned>::iterator I =
1886 OpcodeTablePtr->find((unsigned*)Opc);
1887 if (I != OpcodeTablePtr->end())
1893 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1894 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1895 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1896 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1897 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1898 if (I == MemOp2RegOpTable.end())
1900 unsigned Opc = I->second.first;
1901 unsigned Index = I->second.second & 0xf;
1902 bool FoldedLoad = I->second.second & (1 << 4);
1903 bool FoldedStore = I->second.second & (1 << 5);
1904 if (UnfoldLoad && !FoldedLoad)
1906 UnfoldLoad &= FoldedLoad;
1907 if (UnfoldStore && !FoldedStore)
1909 UnfoldStore &= FoldedStore;
1911 const TargetInstrDesc &TID = get(Opc);
1912 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1913 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
1914 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
1915 SmallVector<MachineOperand,4> AddrOps;
1916 SmallVector<MachineOperand,2> BeforeOps;
1917 SmallVector<MachineOperand,2> AfterOps;
1918 SmallVector<MachineOperand,4> ImpOps;
1919 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1920 MachineOperand &Op = MI->getOperand(i);
1921 if (i >= Index && i < Index+4)
1922 AddrOps.push_back(Op);
1923 else if (Op.isRegister() && Op.isImplicit())
1924 ImpOps.push_back(Op);
1926 BeforeOps.push_back(Op);
1928 AfterOps.push_back(Op);
1931 // Emit the load instruction.
1933 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
1935 // Address operands cannot be marked isKill.
1936 for (unsigned i = 1; i != 5; ++i) {
1937 MachineOperand &MO = NewMIs[0]->getOperand(i);
1938 if (MO.isRegister())
1939 MO.setIsKill(false);
1944 // Emit the data processing instruction.
1945 MachineInstr *DataMI = new MachineInstr(TID, true);
1946 MachineInstrBuilder MIB(DataMI);
1949 MIB.addReg(Reg, true);
1950 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
1951 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
1954 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
1955 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
1956 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
1957 MachineOperand &MO = ImpOps[i];
1958 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
1960 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
1961 unsigned NewOpc = 0;
1962 switch (DataMI->getOpcode()) {
1964 case X86::CMP64ri32:
1968 MachineOperand &MO0 = DataMI->getOperand(0);
1969 MachineOperand &MO1 = DataMI->getOperand(1);
1970 if (MO1.getImm() == 0) {
1971 switch (DataMI->getOpcode()) {
1973 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
1974 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
1975 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
1976 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
1978 DataMI->setDesc(get(NewOpc));
1979 MO1.ChangeToRegister(MO0.getReg(), false);
1983 NewMIs.push_back(DataMI);
1985 // Emit the store instruction.
1987 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1988 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
1989 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
1990 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
1997 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1998 SmallVectorImpl<SDNode*> &NewNodes) const {
1999 if (!N->isTargetOpcode())
2002 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2003 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
2004 if (I == MemOp2RegOpTable.end())
2006 unsigned Opc = I->second.first;
2007 unsigned Index = I->second.second & 0xf;
2008 bool FoldedLoad = I->second.second & (1 << 4);
2009 bool FoldedStore = I->second.second & (1 << 5);
2010 const TargetInstrDesc &TID = get(Opc);
2011 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2012 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2013 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2014 std::vector<SDOperand> AddrOps;
2015 std::vector<SDOperand> BeforeOps;
2016 std::vector<SDOperand> AfterOps;
2017 unsigned NumOps = N->getNumOperands();
2018 for (unsigned i = 0; i != NumOps-1; ++i) {
2019 SDOperand Op = N->getOperand(i);
2020 if (i >= Index && i < Index+4)
2021 AddrOps.push_back(Op);
2023 BeforeOps.push_back(Op);
2025 AfterOps.push_back(Op);
2027 SDOperand Chain = N->getOperand(NumOps-1);
2028 AddrOps.push_back(Chain);
2030 // Emit the load instruction.
2033 MVT::ValueType VT = *RC->vt_begin();
2034 Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
2035 MVT::Other, &AddrOps[0], AddrOps.size());
2036 NewNodes.push_back(Load);
2039 // Emit the data processing instruction.
2040 std::vector<MVT::ValueType> VTs;
2041 const TargetRegisterClass *DstRC = 0;
2042 if (TID.getNumDefs() > 0) {
2043 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2044 DstRC = DstTOI.isLookupPtrRegClass()
2045 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2046 VTs.push_back(*DstRC->vt_begin());
2048 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2049 MVT::ValueType VT = N->getValueType(i);
2050 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2054 BeforeOps.push_back(SDOperand(Load, 0));
2055 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2056 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2057 NewNodes.push_back(NewNode);
2059 // Emit the store instruction.
2062 AddrOps.push_back(SDOperand(NewNode, 0));
2063 AddrOps.push_back(Chain);
2064 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()),
2065 MVT::Other, &AddrOps[0], AddrOps.size());
2066 NewNodes.push_back(Store);
2072 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2073 bool UnfoldLoad, bool UnfoldStore) const {
2074 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2075 MemOp2RegOpTable.find((unsigned*)Opc);
2076 if (I == MemOp2RegOpTable.end())
2078 bool FoldedLoad = I->second.second & (1 << 4);
2079 bool FoldedStore = I->second.second & (1 << 5);
2080 if (UnfoldLoad && !FoldedLoad)
2082 if (UnfoldStore && !FoldedStore)
2084 return I->second.first;
2087 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
2088 if (MBB.empty()) return false;
2090 switch (MBB.back().getOpcode()) {
2091 case X86::TCRETURNri:
2092 case X86::TCRETURNdi:
2093 case X86::RET: // Return.
2098 case X86::JMP: // Uncond branch.
2099 case X86::JMP32r: // Indirect branch.
2100 case X86::JMP64r: // Indirect branch (64-bit).
2101 case X86::JMP32m: // Indirect branch through mem.
2102 case X86::JMP64m: // Indirect branch through mem (64-bit).
2104 default: return false;
2109 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
2110 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2111 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
2115 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2116 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2117 if (Subtarget->is64Bit())
2118 return &X86::GR64RegClass;
2120 return &X86::GR32RegClass;